Home
last modified time | relevance | path

Searched +full:cs +full:- +full:1 (Results 1 – 25 of 1088) sorted by relevance

12345678910>>...44

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c4 * SPDX-License-Identifier: GPL-2.0
47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
60 * Args: freq - current sequence frequency
61 * dram_info - main struct
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
71 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
72 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
77 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
78 dpde_flag = 1; in ddr3_write_leveling_hw()
80 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c4 * SPDX-License-Identifier: GPL-2.0
45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
57 * Args: dram_info - main struct
58 * freq - current sequence frequency
66 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
67 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
70 reg = 1 << REG_DRAM_TRAINING_RL_OFFS; in ddr3_read_leveling_hw()
74 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c4 * SPDX-License-Identifier: GPL-2.0
33 #define SPD_MODULE_TYPE_RDIMM 1
52 #define SPD_MODULE_BANK_NUM_MIN 1
125 SD_CL_1 = 1,
197 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
199 * Args: dimm_addr - array of dimm addresses
212 dimm_cur_addr--) { in ddr3_get_dimm_num()
215 /* Far-End DIMM must be connected */ in ddr3_get_dimm_num()
219 ret = i2c_read(dimm_cur_addr, 0, 1, (uchar *)data, 3); in ddr3_get_dimm_num()
233 * Name: dimmSpdInit - Get the SPD parameters.
[all …]
/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0
30 1,
33 1,
34 1,
41 1,
48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
60 case 1: in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c4 * SPDX-License-Identifier: GPL-2.0
29 1,
32 1,
33 1,
40 1,
47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
30 #define FMC2_BCR_MUXEN BIT(1)
99 FMC2_REG_BCR = 1,
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
188 return -EINVAL; in stm32_fmc2_ebi_check_mux()
[all …]
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
78 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
94 * The first 1MB of GPMC address space is typically mapped to
135 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
136 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
83 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
85 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
86 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
H A Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
29 maxItems: 1
[all …]
/OK3568_Linux_fs/kernel/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include "tick-internal.h"
22 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
33 * NSEC_PER_SEC == 1GHz and @from is the counter frequency. For clock
56 tmp >>=1; in clocks_calc_mult_shift()
57 sftacc--; in clocks_calc_mult_shift()
64 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
76 /*[Clocksource internal variables]---------
86 * Name of the user-specified clocksource.
119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
[all …]
/OK3568_Linux_fs/kernel/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
30 #define FUSE_INT_REQ_BIT (1ULL << 0)
31 #define FUSE_REQ_ID_STEP (1ULL << 1)
38 * Lockless access is OK, because file->private data is set in fuse_get_dev()
41 return READ_ONCE(file->private_data); in fuse_get_dev()
46 INIT_LIST_HEAD(&req->list); in fuse_request_init()
47 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
48 init_waitqueue_head(&req->waitq); in fuse_request_init()
49 refcount_set(&req->count, 1); in fuse_request_init()
50 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
44 /* per-register bitmasks */
48 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
57 #define OMAP3_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
81 #define MCSPI_PINDIR_D0_OUT_D1_IN 1
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
107 /* channel2: 0x54 - 0x64, bus 0 & 1 */
[all …]
H A Dbcm63xx_hsspi.c4 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
5 * Copyright (C) 2000-2010 Broadcom Corporation
6 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
8 * SPDX-License-Identifier: GPL-2.0+
30 #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
32 #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
41 /* SPI Ping-Pong Command registers */
50 /* SPI Ping-Pong Status registers */
52 #define SPI_STAT_SRCBUSY_SHIFT 1
53 #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/OK3568_Linux_fs/external/xserver/composite/
H A Dcompinit.c45 #include <dix-config.h>
58 CompScreenPtr cs = GetCompScreen(pScreen); in compCloseScreen() local
61 free(cs->alternateVisuals); in compCloseScreen()
63 pScreen->CloseScreen = cs->CloseScreen; in compCloseScreen()
64 pScreen->InstallColormap = cs->InstallColormap; in compCloseScreen()
65 pScreen->ChangeWindowAttributes = cs->ChangeWindowAttributes; in compCloseScreen()
66 pScreen->ReparentWindow = cs->ReparentWindow; in compCloseScreen()
67 pScreen->ConfigNotify = cs->ConfigNotify; in compCloseScreen()
68 pScreen->MoveWindow = cs->MoveWindow; in compCloseScreen()
69 pScreen->ResizeWindow = cs->ResizeWindow; in compCloseScreen()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/kpc2000/
H A Dkpc2000_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
63 .bus_num = 1,
70 .bus_num = 1,
71 .chip_select = 1,
91 #define KP_SPI_REG_CONFIG_TRM_RX 1
119 unsigned int pha : 1; /* spim_clk Phase */
120 unsigned int pol : 1; /* spim_clk Polarity */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c4 * SPDX-License-Identifier: GPL-2.0
16 #include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
89 * Set 1 to use dynamic DUNIT configuration,
93 u8 generic_init_controller = 1;
112 * sys_env_device_rev_get - Get Marvell controller device revision number
162 * DESCRIPTION: Get bit mask of enabled CS
169 * Bit mask of enabled CS, 1 if only CS0 enabled,
187 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
191 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n", in ddr3_restore_and_set_final_windows()
198 u32 reg, cs; in ddr3_restore_and_set_final_windows() local
[all …]
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-fsl-spi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
50 #define TYPE_GRLIB 1
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
22 * SPDX-License-Identifier: GPL-2.0+
36 * is_mem_sdr -
37 * - Return 1 if mem type in use is SDR
41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
42 return 1; in is_mem_sdr()
47 * make_cs1_contiguous -
48 * - When we have CS1 populated we want to have it mapped after cs0 to allow
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/common/
H A Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
[all …]

12345678910>>...44