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/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_db.c43 { {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
45 { {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} },
47 { {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} },
49 { {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} },
51 { {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} },
53 { {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
55 { {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} },
57 { {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
59 { {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0}
61 { {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
[all …]
/rk3399_rockchip-uboot/arch/sh/lib/
H A Dudivsi3_i4i.S280 .rept 6
380 .byte -6
381 .byte -6
382 .byte -6
383 .byte -6
384 .byte -6
385 .byte -6
386 .byte -6
387 .byte -6
388 .byte -6
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/rk3399_rockchip-uboot/lib/avb/libavb/
H A Davb_sha256.c65 #define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
80 *((str) + 6) = (uint8_t)((uint64_t)x >> 8); \
146 ctx->h[6] = sha256_h0[6]; in avb_sha256_init()
168 sub_block = message + (i << 6); in SHA256_transform()
184 t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + in SHA256_transform()
187 wv[7] = wv[6]; in SHA256_transform()
188 wv[6] = wv[5]; in SHA256_transform()
207 PACK32(&sub_block[24], &w[6]); in SHA256_transform()
273 wv[6] = ctx->h[6]; in SHA256_transform()
276 SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, 0); in SHA256_transform()
[all …]
/rk3399_rockchip-uboot/include/
H A Dmc13892.h22 #define ICHRG3 (1 << 6)
46 #define VO_2_77V 6
51 #define VGEN 6
60 #define SWMODE_PWM_AUTO 6
87 #define VSD_1_8 (0 << 6)
88 #define VSD_2_0 (1 << 6)
89 #define VSD_2_6 (2 << 6)
90 #define VSD_2_7 (3 << 6)
91 #define VSD_2_8 (4 << 6)
92 #define VSD_2_9 (5 << 6)
[all …]
H A Dipu_pixfmt.h29 #define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
34 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
35 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
36 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
60 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Dmem.h43 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
64 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
97 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
112 #define HYNIX_TDAL_165 6
138 #define HYNIX_TDAL_200 6
164 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
165 /* 15/6 + 18/6 = 5.5 -> 6 */
166 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
167 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */
168 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */
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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsama5d2-pinfunc.h8 #define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2)
13 #define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2)
18 #define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2)
23 #define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2)
28 #define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2)
33 #define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2)
34 #define PIN_PA6 6
40 #define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2)
47 #define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2)
54 #define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2)
[all …]
H A Drv1126b-pinctrl.dtsi58 <6 RK_PA0 4 &pcfg_pull_none>,
60 <6 RK_PA1 4 &pcfg_pull_none>;
76 <6 RK_PA2 4 &pcfg_pull_none>,
78 <6 RK_PA3 4 &pcfg_pull_none>;
240 <6 RK_PB4 3 &pcfg_pull_none>,
242 <6 RK_PC0 3 &pcfg_pull_none>,
244 <6 RK_PB7 3 &pcfg_pull_none>,
246 <6 RK_PA2 3 &pcfg_pull_none>,
248 <6 RK_PA0 3 &pcfg_pull_none>,
250 <6 RK_PC3 3 &pcfg_pull_none>,
[all …]
H A Dstih407-pinctrl.dtsi157 tx = <&pio2 6 ALT3 OUT>;
166 sda = <&pio4 6 ALT1 BIDIR>;
187 keyin3 = <&pio2 6 ALT2 IN>;
189 keyout0 = <&pio4 6 ALT4 OUT>;
191 keyout2 = <&pio0 6 ALT2 OUT>;
213 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
216 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
248 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
257 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
310 pwm-out = <&pio4 6 ALT3 OUT>;
[all …]
H A Dimx6ul-pinfunc.h37 #define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0
44 #define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0
52 #define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0
59 #define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0
79 #define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0
88 #define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0
97 #define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0
106 #define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0
115 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0
124 #define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Dda8xx_gpio.c26 { pinmux(13), 8, 6 }, /* GP0[0] */
34 { pinmux(14), 8, 6 },
42 { pinmux(15), 8, 6 }, /* GP1[0] */
50 { pinmux(16), 8, 6 },
58 { pinmux(17), 8, 6 }, /* GP2[0] */
66 { pinmux(18), 8, 6 },
73 { pinmux(9), 8, 6 },
79 { pinmux(10), 8, 6 },
87 { pinmux(2), 8, 6 },
89 { pinmux(11), 8, 6 },
[all …]
/rk3399_rockchip-uboot/board/sunxi/
H A Ddram_timings_sun4i.h4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
5 .cas = 6,
10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
11 .cas = 6,
16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
17 .cas = 6,
22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
104 # if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc8568mds/
H A Dbcsr.h15 4:6 cfg core pll
21 6 PCI IO
27 6 cfg PCI arbiter
34 6 PHY1 slave
40 6 GETH transactive reset
47 6 UPC2 pos
50 * BCSR 6 *
53 6 Register config led
59 6 enable TSEC2 PHY
73 6 Ready only - indicate flash ready after burning
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h30 u32 ppll_con[6];
32 u32 pmucru_clksel[6];
46 u32 apll_l_con[6];
48 u32 apll_b_con[6];
50 u32 dpll_con[6];
52 u32 cpll_con[6];
54 u32 gpll_con[6];
56 u32 npll_con[6];
58 u32 vpll_con[6];
H A Ddram_spec_timing.h12 /* 6-6-6 */
14 /* 6-6-6 */
23 DDR3_1333G = 6,
69 DDR4_2133N = 6,
102 #define DDR3_RTT_NOM_MASK ((1 << 2) | (1 << 6) | (1 << 9))
105 #define DDR3_RTT_NOM_120 BIT(6)
106 #define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6))
172 #define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3))
203 #define LPDDR3_WL_SUPOT BIT(6)
249 #define LPDDR3_WL_S BIT(6)
[all …]
/rk3399_rockchip-uboot/board/boundary/nitrogen6x/
H A DREADME22 2. Boots using 6x_bootscript on SATA or SD card
25 to look for and source a boot script named '6x_bootscript'
42 '6x_upgrade' to upgrade the U-Boot version
44 6x_bootscript described above.
74 nitrogen6q i.MX6Q/6D 1GB
77 nitrogen6q2g i.MX6Q/6D 2GB
81 The -6q variants support either the i.MX6Quad or i.MX6Dual processors
84 The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
86 The -6s variants use a 32-bit memory bus at 800MHz.
89 along with a binary version of the boot script 6x_upgrade.txt,
/rk3399_rockchip-uboot/arch/nios2/lib/
H A Dlibgcc.c41 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h30 /*6 */
50 /*6 */
83 /*6 */
103 /*6 */
123 /*6 */
156 /*6 2 4 19 */
177 /*6 */
210 /*6 2 4 19 */
230 /*6 */
253 /*1 2 2 6 */
[all …]
/rk3399_rockchip-uboot/drivers/power/power_delivery/
H A Dfusb302_reg.h14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
23 #define FUSB_REG_SWITCHES1_SPECREV1 BIT(6)
31 #define FUSB_REG_MEASURE_MDAC4 BIT(6)
39 #define FUSB_REG_CONTROL0_TX_FLUSH BIT(6)
47 #define FUSB_REG_CONTROL1_ENSOP2DB BIT(6)
62 #define FUSB_REG_CONTROL3_SEND_HARDRESET BIT(6)
74 #define FUSB_REG_MASK_ACTIVITY BIT(6)
92 #define FUSB_REG_MASKA_TOGDONE BIT(6)
122 #define FUSB_REG_INTERRUPTA_TOGDONE BIT(6)
133 #define FUSB_REG_STATUS0_ACTIVITY BIT(6)
[all …]
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Dexynos7420-clk.h19 #define DOUT_ACLK_CCORE_133 6
43 #define CLK_SCLK_UART3 6
62 #define CLK_SCLK_MMC2 6
86 #define PCLK_HSI2C5 6
101 #define SCLK_UART3 6
131 #define PERIS_NR_CLK 6
139 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
152 #define ACLK_UFS20_LINK 6
170 #define ACLK_G2D 6
206 #define AUD_NR_CLK 6
H A Drockchip-ddr.h22 #define DDR3_800E (1) /* 6-6-6 */
23 #define DDR3_1066E (2) /* 6-6-6 */
27 #define DDR3_1333G (6) /* 8-8-8 */
53 #define DDR4_2133N (6) /* 14-14-14 */
/rk3399_rockchip-uboot/board/renesas/sh7757lcr/
H A DREADME.sh7757lcr50 => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
61 ETHERC ch0 = 00:00:87:6c:21:80
62 ETHERC ch1 = 00:00:87:6c:21:81
63 GETHERC ch0 = 00:00:87:6c:21:82
64 GETHERC ch1 = 00:00:87:6c:21:83
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mxs/
H A Diomux-mx28.h27 #define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
49 #define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
82 #define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
108 #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
139 #define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0)
158 #define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0)
178 #define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0)
179 #define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0)
180 #define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0)
181 #define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0)
[all …]
/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/
H A Dsdram-rv1126-loader_params.inc125 ((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) |
127 (((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) << 24),
130 (((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0)) << 16) |
131 (((0x3 << 6) | (0x0 << 4) | (0x2 << 2) | (0x1 << 0)) << 24),
133 (2 << 0) | (6 << 4) | (4 << 8) | (0 << 12) | (3 << 16) | (7 << 20) |
139 ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) |
140 ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) |
141 ((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) |
142 ((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24),
144 ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) |
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dda850_pinmux.c42 { pinmux(3), 2, 6 },
47 { pinmux(4), 2, 6 }, /* UART1_RXD */
57 { pinmux(0), 4, 6 }, /* UART2_RTS */
67 { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
79 { pinmux(2), 8, 6 }, /* MII_TXD[1] */
87 { pinmux(3), 8, 6 }, /* MII_RXD[1] */
124 { pinmux(9), 1, 1 }, /* EMA_D[6] */
129 { pinmux(9), 1, 6 }, /* EMA_D[1] */
132 { pinmux(12), 1, 6 }, /* EMA_A[1] */
137 { pinmux(5), 1, 6 }, /* EMA_BA[1] */
[all …]

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