1*593e1e6dSJoseph Chen /* 2*593e1e6dSJoseph Chen * 3*593e1e6dSJoseph Chen * Copyright (C) 2017 ROCKCHIP, Inc. 4*593e1e6dSJoseph Chen * 5*593e1e6dSJoseph Chen * This software is licensed under the terms of the GNU General Public 6*593e1e6dSJoseph Chen * License version 2, as published by the Free Software Foundation, and 7*593e1e6dSJoseph Chen * may be copied, distributed, and modified under those terms. 8*593e1e6dSJoseph Chen * 9*593e1e6dSJoseph Chen * This program is distributed in the hope that it will be useful, 10*593e1e6dSJoseph Chen * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*593e1e6dSJoseph Chen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*593e1e6dSJoseph Chen * GNU General Public License for more details. 13*593e1e6dSJoseph Chen * 14*593e1e6dSJoseph Chen */ 15*593e1e6dSJoseph Chen 16*593e1e6dSJoseph Chen #ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H 17*593e1e6dSJoseph Chen #define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H 18*593e1e6dSJoseph Chen 19*593e1e6dSJoseph Chen #define DDR2_DEFAULT (0) 20*593e1e6dSJoseph Chen 21*593e1e6dSJoseph Chen #define DDR3_800D (0) /* 5-5-5 */ 22*593e1e6dSJoseph Chen #define DDR3_800E (1) /* 6-6-6 */ 23*593e1e6dSJoseph Chen #define DDR3_1066E (2) /* 6-6-6 */ 24*593e1e6dSJoseph Chen #define DDR3_1066F (3) /* 7-7-7 */ 25*593e1e6dSJoseph Chen #define DDR3_1066G (4) /* 8-8-8 */ 26*593e1e6dSJoseph Chen #define DDR3_1333F (5) /* 7-7-7 */ 27*593e1e6dSJoseph Chen #define DDR3_1333G (6) /* 8-8-8 */ 28*593e1e6dSJoseph Chen #define DDR3_1333H (7) /* 9-9-9 */ 29*593e1e6dSJoseph Chen #define DDR3_1333J (8) /* 10-10-10 */ 30*593e1e6dSJoseph Chen #define DDR3_1600G (9) /* 8-8-8 */ 31*593e1e6dSJoseph Chen #define DDR3_1600H (10) /* 9-9-9 */ 32*593e1e6dSJoseph Chen #define DDR3_1600J (11) /* 10-10-10 */ 33*593e1e6dSJoseph Chen #define DDR3_1600K (12) /* 11-11-11 */ 34*593e1e6dSJoseph Chen #define DDR3_1866J (13) /* 10-10-10 */ 35*593e1e6dSJoseph Chen #define DDR3_1866K (14) /* 11-11-11 */ 36*593e1e6dSJoseph Chen #define DDR3_1866L (15) /* 12-12-12 */ 37*593e1e6dSJoseph Chen #define DDR3_1866M (16) /* 13-13-13 */ 38*593e1e6dSJoseph Chen #define DDR3_2133K (17) /* 11-11-11 */ 39*593e1e6dSJoseph Chen #define DDR3_2133L (18) /* 12-12-12 */ 40*593e1e6dSJoseph Chen #define DDR3_2133M (19) /* 13-13-13 */ 41*593e1e6dSJoseph Chen #define DDR3_2133N (20) /* 14-14-14 */ 42*593e1e6dSJoseph Chen #define DDR3_DEFAULT (21) 43*593e1e6dSJoseph Chen #define DDR_DDR2 (22) 44*593e1e6dSJoseph Chen #define DDR_LPDDR (23) 45*593e1e6dSJoseph Chen #define DDR_LPDDR2 (24) 46*593e1e6dSJoseph Chen 47*593e1e6dSJoseph Chen #define DDR4_1600J (0) /* 10-10-10 */ 48*593e1e6dSJoseph Chen #define DDR4_1600K (1) /* 11-11-11 */ 49*593e1e6dSJoseph Chen #define DDR4_1600L (2) /* 12-12-12 */ 50*593e1e6dSJoseph Chen #define DDR4_1866L (3) /* 12-12-12 */ 51*593e1e6dSJoseph Chen #define DDR4_1866M (4) /* 13-13-13 */ 52*593e1e6dSJoseph Chen #define DDR4_1866N (5) /* 14-14-14 */ 53*593e1e6dSJoseph Chen #define DDR4_2133N (6) /* 14-14-14 */ 54*593e1e6dSJoseph Chen #define DDR4_2133P (7) /* 15-15-15 */ 55*593e1e6dSJoseph Chen #define DDR4_2133R (8) /* 16-16-16 */ 56*593e1e6dSJoseph Chen #define DDR4_2400P (9) /* 15-15-15 */ 57*593e1e6dSJoseph Chen #define DDR4_2400R (10) /* 16-16-16 */ 58*593e1e6dSJoseph Chen #define DDR4_2400U (11) /* 18-18-18 */ 59*593e1e6dSJoseph Chen #define DDR4_DEFAULT (12) 60*593e1e6dSJoseph Chen 61*593e1e6dSJoseph Chen #define PAUSE_CPU_STACK_SIZE 16 62*593e1e6dSJoseph Chen 63*593e1e6dSJoseph Chen #endif 64