xref: /rk3399_rockchip-uboot/include/mc13892.h (revision 326ea986ac150acdc7656d57fca647db80b50158)
1d3588a55SStefano Babic /*
2d3588a55SStefano Babic  * (C) Copyright 2010
3d3588a55SStefano Babic  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4d3588a55SStefano Babic  *
5d3588a55SStefano Babic  * (C) Copyright 2009 Freescale Semiconductor, Inc.
6d3588a55SStefano Babic  *
7*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
8d3588a55SStefano Babic  */
9d3588a55SStefano Babic 
10d3588a55SStefano Babic 
11d3588a55SStefano Babic #ifndef __MC13892_H__
12d3588a55SStefano Babic #define __MC13892_H__
13d3588a55SStefano Babic 
14d3588a55SStefano Babic /* REG_CHARGE */
15d3588a55SStefano Babic 
16888b4f43SShawn Guo #define VCHRG0		(1 << 0)
17d3588a55SStefano Babic #define VCHRG1		(1 << 1)
18d3588a55SStefano Babic #define VCHRG2		(1 << 2)
19d3588a55SStefano Babic #define ICHRG0		(1 << 3)
20d3588a55SStefano Babic #define ICHRG1		(1 << 4)
21d3588a55SStefano Babic #define ICHRG2		(1 << 5)
22d3588a55SStefano Babic #define ICHRG3		(1 << 6)
23888b4f43SShawn Guo #define TREN		(1 << 7)
24888b4f43SShawn Guo #define ACKLPB		(1 << 8)
25888b4f43SShawn Guo #define THCHKB		(1 << 9)
26d3588a55SStefano Babic #define FETOVRD		(1 << 10)
27d3588a55SStefano Babic #define FETCTRL		(1 << 11)
28d3588a55SStefano Babic #define RVRSMODE	(1 << 13)
29888b4f43SShawn Guo #define PLIM0		(1 << 15)
30888b4f43SShawn Guo #define PLIM1		(1 << 16)
31888b4f43SShawn Guo #define PLIMDIS		(1 << 17)
32d3588a55SStefano Babic #define CHRGLEDEN	(1 << 18)
33888b4f43SShawn Guo #define CHGTMRRST	(1 << 19)
34d3588a55SStefano Babic #define CHGRESTART	(1 << 20)
35d3588a55SStefano Babic #define CHGAUTOB	(1 << 21)
36d3588a55SStefano Babic #define CYCLB		(1 << 22)
37d3588a55SStefano Babic #define CHGAUTOVIB	(1 << 23)
38d3588a55SStefano Babic 
39d3588a55SStefano Babic /* REG_SETTING_0/1 */
40d3588a55SStefano Babic #define VO_1_20V	0
41d3588a55SStefano Babic #define VO_1_30V	1
42d3588a55SStefano Babic #define VO_1_50V	2
43d3588a55SStefano Babic #define VO_1_80V	3
44d3588a55SStefano Babic #define VO_1_10V	4
45d3588a55SStefano Babic #define VO_2_00V	5
46d3588a55SStefano Babic #define VO_2_77V	6
47d3588a55SStefano Babic #define VO_2_40V	7
48d3588a55SStefano Babic 
49d3588a55SStefano Babic #define VIOL		2
50d3588a55SStefano Babic #define VDIG		4
51d3588a55SStefano Babic #define VGEN		6
52d3588a55SStefano Babic 
53d3588a55SStefano Babic /* SWxMode for Normal/Standby Mode */
54d3588a55SStefano Babic #define SWMODE_OFF_OFF		0
55d3588a55SStefano Babic #define SWMODE_PWM_OFF		1
56d3588a55SStefano Babic #define SWMODE_PWMPS_OFF	2
57d3588a55SStefano Babic #define SWMODE_PFM_OFF		3
58d3588a55SStefano Babic #define SWMODE_AUTO_OFF		4
59d3588a55SStefano Babic #define SWMODE_PWM_PWM		5
60d3588a55SStefano Babic #define SWMODE_PWM_AUTO		6
61d3588a55SStefano Babic #define SWMODE_AUTO_AUTO	8
62d3588a55SStefano Babic #define SWMODE_PWM_PWMPS	9
63d3588a55SStefano Babic #define SWMODE_PWMS_PWMPS	10
64d3588a55SStefano Babic #define SWMODE_PWMS_AUTO	11
65d3588a55SStefano Babic #define SWMODE_AUTO_PFM		12
66d3588a55SStefano Babic #define SWMODE_PWM_PFM		13
67d3588a55SStefano Babic #define SWMODE_PWMS_PFM		14
68d3588a55SStefano Babic #define SWMODE_PFM_PFM		15
69d3588a55SStefano Babic #define SWMODE_MASK		0x0F
70d3588a55SStefano Babic 
71d3588a55SStefano Babic #define SWMODE1_SHIFT		0
72d3588a55SStefano Babic #define SWMODE2_SHIFT		10
73d3588a55SStefano Babic #define SWMODE3_SHIFT		0
74d3588a55SStefano Babic #define SWMODE4_SHIFT		8
75d3588a55SStefano Babic 
76d3588a55SStefano Babic /* Fields in REG_SETTING_1 */
77d3588a55SStefano Babic #define VVIDEO_2_7	(0 << 2)
78d3588a55SStefano Babic #define VVIDEO_2_775	(1 << 2)
79d3588a55SStefano Babic #define VVIDEO_2_5	(2 << 2)
80d3588a55SStefano Babic #define VVIDEO_2_6	(3 << 2)
81d3588a55SStefano Babic #define VVIDEO_MASK	(3 << 2)
82d3588a55SStefano Babic #define VAUDIO_2_3	(0 << 4)
83d3588a55SStefano Babic #define VAUDIO_2_5	(1 << 4)
84d3588a55SStefano Babic #define VAUDIO_2_775	(2 << 4)
85d3588a55SStefano Babic #define VAUDIO_3_0	(3 << 4)
86d3588a55SStefano Babic #define VAUDIO_MASK	(3 << 4)
87d3588a55SStefano Babic #define VSD_1_8		(0 << 6)
88d3588a55SStefano Babic #define VSD_2_0		(1 << 6)
89d3588a55SStefano Babic #define VSD_2_6		(2 << 6)
90d3588a55SStefano Babic #define VSD_2_7		(3 << 6)
91d3588a55SStefano Babic #define VSD_2_8		(4 << 6)
92d3588a55SStefano Babic #define VSD_2_9		(5 << 6)
93d3588a55SStefano Babic #define VSD_3_0		(6 << 6)
94d3588a55SStefano Babic #define VSD_3_15	(7 << 6)
95d3588a55SStefano Babic #define VSD_MASK	(7 << 6)
96d3588a55SStefano Babic #define VGEN1_1_2	0
97d3588a55SStefano Babic #define VGEN1_1_5	1
98d3588a55SStefano Babic #define VGEN1_2_775	2
99d3588a55SStefano Babic #define VGEN1_3_15	3
100d3588a55SStefano Babic #define VGEN1_MASK	3
101d3588a55SStefano Babic #define VGEN2_1_2	(0 << 6)
102d3588a55SStefano Babic #define VGEN2_1_5	(1 << 6)
103d3588a55SStefano Babic #define VGEN2_1_6	(2 << 6)
104d3588a55SStefano Babic #define VGEN2_1_8	(3 << 6)
105d3588a55SStefano Babic #define VGEN2_2_7	(4 << 6)
106d3588a55SStefano Babic #define VGEN2_2_8	(5 << 6)
107d3588a55SStefano Babic #define VGEN2_3_0	(6 << 6)
108d3588a55SStefano Babic #define VGEN2_3_15	(7 << 6)
109d3588a55SStefano Babic #define VGEN2_MASK	(7 << 6)
110d3588a55SStefano Babic 
111d3588a55SStefano Babic /* Fields in REG_SETTING_1 */
112d3588a55SStefano Babic #define VGEN3_1_8	(0 << 14)
113d3588a55SStefano Babic #define VGEN3_2_9	(1 << 14)
114d3588a55SStefano Babic #define VGEN3_MASK	(1 << 14)
115d3588a55SStefano Babic #define VDIG_1_05	(0 << 4)
116d3588a55SStefano Babic #define VDIG_1_25	(1 << 4)
117d3588a55SStefano Babic #define VDIG_1_65	(2 << 4)
118d3588a55SStefano Babic #define VDIG_1_8	(3 << 4)
119d3588a55SStefano Babic #define VDIG_MASK	(3 << 4)
120d3588a55SStefano Babic #define VCAM_2_5	(0 << 16)
121d3588a55SStefano Babic #define VCAM_2_6	(1 << 16)
122d3588a55SStefano Babic #define VCAM_2_75	(2 << 16)
123d3588a55SStefano Babic #define VCAM_3_0	(3 << 16)
124d3588a55SStefano Babic #define VCAM_MASK	(3 << 16)
125d3588a55SStefano Babic 
126761e83a9SMarek Vasut /* Reg Mode 0 */
127761e83a9SMarek Vasut #define VGEN1EN		(1 << 0)
128761e83a9SMarek Vasut #define VGEN1STBY	(1 << 1)
129761e83a9SMarek Vasut #define VGEN1MODE	(1 << 2)
130761e83a9SMarek Vasut #define VIOHIEN		(1 << 3)
131761e83a9SMarek Vasut #define VIOHISTBY	(1 << 4)
132761e83a9SMarek Vasut #define VDIGEN		(1 << 9)
133761e83a9SMarek Vasut #define VDIGSTBY	(1 << 10)
134761e83a9SMarek Vasut #define VGEN2EN		(1 << 12)
135761e83a9SMarek Vasut #define VGEN2STBY	(1 << 13)
136761e83a9SMarek Vasut #define VGEN2MODE	(1 << 14)
137761e83a9SMarek Vasut #define VPLLEN		(1 << 15)
138761e83a9SMarek Vasut #define VPLLSTBY	(1 << 16)
139761e83a9SMarek Vasut #define VUSBEN		(1 << 18)
140761e83a9SMarek Vasut #define VUSBSTBY	(1 << 19)
141761e83a9SMarek Vasut 
142d3588a55SStefano Babic /* Reg Mode 1 */
143d3588a55SStefano Babic #define VGEN3EN		(1 << 0)
144d3588a55SStefano Babic #define VGEN3STBY	(1 << 1)
145d3588a55SStefano Babic #define VGEN3MODE	(1 << 2)
146d3588a55SStefano Babic #define VGEN3CONFIG	(1 << 3)
147d3588a55SStefano Babic #define VCAMEN		(1 << 6)
148d3588a55SStefano Babic #define VCAMSTBY	(1 << 7)
149d3588a55SStefano Babic #define VCAMMODE	(1 << 8)
150d3588a55SStefano Babic #define VCAMCONFIG	(1 << 9)
151d3588a55SStefano Babic #define VVIDEOEN	(1 << 12)
152d3588a55SStefano Babic #define VIDEOSTBY	(1 << 13)
153d3588a55SStefano Babic #define VVIDEOMODE	(1 << 14)
154d3588a55SStefano Babic #define VAUDIOEN	(1 << 15)
155d3588a55SStefano Babic #define VAUDIOSTBY	(1 << 16)
156d3588a55SStefano Babic #define VSDEN		(1 << 18)
157d3588a55SStefano Babic #define VSDSTBY		(1 << 19)
158d3588a55SStefano Babic #define VSDMODE		(1 << 20)
159d3588a55SStefano Babic 
160f8f8acd7SStefano Babic /* Reg Power Control 2*/
161f8f8acd7SStefano Babic #define WDIRESET	(1 << 12)
162f8f8acd7SStefano Babic 
16394391fbcSLiu Hui-R64343 /* SWx Output Volts */
16494391fbcSLiu Hui-R64343 #define SWX_OUT_MASK	0x1F
16594391fbcSLiu Hui-R64343 #define SWX_OUT_1_25	0x1A
16694391fbcSLiu Hui-R64343 #define SWX_OUT_1_30    0X1C
16794391fbcSLiu Hui-R64343 
1683db9e9d7SMarek Vasut /* Buck Switchers (SW1,2,3,4) Output Voltage */
1693db9e9d7SMarek Vasut /*
1703db9e9d7SMarek Vasut  * NOTE: These values are for SWxHI = 0,
1713db9e9d7SMarek Vasut  * SWxHI = 1 adds 0.5V to the desired voltage
1723db9e9d7SMarek Vasut  */
1733db9e9d7SMarek Vasut #define SWx_0_600V	0
1743db9e9d7SMarek Vasut #define SWx_0_625V	1
1753db9e9d7SMarek Vasut #define SWx_0_650V	2
1763db9e9d7SMarek Vasut #define SWx_0_675V	3
1773db9e9d7SMarek Vasut #define SWx_0_700V	4
1783db9e9d7SMarek Vasut #define SWx_0_725V	5
1793db9e9d7SMarek Vasut #define SWx_0_750V	6
1803db9e9d7SMarek Vasut #define SWx_0_775V	7
1813db9e9d7SMarek Vasut #define SWx_0_800V	8
1823db9e9d7SMarek Vasut #define SWx_0_825V	9
1833db9e9d7SMarek Vasut #define SWx_0_850V	10
1843db9e9d7SMarek Vasut #define SWx_0_875V	11
1853db9e9d7SMarek Vasut #define SWx_0_900V	12
1863db9e9d7SMarek Vasut #define SWx_0_925V	13
1873db9e9d7SMarek Vasut #define SWx_0_950V	14
1883db9e9d7SMarek Vasut #define SWx_0_975V	15
1893db9e9d7SMarek Vasut #define SWx_1_000V	16
1903db9e9d7SMarek Vasut #define SWx_1_025V	17
1913db9e9d7SMarek Vasut #define SWx_1_050V	18
1923db9e9d7SMarek Vasut #define SWx_1_075V	19
1933db9e9d7SMarek Vasut #define SWx_1_100V	20
1943db9e9d7SMarek Vasut #define SWx_1_125V	21
1953db9e9d7SMarek Vasut #define SWx_1_150V	22
1963db9e9d7SMarek Vasut #define SWx_1_175V	23
1973db9e9d7SMarek Vasut #define SWx_1_200V	24
1983db9e9d7SMarek Vasut #define SWx_1_225V	25
1993db9e9d7SMarek Vasut #define SWx_1_250V	26
2003db9e9d7SMarek Vasut #define SWx_1_275V	27
2013db9e9d7SMarek Vasut #define SWx_1_300V	28
2023db9e9d7SMarek Vasut #define SWx_1_325V	29
2033db9e9d7SMarek Vasut #define SWx_1_350V	30
2043db9e9d7SMarek Vasut #define SWx_1_375V	31
2053db9e9d7SMarek Vasut #define SWx_VOLT_MASK	0x1F
2063db9e9d7SMarek Vasut 
207d3588a55SStefano Babic #endif
208