Home
last modified time | relevance | path

Searched full:3 (Results 1 – 25 of 3870) sorted by relevance

12345678910>>...155

/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dtie.h103 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
106 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
107 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
108 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
109 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
110 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
111 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
112 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
113 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3326.dtsi20 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */
21 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */
22 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */
23 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */
24 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */
25 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */
26 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */
27 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */
28 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */
29 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */
[all …]
H A Drk3568-pinctrl.dtsi59 <3 RK_PA0 2 &pcfg_pull_none>,
82 <3 RK_PC6 5 &pcfg_pull_none>,
84 <3 RK_PC7 5 &pcfg_pull_none>,
86 <3 RK_PD0 5 &pcfg_pull_none>,
88 <3 RK_PD1 5 &pcfg_pull_none>,
90 <3 RK_PD2 5 &pcfg_pull_none>,
92 <3 RK_PD3 5 &pcfg_pull_none>,
94 <3 RK_PD4 5 &pcfg_pull_none>,
96 <3 RK_PD5 5 &pcfg_pull_none>;
103 <3 RK_PA6 2 &pcfg_pull_none>,
[all …]
H A Drv1126-pinctrl.dtsi14 <1 RK_PA6 3 &pcfg_pull_none>,
16 <1 RK_PA7 3 &pcfg_pull_none>;
21 <3 RK_PA2 2 &pcfg_pull_none>,
23 <3 RK_PA3 2 &pcfg_pull_none>;
30 <3 RK_PD1 4 &pcfg_pull_none>,
32 <3 RK_PD7 3 &pcfg_pull_none>,
34 <3 RK_PD4 3 &pcfg_pull_none>,
36 <3 RK_PD0 3 &pcfg_pull_none>,
38 <3 RK_PD6 3 &pcfg_pull_none>,
40 <3 RK_PD5 3 &pcfg_pull_none>,
[all …]
H A Drk3528-pinctrl.dtsi18 <4 RK_PC4 3 &pcfg_pull_none>;
26 <4 RK_PA0 3 &pcfg_pull_none>,
28 <4 RK_PA1 3 &pcfg_pull_none>;
34 <4 RK_PC6 3 &pcfg_pull_none>,
36 <4 RK_PC5 3 &pcfg_pull_none>;
70 <3 RK_PA5 5 &pcfg_pull_none>,
72 <3 RK_PA4 5 &pcfg_pull_none>;
88 <3 RK_PB3 2 &pcfg_pull_none>,
90 <3 RK_PB2 2 &pcfg_pull_none>;
98 <3 RK_PC3 3 &pcfg_pull_none>;
[all …]
H A Drk3562-pinctrl.dtsi18 <3 RK_PB2 2 &pcfg_pull_none>,
20 <3 RK_PB3 2 &pcfg_pull_none>;
26 <4 RK_PB1 3 &pcfg_pull_none>,
28 <4 RK_PB7 3 &pcfg_pull_none>;
34 <3 RK_PB4 2 &pcfg_pull_none>;
39 <3 RK_PB5 2 &pcfg_pull_none>;
47 <3 RK_PA1 4 &pcfg_pull_none>,
49 <3 RK_PA0 4 &pcfg_pull_none>;
55 <3 RK_PB7 6 &pcfg_pull_none>,
57 <3 RK_PB6 6 &pcfg_pull_none>;
[all …]
H A Drv1106-pinctrl.dtsi41 <0 RK_PA0 3 &pcfg_pull_none>;
123 <1 RK_PB2 3 &pcfg_pull_none>,
125 <1 RK_PB3 3 &pcfg_pull_none>;
131 <3 RK_PA7 4 &pcfg_pull_none>,
133 <3 RK_PA6 4 &pcfg_pull_none>;
157 <3 RK_PA4 3 &pcfg_pull_none_smt>,
159 <3 RK_PA5 3 &pcfg_pull_none_smt>;
211 <1 RK_PD3 3 &pcfg_pull_none_smt>,
213 <1 RK_PD2 3 &pcfg_pull_none_smt>;
219 <3 RK_PD1 3 &pcfg_pull_none_smt>,
[all …]
H A Dsama5d2-pinfunc.h19 #define PIN_PA3 3
89 #define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2)
97 #define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2)
105 #define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2)
113 #define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2)
121 #define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2)
129 #define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2)
142 #define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3)
150 #define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4)
153 #define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3)
[all …]
H A Drk3576-pinctrl.dtsi18 <0 RK_PA0 3 &pcfg_pull_none>;
24 <0 RK_PB0 3 &pcfg_pull_none>;
30 <4 RK_PA2 3 &pcfg_pull_none>;
38 <3 RK_PD7 3 &pcfg_pull_none>;
52 <4 RK_PA0 3 &pcfg_pull_none>;
66 <4 RK_PA1 3 &pcfg_pull_none>;
104 <3 RK_PC1 12 &pcfg_pull_none>,
106 <3 RK_PC4 12 &pcfg_pull_none>;
138 <3 RK_PA3 11 &pcfg_pull_none>,
140 <3 RK_PA2 11 &pcfg_pull_none>;
[all …]
H A Drk3588s-pinctrl.dtsi18 <3 RK_PA1 4 &pcfg_pull_none>,
20 <3 RK_PA2 4 &pcfg_pull_none>,
22 <3 RK_PA3 4 &pcfg_pull_none>,
24 <3 RK_PA4 4 &pcfg_pull_none>;
90 <3 RK_PB5 9 &pcfg_pull_none>,
92 <3 RK_PB6 9 &pcfg_pull_none>;
108 <3 RK_PC4 9 &pcfg_pull_none>,
110 <3 RK_PC5 9 &pcfg_pull_none>;
142 <3 RK_PC4 1 &pcfg_pull_none>,
144 <3 RK_PC5 1 &pcfg_pull_none>,
[all …]
/rk3399_rockchip-uboot/examples/standalone/
H A Dppc_setjmp.S13 # define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
27 stw r1,(JB_GPR1*4)(3)
29 stw r2,(JB_GPR2*4)(3)
30 stw r14,((JB_GPRS+0)*4)(3)
31 FP( stfd 14,((JB_FPRS+0*2)*4)(3))
32 stw r0,(JB_LR*4)(3)
33 stw r15,((JB_GPRS+1)*4)(3)
34 FP( stfd 15,((JB_FPRS+1*2)*4)(3))
36 stw r16,((JB_GPRS+2)*4)(3)
37 FP( stfd 16,((JB_FPRS+2*2)*4)(3))
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dnand_ids.c30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
87 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
88 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
89 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
90 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
93 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h23 uint32_t reserved_writeonce[3];
27 uint32_t reserved_entropy[3];
29 uint32_t reserved_entropy_latched[3];
35 uint32_t reserved_hw_digctl_dbgrd[3];
37 uint32_t reserved_hw_digctl_dbg[3];
60 uint32_t reserved_hw_digctl_scratch0[3];
62 uint32_t reserved_hw_digctl_scratch1[3];
64 uint32_t reserved_hw_digctl_armcache[3];
67 uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
69 uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3];
[all …]
H A Diomux-mx28.h24 #define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
46 #define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
79 #define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
102 #define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
103 #define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
104 #define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
105 #define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
106 #define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
107 #define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
108 #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dgrf_rk3188.h44 u32 busdmac_con[3];
64 u32 gpio0_p[3];
65 u32 gpio1_p[3][4];
95 GPIO0D3_MASK = 3,
101 GPIO0D2_MASK = 3,
112 GPIO0D0_MASK = 3,
121 GPIO1A7_MASK = 3,
127 GPIO1A6_MASK = 3,
133 GPIO1A5_MASK = 3,
139 GPIO1A4_MASK = 3,
[all …]
H A Dgrf_rk3128.h102 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
107 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
112 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
135 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
141 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
152 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
158 GPIO0B1_MASK = 3,
164 GPIO0B0_MASK = 3,
192 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
201 GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
[all …]
H A Dgrf_rk3399.h60 u32 reserved11[3];
151 u32 gpio2_sr[3][4];
153 u32 gpio2_smt[3][4];
284 u32 reserved1[3];
329 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
332 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
335 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
338 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
343 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
346 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
[all …]
H A Dgrf_rk3288.h17 u32 reserved[3];
80 u32 reserved10[3];
88 u32 pvtm_con[3];
89 u32 pvtm_status[3];
110 u32 cpu_con[3];
173 GPIO3A7_MASK = 3,
179 GPIO3A6_MASK = 3,
185 GPIO3A5_MASK = 3,
191 GPIO3A4_MASK = 3,
197 GPIO3A3_MASK = 3,
[all …]
H A Dgrf_rk3036.h96 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
102 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
111 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
117 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
123 GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
129 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
135 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
141 GPIO0B0_MASK = 3,
212 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
260 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
[all …]
/rk3399_rockchip-uboot/board/altera/arria5-socdk/qts/
H A Dpinmux_config.h4 * SPDX-License-Identifier: BSD-3-Clause
25 3, /* EMACIO14 */
26 3, /* EMACIO15 */
27 3, /* EMACIO16 */
28 3, /* EMACIO17 */
29 3, /* EMACIO18 */
30 3, /* EMACIO19 */
31 3, /* FLASHIO0 */
33 3, /* FLASHIO2 */
34 3, /* FLASHIO3 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h73 u32 analog_reserved1[3];
75 u32 analog_reserved2[3];
77 u32 analog_reserved3[3];
83 u32 analog_reserved4[3];
85 u32 analog_reserved5[3];
91 u32 analog_reserved6[3];
258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
485 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
486 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Di2s-regs.h16 #define MOD_OP_CLK (3 << 30)
21 #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
26 #define MOD_BLC_MASK (3 << 13)
30 #define MOD_MASK (3 << 8)
36 #define MOD_SDF_MASK (3 << 5)
37 #define MOD_RCLK_256FS (0 << 3)
38 #define MOD_RCLK_512FS (1 << 3)
39 #define MOD_RCLK_384FS (2 << 3)
40 #define MOD_RCLK_768FS (3 << 3)
41 #define MOD_RCLK_MASK (3 << 3)
[all …]
/rk3399_rockchip-uboot/lib/avb/libavb/
H A Davb_sha256.c21 * 3. Neither the name of the project nor the names of its contributors
59 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
60 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
66 #define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
71 *((str) + 3) = (uint8_t)((x)); \
83 *((str) + 3) = (uint8_t)((uint64_t)x >> 32); \
91 *(x) = ((uint32_t) * ((str) + 3)) | ((uint32_t) * ((str) + 2) << 8) | \
143 ctx->h[3] = sha256_h0[3]; in avb_sha256_init()
190 wv[4] = wv[3] + t1; in SHA256_transform()
191 wv[3] = wv[2]; in SHA256_transform()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dmfsl.c44 case 3: CGET (num, 0); in do_frd()
60 case 3: CGET (num, 1); in do_frd()
76 case 3: CGET (num, 2); in do_frd()
83 #if (XILINX_FSL_NUMBER > 3) in do_frd()
84 case 3: in do_frd()
86 case 0: NGET (num, 3); in do_frd()
88 case 1: NCGET (num, 3); in do_frd()
90 case 2: GET (num, 3); in do_frd()
92 case 3: CGET (num, 3); in do_frd()
108 case 3: CGET (num, 4); in do_frd()
[all …]
/rk3399_rockchip-uboot/board/altera/cyclone5-socdk/qts/
H A Dpinmux_config.h4 * SPDX-License-Identifier: BSD-3-Clause
31 3, /* FLASHIO0 */
33 3, /* FLASHIO2 */
34 3, /* FLASHIO3 */
40 3, /* FLASHIO9 */
41 3, /* FLASHIO10 */
42 3, /* FLASHIO11 */
43 3, /* GENERALIO0 */
44 3, /* GENERALIO1 */
45 3, /* GENERALIO2 */
[all …]

12345678910>>...155