1*28b48a07SMax Filippov /* 2*28b48a07SMax Filippov * This header file describes this specific Xtensa processor's TIE extensions 3*28b48a07SMax Filippov * that extend basic Xtensa core functionality. It is customized to this 4*28b48a07SMax Filippov * Xtensa processor configuration. 5*28b48a07SMax Filippov * This file is autogenerated, please do not edit. 6*28b48a07SMax Filippov * 7*28b48a07SMax Filippov * Copyright (C) 1999-2015 Cadence Design Systems Inc. 8*28b48a07SMax Filippov * 9*28b48a07SMax Filippov * SPDX-License-Identifier: GPL-2.0+ 10*28b48a07SMax Filippov */ 11*28b48a07SMax Filippov 12*28b48a07SMax Filippov #ifndef _XTENSA_CORE_TIE_H 13*28b48a07SMax Filippov #define _XTENSA_CORE_TIE_H 14*28b48a07SMax Filippov 15*28b48a07SMax Filippov #define XCHAL_CP_NUM 0 /* number of coprocessors */ 16*28b48a07SMax Filippov #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 17*28b48a07SMax Filippov #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 18*28b48a07SMax Filippov #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 19*28b48a07SMax Filippov 20*28b48a07SMax Filippov /* Save area for non-coprocessor optional and custom (TIE) state: */ 21*28b48a07SMax Filippov #define XCHAL_NCP_SA_SIZE 28 22*28b48a07SMax Filippov #define XCHAL_NCP_SA_ALIGN 4 23*28b48a07SMax Filippov 24*28b48a07SMax Filippov /* Total save area for optional and custom state (NCP + CPn): */ 25*28b48a07SMax Filippov #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ 26*28b48a07SMax Filippov #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ 27*28b48a07SMax Filippov 28*28b48a07SMax Filippov /* 29*28b48a07SMax Filippov * Detailed contents of save areas. 30*28b48a07SMax Filippov * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 31*28b48a07SMax Filippov * before expanding the XCHAL_xxx_SA_LIST() macros. 32*28b48a07SMax Filippov * 33*28b48a07SMax Filippov * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 34*28b48a07SMax Filippov * dbnum,base,regnum,bitsz,gapsz,reset,x...) 35*28b48a07SMax Filippov * 36*28b48a07SMax Filippov * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 37*28b48a07SMax Filippov * ccused = set if used by compiler without special options or code 38*28b48a07SMax Filippov * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 39*28b48a07SMax Filippov * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 40*28b48a07SMax Filippov * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 41*28b48a07SMax Filippov * name = lowercase reg name (no quotes) 42*28b48a07SMax Filippov * galign = group byte alignment (power of 2) (galign >= align) 43*28b48a07SMax Filippov * align = register byte alignment (power of 2) 44*28b48a07SMax Filippov * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 45*28b48a07SMax Filippov * (not including any pad bytes required to galign this or next reg) 46*28b48a07SMax Filippov * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 47*28b48a07SMax Filippov * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 48*28b48a07SMax Filippov * regnum = reg index in regfile, or special/TIE-user reg number 49*28b48a07SMax Filippov * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 50*28b48a07SMax Filippov * gapsz = intervening bits, if bitsz bits not stored contiguously 51*28b48a07SMax Filippov * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 52*28b48a07SMax Filippov * reset = register reset value (or 0 if undefined at reset) 53*28b48a07SMax Filippov * x = reserved for future use (0 until then) 54*28b48a07SMax Filippov * 55*28b48a07SMax Filippov * To filter out certain registers, e.g. to expand only the non-global 56*28b48a07SMax Filippov * registers used by the compiler, you can do something like this: 57*28b48a07SMax Filippov * 58*28b48a07SMax Filippov * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 59*28b48a07SMax Filippov * #define SELCC0(p...) 60*28b48a07SMax Filippov * #define SELCC1(abikind,p...) SELAK##abikind(p) 61*28b48a07SMax Filippov * #define SELAK0(p...) REG(p) 62*28b48a07SMax Filippov * #define SELAK1(p...) REG(p) 63*28b48a07SMax Filippov * #define SELAK2(p...) 64*28b48a07SMax Filippov * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 65*28b48a07SMax Filippov * ...what you want to expand... 66*28b48a07SMax Filippov */ 67*28b48a07SMax Filippov 68*28b48a07SMax Filippov #define XCHAL_NCP_SA_NUM 7 69*28b48a07SMax Filippov #define XCHAL_NCP_SA_LIST(s) \ 70*28b48a07SMax Filippov XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 71*28b48a07SMax Filippov XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 72*28b48a07SMax Filippov XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 73*28b48a07SMax Filippov XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 74*28b48a07SMax Filippov XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 75*28b48a07SMax Filippov XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 76*28b48a07SMax Filippov XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) 77*28b48a07SMax Filippov 78*28b48a07SMax Filippov #define XCHAL_CP0_SA_NUM 0 79*28b48a07SMax Filippov #define XCHAL_CP0_SA_LIST(s) /* empty */ 80*28b48a07SMax Filippov 81*28b48a07SMax Filippov #define XCHAL_CP1_SA_NUM 0 82*28b48a07SMax Filippov #define XCHAL_CP1_SA_LIST(s) /* empty */ 83*28b48a07SMax Filippov 84*28b48a07SMax Filippov #define XCHAL_CP2_SA_NUM 0 85*28b48a07SMax Filippov #define XCHAL_CP2_SA_LIST(s) /* empty */ 86*28b48a07SMax Filippov 87*28b48a07SMax Filippov #define XCHAL_CP3_SA_NUM 0 88*28b48a07SMax Filippov #define XCHAL_CP3_SA_LIST(s) /* empty */ 89*28b48a07SMax Filippov 90*28b48a07SMax Filippov #define XCHAL_CP4_SA_NUM 0 91*28b48a07SMax Filippov #define XCHAL_CP4_SA_LIST(s) /* empty */ 92*28b48a07SMax Filippov 93*28b48a07SMax Filippov #define XCHAL_CP5_SA_NUM 0 94*28b48a07SMax Filippov #define XCHAL_CP5_SA_LIST(s) /* empty */ 95*28b48a07SMax Filippov 96*28b48a07SMax Filippov #define XCHAL_CP6_SA_NUM 0 97*28b48a07SMax Filippov #define XCHAL_CP6_SA_LIST(s) /* empty */ 98*28b48a07SMax Filippov 99*28b48a07SMax Filippov #define XCHAL_CP7_SA_NUM 0 100*28b48a07SMax Filippov #define XCHAL_CP7_SA_LIST(s) /* empty */ 101*28b48a07SMax Filippov 102*28b48a07SMax Filippov /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 103*28b48a07SMax Filippov #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 104*28b48a07SMax Filippov /* Byte length of instruction from its first byte, per FLIX. */ 105*28b48a07SMax Filippov #define XCHAL_BYTE0_FORMAT_LENGTHS \ 106*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 107*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 108*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 109*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 110*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 111*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 112*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 113*28b48a07SMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 114*28b48a07SMax Filippov 115*28b48a07SMax Filippov #endif /*_XTENSA_CORE_TIE_H*/ 116*28b48a07SMax Filippov 117