1c17736c0Shuang lin /* 2c17736c0Shuang lin * (C) Copyright 2015 Rockchip Electronics Co., Ltd 3c17736c0Shuang lin * 4c17736c0Shuang lin * SPDX-License-Identifier: GPL-2.0+ 5c17736c0Shuang lin */ 6c17736c0Shuang lin #ifndef _ASM_ARCH_GRF_RK3036_H 7c17736c0Shuang lin #define _ASM_ARCH_GRF_RK3036_H 8c17736c0Shuang lin 9c17736c0Shuang lin #include <common.h> 10c17736c0Shuang lin 11c17736c0Shuang lin struct rk3036_grf { 12c17736c0Shuang lin unsigned int reserved[0x2a]; 13c17736c0Shuang lin unsigned int gpio0a_iomux; 14c17736c0Shuang lin unsigned int gpio0b_iomux; 15c17736c0Shuang lin unsigned int gpio0c_iomux; 16c17736c0Shuang lin unsigned int gpio0d_iomux; 17c17736c0Shuang lin 18c17736c0Shuang lin unsigned int gpio1a_iomux; 19c17736c0Shuang lin unsigned int gpio1b_iomux; 20c17736c0Shuang lin unsigned int gpio1c_iomux; 21c17736c0Shuang lin unsigned int gpio1d_iomux; 22c17736c0Shuang lin 23c17736c0Shuang lin unsigned int gpio2a_iomux; 24c17736c0Shuang lin unsigned int gpio2b_iomux; 25c17736c0Shuang lin unsigned int gpio2c_iomux; 26c17736c0Shuang lin unsigned int gpio2d_iomux; 27c17736c0Shuang lin 28c17736c0Shuang lin unsigned int reserved2[0x0a]; 29c17736c0Shuang lin unsigned int gpiods; 30c17736c0Shuang lin unsigned int reserved3[0x05]; 31c17736c0Shuang lin unsigned int gpio0l_pull; 32c17736c0Shuang lin unsigned int gpio0h_pull; 33c17736c0Shuang lin unsigned int gpio1l_pull; 34c17736c0Shuang lin unsigned int gpio1h_pull; 35c17736c0Shuang lin unsigned int gpio2l_pull; 36c17736c0Shuang lin unsigned int gpio2h_pull; 37c17736c0Shuang lin unsigned int reserved4[4]; 38c17736c0Shuang lin unsigned int soc_con0; 39c17736c0Shuang lin unsigned int soc_con1; 40c17736c0Shuang lin unsigned int soc_con2; 41c17736c0Shuang lin unsigned int soc_status0; 42c17736c0Shuang lin unsigned int reserved5; 43c17736c0Shuang lin unsigned int soc_con3; 44c17736c0Shuang lin unsigned int reserved6; 45c17736c0Shuang lin unsigned int dmac_con0; 46c17736c0Shuang lin unsigned int dmac_con1; 47c17736c0Shuang lin unsigned int dmac_con2; 48c17736c0Shuang lin unsigned int reserved7[5]; 49c17736c0Shuang lin unsigned int uoc0_con5; 50c17736c0Shuang lin unsigned int reserved8[4]; 51c17736c0Shuang lin unsigned int uoc1_con4; 52c17736c0Shuang lin unsigned int uoc1_con5; 53c17736c0Shuang lin unsigned int reserved9; 54c17736c0Shuang lin unsigned int ddrc_stat; 55c17736c0Shuang lin unsigned int uoc_con6; 56c17736c0Shuang lin unsigned int soc_status1; 57c17736c0Shuang lin unsigned int cpu_con0; 58c17736c0Shuang lin unsigned int cpu_con1; 59c17736c0Shuang lin unsigned int cpu_con2; 60c17736c0Shuang lin unsigned int cpu_con3; 61c17736c0Shuang lin unsigned int reserved10; 62c17736c0Shuang lin unsigned int reserved11; 63c17736c0Shuang lin unsigned int cpu_status0; 64c17736c0Shuang lin unsigned int cpu_status1; 65c17736c0Shuang lin unsigned int os_reg[8]; 66c17736c0Shuang lin unsigned int reserved12[6]; 67c17736c0Shuang lin unsigned int dll_con[4]; 68c17736c0Shuang lin unsigned int dll_status[4]; 69c17736c0Shuang lin unsigned int dfi_wrnum; 70c17736c0Shuang lin unsigned int dfi_rdnum; 71c17736c0Shuang lin unsigned int dfi_actnum; 72c17736c0Shuang lin unsigned int dfi_timerval; 73c17736c0Shuang lin unsigned int nfi_fifo[4]; 74c17736c0Shuang lin unsigned int reserved13[0x10]; 75c17736c0Shuang lin unsigned int usbphy0_con[8]; 76c17736c0Shuang lin unsigned int usbphy1_con[8]; 77c17736c0Shuang lin unsigned int reserved14[0x10]; 78c17736c0Shuang lin unsigned int chip_tag; 79c17736c0Shuang lin unsigned int sdmmc_det_cnt; 80c17736c0Shuang lin }; 81c17736c0Shuang lin check_member(rk3036_grf, sdmmc_det_cnt, 0x304); 82c17736c0Shuang lin 83c17736c0Shuang lin /* GRF_GPIO0A_IOMUX */ 84c17736c0Shuang lin enum { 85c17736c0Shuang lin GPIO0A3_SHIFT = 6, 863c421f6fSKever Yang GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, 87c17736c0Shuang lin GPIO0A3_GPIO = 0, 88c17736c0Shuang lin GPIO0A3_I2C1_SDA, 89c17736c0Shuang lin 90c17736c0Shuang lin GPIO0A2_SHIFT = 4, 913c421f6fSKever Yang GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, 92c17736c0Shuang lin GPIO0A2_GPIO = 0, 93c17736c0Shuang lin GPIO0A2_I2C1_SCL, 94c17736c0Shuang lin 95c17736c0Shuang lin GPIO0A1_SHIFT = 2, 963c421f6fSKever Yang GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, 97c17736c0Shuang lin GPIO0A1_GPIO = 0, 98c17736c0Shuang lin GPIO0A1_I2C0_SDA, 99c17736c0Shuang lin GPIO0A1_PWM2, 100c17736c0Shuang lin 101c17736c0Shuang lin GPIO0A0_SHIFT = 0, 1023c421f6fSKever Yang GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, 103c17736c0Shuang lin GPIO0A0_GPIO = 0, 104c17736c0Shuang lin GPIO0A0_I2C0_SCL, 105c17736c0Shuang lin GPIO0A0_PWM1, 106c17736c0Shuang lin }; 107c17736c0Shuang lin 108c17736c0Shuang lin /* GRF_GPIO0B_IOMUX */ 109c17736c0Shuang lin enum { 110c17736c0Shuang lin GPIO0B6_SHIFT = 12, 1113c421f6fSKever Yang GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, 112c17736c0Shuang lin GPIO0B6_GPIO = 0, 113c17736c0Shuang lin GPIO0B6_MMC1_D3, 114c17736c0Shuang lin GPIO0B6_I2S1_SCLK, 115c17736c0Shuang lin 116c17736c0Shuang lin GPIO0B5_SHIFT = 10, 1173c421f6fSKever Yang GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, 118c17736c0Shuang lin GPIO0B5_GPIO = 0, 119c17736c0Shuang lin GPIO0B5_MMC1_D2, 120c17736c0Shuang lin GPIO0B5_I2S1_SDI, 121c17736c0Shuang lin 122c17736c0Shuang lin GPIO0B4_SHIFT = 8, 1233c421f6fSKever Yang GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, 124c17736c0Shuang lin GPIO0B4_GPIO = 0, 125c17736c0Shuang lin GPIO0B4_MMC1_D1, 126c17736c0Shuang lin GPIO0B4_I2S1_LRCKTX, 127c17736c0Shuang lin 128c17736c0Shuang lin GPIO0B3_SHIFT = 6, 1293c421f6fSKever Yang GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, 130c17736c0Shuang lin GPIO0B3_GPIO = 0, 131c17736c0Shuang lin GPIO0B3_MMC1_D0, 132c17736c0Shuang lin GPIO0B3_I2S1_LRCKRX, 133c17736c0Shuang lin 134c17736c0Shuang lin GPIO0B1_SHIFT = 2, 1353c421f6fSKever Yang GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, 136c17736c0Shuang lin GPIO0B1_GPIO = 0, 137c17736c0Shuang lin GPIO0B1_MMC1_CLKOUT, 138c17736c0Shuang lin GPIO0B1_I2S1_MCLK, 139c17736c0Shuang lin 140c17736c0Shuang lin GPIO0B0_SHIFT = 0, 141c17736c0Shuang lin GPIO0B0_MASK = 3, 142c17736c0Shuang lin GPIO0B0_GPIO = 0, 143c17736c0Shuang lin GPIO0B0_MMC1_CMD, 144c17736c0Shuang lin GPIO0B0_I2S1_SDO, 145c17736c0Shuang lin }; 146c17736c0Shuang lin 147c17736c0Shuang lin /* GRF_GPIO0C_IOMUX */ 148c17736c0Shuang lin enum { 149c17736c0Shuang lin GPIO0C4_SHIFT = 8, 1503c421f6fSKever Yang GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, 151c17736c0Shuang lin GPIO0C4_GPIO = 0, 152c17736c0Shuang lin GPIO0C4_DRIVE_VBUS, 153c17736c0Shuang lin 154c17736c0Shuang lin GPIO0C3_SHIFT = 6, 1553c421f6fSKever Yang GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, 156c17736c0Shuang lin GPIO0C3_GPIO = 0, 157c17736c0Shuang lin GPIO0C3_UART0_CTSN, 158c17736c0Shuang lin 159c17736c0Shuang lin GPIO0C2_SHIFT = 4, 1603c421f6fSKever Yang GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, 161c17736c0Shuang lin GPIO0C2_GPIO = 0, 162c17736c0Shuang lin GPIO0C2_UART0_RTSN, 163c17736c0Shuang lin 164c17736c0Shuang lin GPIO0C1_SHIFT = 2, 1653c421f6fSKever Yang GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, 166c17736c0Shuang lin GPIO0C1_GPIO = 0, 167c17736c0Shuang lin GPIO0C1_UART0_SIN, 168c17736c0Shuang lin 169c17736c0Shuang lin 170c17736c0Shuang lin GPIO0C0_SHIFT = 0, 1713c421f6fSKever Yang GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, 172c17736c0Shuang lin GPIO0C0_GPIO = 0, 173c17736c0Shuang lin GPIO0C0_UART0_SOUT, 174c17736c0Shuang lin }; 175c17736c0Shuang lin 176c17736c0Shuang lin /* GRF_GPIO0D_IOMUX */ 177c17736c0Shuang lin enum { 178c17736c0Shuang lin GPIO0D4_SHIFT = 8, 1793c421f6fSKever Yang GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, 180c17736c0Shuang lin GPIO0D4_GPIO = 0, 181c17736c0Shuang lin GPIO0D4_SPDIF, 182c17736c0Shuang lin 183c17736c0Shuang lin GPIO0D3_SHIFT = 6, 1843c421f6fSKever Yang GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, 185c17736c0Shuang lin GPIO0D3_GPIO = 0, 186c17736c0Shuang lin GPIO0D3_PWM3, 187c17736c0Shuang lin 188c17736c0Shuang lin GPIO0D2_SHIFT = 4, 1893c421f6fSKever Yang GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, 190c17736c0Shuang lin GPIO0D2_GPIO = 0, 191c17736c0Shuang lin GPIO0D2_PWM0, 192c17736c0Shuang lin }; 193c17736c0Shuang lin 194c17736c0Shuang lin /* GRF_GPIO1A_IOMUX */ 195c17736c0Shuang lin enum { 196c17736c0Shuang lin GPIO1A5_SHIFT = 10, 1973c421f6fSKever Yang GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, 198c17736c0Shuang lin GPIO1A5_GPIO = 0, 199c17736c0Shuang lin GPIO1A5_I2S_SDI, 200c17736c0Shuang lin 201c17736c0Shuang lin GPIO1A4_SHIFT = 8, 2023c421f6fSKever Yang GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, 203c17736c0Shuang lin GPIO1A4_GPIO = 0, 204c17736c0Shuang lin GPIO1A4_I2S_SD0, 205c17736c0Shuang lin 206c17736c0Shuang lin GPIO1A3_SHIFT = 6, 2073c421f6fSKever Yang GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, 208c17736c0Shuang lin GPIO1A3_GPIO = 0, 209c17736c0Shuang lin GPIO1A3_I2S_LRCKTX, 210c17736c0Shuang lin 211c17736c0Shuang lin GPIO1A2_SHIFT = 4, 212*f63defb3SKever Yang GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, 213c17736c0Shuang lin GPIO1A2_GPIO = 0, 214c17736c0Shuang lin GPIO1A2_I2S_LRCKRX, 215*f63defb3SKever Yang GPIO1A2_PWM1_0, 216c17736c0Shuang lin 217c17736c0Shuang lin GPIO1A1_SHIFT = 2, 2183c421f6fSKever Yang GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, 219c17736c0Shuang lin GPIO1A1_GPIO = 0, 220c17736c0Shuang lin GPIO1A1_I2S_SCLK, 221c17736c0Shuang lin 222c17736c0Shuang lin GPIO1A0_SHIFT = 0, 2233c421f6fSKever Yang GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, 224c17736c0Shuang lin GPIO1A0_GPIO = 0, 225c17736c0Shuang lin GPIO1A0_I2S_MCLK, 226c17736c0Shuang lin 227c17736c0Shuang lin }; 228c17736c0Shuang lin 229c17736c0Shuang lin /* GRF_GPIO1B_IOMUX */ 230c17736c0Shuang lin enum { 231c17736c0Shuang lin GPIO1B7_SHIFT = 14, 2323c421f6fSKever Yang GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, 233c17736c0Shuang lin GPIO1B7_GPIO = 0, 234c17736c0Shuang lin GPIO1B7_MMC0_CMD, 235c17736c0Shuang lin 236c17736c0Shuang lin GPIO1B3_SHIFT = 6, 2373c421f6fSKever Yang GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, 238c17736c0Shuang lin GPIO1B3_GPIO = 0, 239c17736c0Shuang lin GPIO1B3_HDMI_HPD, 240c17736c0Shuang lin 241c17736c0Shuang lin GPIO1B2_SHIFT = 4, 2423c421f6fSKever Yang GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, 243c17736c0Shuang lin GPIO1B2_GPIO = 0, 244c17736c0Shuang lin GPIO1B2_HDMI_SCL, 245c17736c0Shuang lin 246c17736c0Shuang lin GPIO1B1_SHIFT = 2, 2473c421f6fSKever Yang GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, 248c17736c0Shuang lin GPIO1B1_GPIO = 0, 249c17736c0Shuang lin GPIO1B1_HDMI_SDA, 250c17736c0Shuang lin 251c17736c0Shuang lin GPIO1B0_SHIFT = 0, 2523c421f6fSKever Yang GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, 253c17736c0Shuang lin GPIO1B0_GPIO = 0, 254c17736c0Shuang lin GPIO1B0_HDMI_CEC, 255c17736c0Shuang lin }; 256c17736c0Shuang lin 257c17736c0Shuang lin /* GRF_GPIO1C_IOMUX */ 258c17736c0Shuang lin enum { 259c17736c0Shuang lin GPIO1C5_SHIFT = 10, 2603c421f6fSKever Yang GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, 261c17736c0Shuang lin GPIO1C5_GPIO = 0, 262c17736c0Shuang lin GPIO1C5_MMC0_D3, 263c17736c0Shuang lin GPIO1C5_JTAG_TMS, 264c17736c0Shuang lin 265c17736c0Shuang lin GPIO1C4_SHIFT = 8, 2663c421f6fSKever Yang GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, 267c17736c0Shuang lin GPIO1C4_GPIO = 0, 268c17736c0Shuang lin GPIO1C4_MMC0_D2, 269c17736c0Shuang lin GPIO1C4_JTAG_TCK, 270c17736c0Shuang lin 271c17736c0Shuang lin GPIO1C3_SHIFT = 6, 2723c421f6fSKever Yang GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, 273c17736c0Shuang lin GPIO1C3_GPIO = 0, 274c17736c0Shuang lin GPIO1C3_MMC0_D1, 275c17736c0Shuang lin GPIO1C3_UART2_SOUT, 276c17736c0Shuang lin 277c17736c0Shuang lin GPIO1C2_SHIFT = 4, 2783c421f6fSKever Yang GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , 279c17736c0Shuang lin GPIO1C2_GPIO = 0, 280c17736c0Shuang lin GPIO1C2_MMC0_D0, 281c17736c0Shuang lin GPIO1C2_UART2_SIN, 282c17736c0Shuang lin 283c17736c0Shuang lin GPIO1C1_SHIFT = 2, 2843c421f6fSKever Yang GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, 285c17736c0Shuang lin GPIO1C1_GPIO = 0, 286c17736c0Shuang lin GPIO1C1_MMC0_DETN, 287c17736c0Shuang lin 288c17736c0Shuang lin GPIO1C0_SHIFT = 0, 2893c421f6fSKever Yang GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, 290c17736c0Shuang lin GPIO1C0_GPIO = 0, 291c17736c0Shuang lin GPIO1C0_MMC0_CLKOUT, 292c17736c0Shuang lin }; 293c17736c0Shuang lin 294c17736c0Shuang lin /* GRF_GPIO1D_IOMUX */ 295c17736c0Shuang lin enum { 296c17736c0Shuang lin GPIO1D7_SHIFT = 14, 2973c421f6fSKever Yang GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, 298c17736c0Shuang lin GPIO1D7_GPIO = 0, 299c17736c0Shuang lin GPIO1D7_NAND_D7, 300c17736c0Shuang lin GPIO1D7_EMMC_D7, 301c17736c0Shuang lin GPIO1D7_SPI_CSN1, 302c17736c0Shuang lin 303c17736c0Shuang lin GPIO1D6_SHIFT = 12, 3043c421f6fSKever Yang GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, 305c17736c0Shuang lin GPIO1D6_GPIO = 0, 306c17736c0Shuang lin GPIO1D6_NAND_D6, 307c17736c0Shuang lin GPIO1D6_EMMC_D6, 308c17736c0Shuang lin GPIO1D6_SPI_CSN0, 309c17736c0Shuang lin 310c17736c0Shuang lin GPIO1D5_SHIFT = 10, 3113c421f6fSKever Yang GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, 312c17736c0Shuang lin GPIO1D5_GPIO = 0, 313c17736c0Shuang lin GPIO1D5_NAND_D5, 314c17736c0Shuang lin GPIO1D5_EMMC_D5, 315c17736c0Shuang lin GPIO1D5_SPI_TXD, 316c17736c0Shuang lin 317c17736c0Shuang lin GPIO1D4_SHIFT = 8, 3183c421f6fSKever Yang GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, 319c17736c0Shuang lin GPIO1D4_GPIO = 0, 320c17736c0Shuang lin GPIO1D4_NAND_D4, 321c17736c0Shuang lin GPIO1D4_EMMC_D4, 322c17736c0Shuang lin GPIO1D4_SPI_RXD, 323c17736c0Shuang lin 324c17736c0Shuang lin GPIO1D3_SHIFT = 6, 3253c421f6fSKever Yang GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, 326c17736c0Shuang lin GPIO1D3_GPIO = 0, 327c17736c0Shuang lin GPIO1D3_NAND_D3, 328c17736c0Shuang lin GPIO1D3_EMMC_D3, 329c17736c0Shuang lin GPIO1D3_SFC_SIO3, 330c17736c0Shuang lin 331c17736c0Shuang lin GPIO1D2_SHIFT = 4, 3323c421f6fSKever Yang GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, 333c17736c0Shuang lin GPIO1D2_GPIO = 0, 334c17736c0Shuang lin GPIO1D2_NAND_D2, 335c17736c0Shuang lin GPIO1D2_EMMC_D2, 336c17736c0Shuang lin GPIO1D2_SFC_SIO2, 337c17736c0Shuang lin 338c17736c0Shuang lin GPIO1D1_SHIFT = 2, 3393c421f6fSKever Yang GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, 340c17736c0Shuang lin GPIO1D1_GPIO = 0, 341c17736c0Shuang lin GPIO1D1_NAND_D1, 342c17736c0Shuang lin GPIO1D1_EMMC_D1, 343c17736c0Shuang lin GPIO1D1_SFC_SIO1, 344c17736c0Shuang lin 345c17736c0Shuang lin GPIO1D0_SHIFT = 0, 3463c421f6fSKever Yang GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, 347c17736c0Shuang lin GPIO1D0_GPIO = 0, 348c17736c0Shuang lin GPIO1D0_NAND_D0, 349c17736c0Shuang lin GPIO1D0_EMMC_D0, 350c17736c0Shuang lin GPIO1D0_SFC_SIO0, 351c17736c0Shuang lin }; 352c17736c0Shuang lin 353c17736c0Shuang lin /* GRF_GPIO2A_IOMUX */ 354c17736c0Shuang lin enum { 355c17736c0Shuang lin GPIO2A7_SHIFT = 14, 3563c421f6fSKever Yang GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, 357c17736c0Shuang lin GPIO2A7_GPIO = 0, 358c17736c0Shuang lin GPIO2A7_TESTCLK_OUT, 359c17736c0Shuang lin 360c17736c0Shuang lin GPIO2A6_SHIFT = 12, 3613c421f6fSKever Yang GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, 362c17736c0Shuang lin GPIO2A6_GPIO = 0, 363c17736c0Shuang lin GPIO2A6_NAND_CS0, 364c17736c0Shuang lin 365c17736c0Shuang lin GPIO2A4_SHIFT = 8, 3663c421f6fSKever Yang GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, 367c17736c0Shuang lin GPIO2A4_GPIO = 0, 368c17736c0Shuang lin GPIO2A4_NAND_RDY, 369c17736c0Shuang lin GPIO2A4_EMMC_CMD, 370c17736c0Shuang lin GPIO2A3_SFC_CLK, 371c17736c0Shuang lin 372c17736c0Shuang lin GPIO2A3_SHIFT = 6, 3733c421f6fSKever Yang GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, 374c17736c0Shuang lin GPIO2A3_GPIO = 0, 375c17736c0Shuang lin GPIO2A3_NAND_RDN, 376c17736c0Shuang lin GPIO2A4_SFC_CSN1, 377c17736c0Shuang lin 378c17736c0Shuang lin GPIO2A2_SHIFT = 4, 3793c421f6fSKever Yang GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, 380c17736c0Shuang lin GPIO2A2_GPIO = 0, 381c17736c0Shuang lin GPIO2A2_NAND_WRN, 382c17736c0Shuang lin GPIO2A4_SFC_CSN0, 383c17736c0Shuang lin 384c17736c0Shuang lin GPIO2A1_SHIFT = 2, 3853c421f6fSKever Yang GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, 386c17736c0Shuang lin GPIO2A1_GPIO = 0, 387c17736c0Shuang lin GPIO2A1_NAND_CLE, 388c17736c0Shuang lin GPIO2A1_EMMC_CLKOUT, 389c17736c0Shuang lin 390c17736c0Shuang lin GPIO2A0_SHIFT = 0, 3913c421f6fSKever Yang GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, 392c17736c0Shuang lin GPIO2A0_GPIO = 0, 393c17736c0Shuang lin GPIO2A0_NAND_ALE, 394c17736c0Shuang lin GPIO2A0_SPI_CLK, 395c17736c0Shuang lin }; 396c17736c0Shuang lin 397c17736c0Shuang lin /* GRF_GPIO2B_IOMUX */ 398c17736c0Shuang lin enum { 399c17736c0Shuang lin GPIO2B7_SHIFT = 14, 4003c421f6fSKever Yang GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, 401c17736c0Shuang lin GPIO2B7_GPIO = 0, 402c17736c0Shuang lin GPIO2B7_MAC_RXER, 403c17736c0Shuang lin 404c17736c0Shuang lin GPIO2B6_SHIFT = 12, 4053c421f6fSKever Yang GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, 406c17736c0Shuang lin GPIO2B6_GPIO = 0, 407c17736c0Shuang lin GPIO2B6_MAC_CLKOUT, 408c17736c0Shuang lin GPIO2B6_MAC_CLKIN, 409c17736c0Shuang lin 410c17736c0Shuang lin GPIO2B5_SHIFT = 10, 4113c421f6fSKever Yang GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, 412c17736c0Shuang lin GPIO2B5_GPIO = 0, 413c17736c0Shuang lin GPIO2B5_MAC_TXEN, 414c17736c0Shuang lin 415c17736c0Shuang lin GPIO2B4_SHIFT = 8, 4163c421f6fSKever Yang GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, 417c17736c0Shuang lin GPIO2B4_GPIO = 0, 418c17736c0Shuang lin GPIO2B4_MAC_MDIO, 419c17736c0Shuang lin 420c17736c0Shuang lin GPIO2B2_SHIFT = 4, 4213c421f6fSKever Yang GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, 422c17736c0Shuang lin GPIO2B2_GPIO = 0, 423c17736c0Shuang lin GPIO2B2_MAC_CRS, 424c17736c0Shuang lin }; 425c17736c0Shuang lin 426c17736c0Shuang lin /* GRF_GPIO2C_IOMUX */ 427c17736c0Shuang lin enum { 428c17736c0Shuang lin GPIO2C7_SHIFT = 14, 4293c421f6fSKever Yang GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, 430c17736c0Shuang lin GPIO2C7_GPIO = 0, 431c17736c0Shuang lin GPIO2C7_UART1_SOUT, 432c17736c0Shuang lin GPIO2C7_TESTCLK_OUT1, 433c17736c0Shuang lin 434c17736c0Shuang lin GPIO2C6_SHIFT = 12, 4353c421f6fSKever Yang GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, 436c17736c0Shuang lin GPIO2C6_GPIO = 0, 437c17736c0Shuang lin GPIO2C6_UART1_SIN, 438c17736c0Shuang lin 439c17736c0Shuang lin GPIO2C5_SHIFT = 10, 4403c421f6fSKever Yang GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, 441c17736c0Shuang lin GPIO2C5_GPIO = 0, 442c17736c0Shuang lin GPIO2C5_I2C2_SCL, 443c17736c0Shuang lin 444c17736c0Shuang lin GPIO2C4_SHIFT = 8, 4453c421f6fSKever Yang GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, 446c17736c0Shuang lin GPIO2C4_GPIO = 0, 447c17736c0Shuang lin GPIO2C4_I2C2_SDA, 448c17736c0Shuang lin 449c17736c0Shuang lin GPIO2C3_SHIFT = 6, 4503c421f6fSKever Yang GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, 451c17736c0Shuang lin GPIO2C3_GPIO = 0, 452c17736c0Shuang lin GPIO2C3_MAC_TXD0, 453c17736c0Shuang lin 454c17736c0Shuang lin GPIO2C2_SHIFT = 4, 4553c421f6fSKever Yang GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, 456c17736c0Shuang lin GPIO2C2_GPIO = 0, 457c17736c0Shuang lin GPIO2C2_MAC_TXD1, 458c17736c0Shuang lin 459c17736c0Shuang lin GPIO2C1_SHIFT = 2, 4603c421f6fSKever Yang GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, 461c17736c0Shuang lin GPIO2C1_GPIO = 0, 462c17736c0Shuang lin GPIO2C1_MAC_RXD0, 463c17736c0Shuang lin 464c17736c0Shuang lin GPIO2C0_SHIFT = 0, 4653c421f6fSKever Yang GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, 466c17736c0Shuang lin GPIO2C0_GPIO = 0, 467c17736c0Shuang lin GPIO2C0_MAC_RXD1, 468c17736c0Shuang lin }; 469c17736c0Shuang lin 470c17736c0Shuang lin /* GRF_GPIO2D_IOMUX */ 471c17736c0Shuang lin enum { 472c17736c0Shuang lin GPIO2D6_SHIFT = 12, 4733c421f6fSKever Yang GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, 474c17736c0Shuang lin GPIO2D6_GPIO = 0, 475c17736c0Shuang lin GPIO2D6_I2S_SDO1, 476c17736c0Shuang lin 477c17736c0Shuang lin GPIO2D5_SHIFT = 10, 4783c421f6fSKever Yang GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, 479c17736c0Shuang lin GPIO2D5_GPIO = 0, 480c17736c0Shuang lin GPIO2D5_I2S_SDO2, 481c17736c0Shuang lin 482c17736c0Shuang lin GPIO2D4_SHIFT = 8, 4833c421f6fSKever Yang GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, 484c17736c0Shuang lin GPIO2D4_GPIO = 0, 485c17736c0Shuang lin GPIO2D4_I2S_SDO3, 486c17736c0Shuang lin 487c17736c0Shuang lin GPIO2D1_SHIFT = 2, 4883c421f6fSKever Yang GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, 489c17736c0Shuang lin GPIO2D1_GPIO = 0, 490c17736c0Shuang lin GPIO2D1_MAC_MDC, 491c17736c0Shuang lin }; 492c17736c0Shuang lin #endif 493