xref: /rk3399_rockchip-uboot/arch/arm/dts/rv1106-pinctrl.dtsi (revision 64c12acace551e058ce42120de996661ee704c57)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"

/*
 * This file is auto generated by pin2dts tool, please keep these code
 * by adding changes at end of this file.
 */
&pinctrl {
	adc {
		adc_pins: adc-pins {
			rockchip,pins =
				/* adc_in0 */
				<4 RK_PC0 1 &pcfg_pull_none>,
				/* adc_in1 */
				<4 RK_PC1 1 &pcfg_pull_none>;
		};
	};

	avs {
		avs_pins: avs-pins {
			rockchip,pins =
				/* avs_arm */
				<1 RK_PA2 2 &pcfg_pull_none>;
		};
	};

	clk {
		clk_32k: clk-32k {
			rockchip,pins =
				/* clk_32k */
				<0 RK_PA0 2 &pcfg_pull_none>;
		};
		clk_refout: clk-refout {
			rockchip,pins =
				/* clk_refout */
				<0 RK_PA0 3 &pcfg_pull_none>;
		};
	};

	dsmaudio {
		dsmaudio_pins: dsmaudio-pins {
			rockchip,pins =
				/* dsmaudio_n */
				<1 RK_PD3 7 &pcfg_pull_none>,
				/* dsmaudio_p */
				<1 RK_PD2 7 &pcfg_pull_none>;
		};
	};

	emmc {
		emmc_bus8: emmc-bus8 {
			rockchip,pins =
				/* emmc_d0 */
				<4 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d1 */
				<4 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d2 */
				<4 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d3 */
				<4 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d4 */
				<4 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d5 */
				<4 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d6 */
				<4 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d7 */
				<4 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
		};

		emmc_clk: emmc-clk {
			rockchip,pins =
				/* emmc_clk */
				<4 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
		};

		emmc_cmd: emmc-cmd {
			rockchip,pins =
				/* emmc_cmd */
				<4 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
		};
	};

	flash {
		flash_pins: flash-pins {
			rockchip,pins =
				/* flash_trig_out */
				<2 RK_PA6 6 &pcfg_pull_none>;
		};
	};

	fspi {
		fspi_pins: fspi-pins {
			rockchip,pins =
				/* fspi_clk */
				<4 RK_PB1 2 &pcfg_pull_up_drv_level_2>,
				/* fspi_d0 */
				<4 RK_PA4 2 &pcfg_pull_none>,
				/* fspi_d1 */
				<4 RK_PA3 2 &pcfg_pull_none>,
				/* fspi_d2 */
				<4 RK_PA2 2 &pcfg_pull_none>,
				/* fspi_d3 */
				<4 RK_PA6 2 &pcfg_pull_none>;
		};

		fspi_cs0: fspi-cs0 {
			rockchip,pins =
				/* fspi_cs0n */
				<4 RK_PB0 2 &pcfg_pull_up>;
		};
	};

	hpmcu {
		hpmcum0_pins: hpmcum0-pins {
			rockchip,pins =
				/* hpmcu_jtag_tck_m0 */
				<1 RK_PB2 3 &pcfg_pull_none>,
				/* hpmcu_jtag_tms_m0 */
				<1 RK_PB3 3 &pcfg_pull_none>;
		};

		hpmcum1_pins: hpmcum1-pins {
			rockchip,pins =
				/* hpmcu_jtag_tck_m1 */
				<3 RK_PA7 4 &pcfg_pull_none>,
				/* hpmcu_jtag_tms_m1 */
				<3 RK_PA6 4 &pcfg_pull_none>;
		};
	};

	i2c0 {
		i2c0m0_xfer: i2c0m0-xfer {
			rockchip,pins =
				/* i2c0_scl_m0 */
				<1 RK_PA3 2 &pcfg_pull_none_smt>,
				/* i2c0_sda_m0 */
				<1 RK_PA4 2 &pcfg_pull_none_smt>;
		};

		i2c0m1_xfer: i2c0m1-xfer {
			rockchip,pins =
				/* i2c0_scl_m1 */
				<4 RK_PA1 4 &pcfg_pull_none_smt>,
				/* i2c0_sda_m1 */
				<4 RK_PA0 4 &pcfg_pull_none_smt>;
		};

		i2c0m2_xfer: i2c0m2-xfer {
			rockchip,pins =
				/* i2c0_scl_m2 */
				<3 RK_PA4 3 &pcfg_pull_none_smt>,
				/* i2c0_sda_m2 */
				<3 RK_PA5 3 &pcfg_pull_none_smt>;
		};
	};

	i2c1 {
		i2c1m0_xfer: i2c1m0-xfer {
			rockchip,pins =
				/* i2c1_scl_m0 */
				<0 RK_PA5 1 &pcfg_pull_none_smt>,
				/* i2c1_sda_m0 */
				<0 RK_PA6 1 &pcfg_pull_none_smt>;
		};

		i2c1m1_xfer: i2c1m1-xfer {
			rockchip,pins =
				/* i2c1_scl_m1 */
				<2 RK_PB0 2 &pcfg_pull_none_smt>,
				/* i2c1_sda_m1 */
				<2 RK_PB1 2 &pcfg_pull_none_smt>;
		};
	};

	i2c2 {
		i2c2m0_xfer: i2c2m0-xfer {
			rockchip,pins =
				/* i2c2_scl_m0 */
				<1 RK_PA0 2 &pcfg_pull_none_smt>,
				/* i2c2_sda_m0 */
				<1 RK_PA1 2 &pcfg_pull_none_smt>;
		};

		i2c2m1_xfer: i2c2m1-xfer {
			rockchip,pins =
				/* i2c2_scl_m1 */
				<4 RK_PA7 4 &pcfg_pull_none_smt>,
				/* i2c2_sda_m1 */
				<4 RK_PA5 4 &pcfg_pull_none_smt>;
		};
	};

	i2c3 {
		i2c3m0_xfer: i2c3m0-xfer {
			rockchip,pins =
				/* i2c3_scl_m0 */
				<2 RK_PA6 5 &pcfg_pull_none_smt>,
				/* i2c3_sda_m0 */
				<2 RK_PA7 5 &pcfg_pull_none_smt>;
		};

		i2c3m1_xfer: i2c3m1-xfer {
			rockchip,pins =
				/* i2c3_scl_m1 */
				<1 RK_PD3 3 &pcfg_pull_none_smt>,
				/* i2c3_sda_m1 */
				<1 RK_PD2 3 &pcfg_pull_none_smt>;
		};

		i2c3m2_xfer: i2c3m2-xfer {
			rockchip,pins =
				/* i2c3_scl_m2 */
				<3 RK_PD1 3 &pcfg_pull_none_smt>,
				/* i2c3_sda_m2 */
				<3 RK_PD2 3 &pcfg_pull_none_smt>;
		};
	};

	i2c4 {
		i2c4m0_xfer: i2c4m0-xfer {
			rockchip,pins =
				/* i2c4_scl_m0 */
				<2 RK_PA1 5 &pcfg_pull_none_smt>,
				/* i2c4_sda_m0 */
				<2 RK_PA0 5 &pcfg_pull_none_smt>;
		};

		i2c4m1_xfer: i2c4m1-xfer {
			rockchip,pins =
				/* i2c4_scl_m1 */
				<1 RK_PC2 4 &pcfg_pull_none_smt>,
				/* i2c4_sda_m1 */
				<1 RK_PC3 4 &pcfg_pull_none_smt>;
		};

		i2c4m2_xfer: i2c4m2-xfer {
			rockchip,pins =
				/* i2c4_scl_m2 */
				<3 RK_PC7 3 &pcfg_pull_none_smt>,
				/* i2c4_sda_m2 */
				<3 RK_PD0 3 &pcfg_pull_none_smt>;
		};
	};

	i2s0 {
		i2s0_pins: i2s0-pins {
			rockchip,pins =
				/* i2s0_lrck */
				<2 RK_PA1 2 &pcfg_pull_none>,
				/* i2s0_mclk */
				<2 RK_PA2 2 &pcfg_pull_none>,
				/* i2s0_sclk */
				<2 RK_PA0 2 &pcfg_pull_none>,
				/* i2s0_sdi0 */
				<2 RK_PA5 2 &pcfg_pull_none>,
				/* i2s0_sdo0 */
				<2 RK_PA4 2 &pcfg_pull_none>,
				/* i2s0_sdo1_sdi3 */
				<2 RK_PA7 2 &pcfg_pull_none>,
				/* i2s0_sdo2_sdi2 */
				<2 RK_PA6 2 &pcfg_pull_none>,
				/* i2s0_sdo3_sdi1 */
				<2 RK_PA3 2 &pcfg_pull_none>;
		};
	};

	lcd {
		lcd_pins: lcd-pins {
			rockchip,pins =
				/* lcd_clk */
				<1 RK_PD3 1 &pcfg_pull_none>,
				/* lcd_d0 */
				<1 RK_PC7 1 &pcfg_pull_none>,
				/* lcd_d1 */
				<1 RK_PC6 1 &pcfg_pull_none>,
				/* lcd_d2 */
				<1 RK_PC5 1 &pcfg_pull_none>,
				/* lcd_d3 */
				<1 RK_PC4 1 &pcfg_pull_none>,
				/* lcd_d4 */
				<1 RK_PC3 1 &pcfg_pull_none>,
				/* lcd_d5 */
				<1 RK_PC2 1 &pcfg_pull_none>,
				/* lcd_d6 */
				<1 RK_PC1 1 &pcfg_pull_none>,
				/* lcd_d7 */
				<1 RK_PC0 1 &pcfg_pull_none>,
				/* lcd_d8 */
				<2 RK_PA0 3 &pcfg_pull_none>,
				/* lcd_d9 */
				<2 RK_PA1 3 &pcfg_pull_none>,
				/* lcd_d10 */
				<2 RK_PA2 3 &pcfg_pull_none>,
				/* lcd_d11 */
				<2 RK_PA3 3 &pcfg_pull_none>,
				/* lcd_d12 */
				<2 RK_PA4 3 &pcfg_pull_none>,
				/* lcd_d13 */
				<2 RK_PA5 3 &pcfg_pull_none>,
				/* lcd_d14 */
				<2 RK_PA6 3 &pcfg_pull_none>,
				/* lcd_d15 */
				<2 RK_PA7 3 &pcfg_pull_none>,
				/* lcd_d16 */
				<2 RK_PB0 3 &pcfg_pull_none>,
				/* lcd_d17 */
				<2 RK_PB1 3 &pcfg_pull_none>,
				/* lcd_den */
				<1 RK_PD0 1 &pcfg_pull_none>,
				/* lcd_hsync */
				<1 RK_PD1 1 &pcfg_pull_none>,
				/* lcd_vsync */
				<1 RK_PD2 1 &pcfg_pull_none>;
		};
	};

	lpmcu {
		lpmcum0_pins: lpmcum0-pins {
			rockchip,pins =
				/* lpmcu_jtag_tck_m0 */
				<1 RK_PB2 4 &pcfg_pull_none>,
				/* lpmcu_jtag_tms_m0 */
				<1 RK_PB3 4 &pcfg_pull_none>;
		};

		lpmcum1_pins: lpmcum1-pins {
			rockchip,pins =
				/* lpmcu_jtag_tck_m1 */
				<3 RK_PA4 4 &pcfg_pull_none>,
				/* lpmcu_jtag_tms_m1 */
				<3 RK_PA5 4 &pcfg_pull_none>;
		};
	};

	mipi {
		mipi_pins: mipi-pins {
			rockchip,pins =
				/* mipi_lvds_ck0n */
				<3 RK_PC0 2 &pcfg_pull_none>,
				/* mipi_lvds_ck0p */
				<3 RK_PC1 2 &pcfg_pull_none>,
				/* mipi_lvds_ck1n */
				<3 RK_PB2 2 &pcfg_pull_none>,
				/* mipi_lvds_ck1p */
				<3 RK_PB3 2 &pcfg_pull_none>,
				/* mipi_lvds_d0n */
				<3 RK_PC2 2 &pcfg_pull_none>,
				/* mipi_lvds_d0p */
				<3 RK_PC3 2 &pcfg_pull_none>,
				/* mipi_lvds_d1n */
				<3 RK_PB6 2 &pcfg_pull_none>,
				/* mipi_lvds_d1p */
				<3 RK_PB7 2 &pcfg_pull_none>,
				/* mipi_lvds_d2n */
				<3 RK_PB4 2 &pcfg_pull_none>,
				/* mipi_lvds_d2p */
				<3 RK_PB5 2 &pcfg_pull_none>,
				/* mipi_lvds_d3n */
				<3 RK_PB0 2 &pcfg_pull_none>,
				/* mipi_lvds_d3p */
				<3 RK_PB1 2 &pcfg_pull_none>,
				/* mipi_refclk_out0 */
				<3 RK_PC4 2 &pcfg_pull_none>,
				/* mipi_refclk_out1 */
				<3 RK_PC6 3 &pcfg_pull_none>;
		};
	};

	pmic {
		pmicm0_pins: pmicm0-pins {
			rockchip,pins =
				/* pmic_sleep_m0 */
				<0 RK_PA4 1 &pcfg_pull_none>;
		};

		pmicm1_pins: pmicm1-pins {
			rockchip,pins =
				/* pmic_sleep_m1 */
				<0 RK_PA3 1 &pcfg_pull_none>;
		};
	};

	pmu {
		pmu_pins: pmu-pins {
			rockchip,pins =
				/* pmu_debug */
				<1 RK_PA1 3 &pcfg_pull_none>;
		};
	};

	prelight {
		prelight_pins: prelight-pins {
			rockchip,pins =
				/* prelight_trig_out */
				<2 RK_PA7 6 &pcfg_pull_none>;
		};
	};

	pwm0 {
		pwm0m0_pins: pwm0m0-pins {
			rockchip,pins =
				/* pwm0_m0 */
				<1 RK_PA2 1 &pcfg_pull_none>;
		};

		pwm0m1_pins: pwm0m1-pins {
			rockchip,pins =
				/* pwm0_m1 */
				<1 RK_PD2 6 &pcfg_pull_none>;
		};
	};

	pwm1 {
		pwm1m0_pins: pwm1m0-pins {
			rockchip,pins =
				/* pwm1_m0 */
				<0 RK_PA4 2 &pcfg_pull_none>;
		};

		pwm1m1_pins: pwm1m1-pins {
			rockchip,pins =
				/* pwm1_m1 */
				<4 RK_PC1 2 &pcfg_pull_none>;
		};

		pwm1m2_pins: pwm1m2-pins {
			rockchip,pins =
				/* pwm1_m2 */
				<3 RK_PD3 2 &pcfg_pull_none>;
		};
	};

	pwm2 {
		pwm2m0_pins: pwm2m0-pins {
			rockchip,pins =
				/* pwm2_m0 */
				<0 RK_PA1 2 &pcfg_pull_none>;
		};

		pwm2m1_pins: pwm2m1-pins {
			rockchip,pins =
				/* pwm2_m1 */
				<2 RK_PA6 4 &pcfg_pull_none>;
		};

		pwm2m2_pins: pwm2m2-pins {
			rockchip,pins =
				/* pwm2_m2 */
				<1 RK_PC0 3 &pcfg_pull_none>;
		};
	};

	pwm3 {
		pwm3m0_pins: pwm3m0-pins {
			rockchip,pins =
				/* pwm3_ir_m0 */
				<0 RK_PA2 1 &pcfg_pull_none>;
		};

		pwm3m1_pins: pwm3m1-pins {
			rockchip,pins =
				/* pwm3_ir_m1 */
				<1 RK_PB0 2 &pcfg_pull_none>;
		};

		pwm3m2_pins: pwm3m2-pins {
			rockchip,pins =
				/* pwm3_ir_m2 */
				<1 RK_PD0 3 &pcfg_pull_none>;
		};
	};

	pwm4 {
		pwm4m0_pins: pwm4m0-pins {
			rockchip,pins =
				/* pwm4_m0 */
				<1 RK_PA1 4 &pcfg_pull_none>;
		};

		pwm4m1_pins: pwm4m1-pins {
			rockchip,pins =
				/* pwm4_m1 */
				<2 RK_PA7 4 &pcfg_pull_none>;
		};

		pwm4m2_pins: pwm4m2-pins {
			rockchip,pins =
				/* pwm4_m2 */
				<1 RK_PC1 3 &pcfg_pull_none>;
		};
	};

	pwm5 {
		pwm5m0_pins: pwm5m0-pins {
			rockchip,pins =
				/* pwm5_m0 */
				<0 RK_PA5 3 &pcfg_pull_none>;
		};

		pwm5m1_pins: pwm5m1-pins {
			rockchip,pins =
				/* pwm5_m1 */
				<2 RK_PB0 4 &pcfg_pull_none>;
		};

		pwm5m2_pins: pwm5m2-pins {
			rockchip,pins =
				/* pwm5_m2 */
				<1 RK_PC2 3 &pcfg_pull_none>;
		};
	};

	pwm6 {
		pwm6m0_pins: pwm6m0-pins {
			rockchip,pins =
				/* pwm6_m0 */
				<0 RK_PA6 3 &pcfg_pull_none>;
		};

		pwm6m1_pins: pwm6m1-pins {
			rockchip,pins =
				/* pwm6_m1 */
				<2 RK_PB1 4 &pcfg_pull_none>;
		};

		pwm6m2_pins: pwm6m2-pins {
			rockchip,pins =
				/* pwm6_m2 */
				<1 RK_PC3 3 &pcfg_pull_none>;
		};
	};

	pwm7 {
		pwm7m0_pins: pwm7m0-pins {
			rockchip,pins =
				/* pwm7_ir_m0 */
				<1 RK_PA0 3 &pcfg_pull_none>;
		};

		pwm7m1_pins: pwm7m1-pins {
			rockchip,pins =
				/* pwm7_ir_m1 */
				<1 RK_PB1 2 &pcfg_pull_none>;
		};

		pwm7m2_pins: pwm7m2-pins {
			rockchip,pins =
				/* pwm7_ir_m2 */
				<3 RK_PC6 2 &pcfg_pull_none>;
		};
	};

	pwm8 {
		pwm8m0_pins: pwm8m0-pins {
			rockchip,pins =
				/* pwm8_m0 */
				<3 RK_PA3 4 &pcfg_pull_none>;
		};

		pwm8m1_pins: pwm8m1-pins {
			rockchip,pins =
				/* pwm8_m1 */
				<1 RK_PC4 3 &pcfg_pull_none>;
		};
	};

	pwm9 {
		pwm9m0_pins: pwm9m0-pins {
			rockchip,pins =
				/* pwm9_m0 */
				<3 RK_PA2 4 &pcfg_pull_none>;
		};

		pwm9m1_pins: pwm9m1-pins {
			rockchip,pins =
				/* pwm9_m1 */
				<1 RK_PC5 3 &pcfg_pull_none>;
		};
	};

	pwm10 {
		pwm10m0_pins: pwm10m0-pins {
			rockchip,pins =
				/* pwm10_m0 */
				<3 RK_PA4 5 &pcfg_pull_none>;
		};

		pwm10m1_pins: pwm10m1-pins {
			rockchip,pins =
				/* pwm10_m1 */
				<1 RK_PC6 3 &pcfg_pull_none>;
		};

		pwm10m2_pins: pwm10m2-pins {
			rockchip,pins =
				/* pwm10_m2 */
				<1 RK_PD1 3 &pcfg_pull_none>;
		};
	};

	pwm11 {
		pwm11m0_pins: pwm11m0-pins {
			rockchip,pins =
				/* pwm11_ir_m0 */
				<3 RK_PA5 5 &pcfg_pull_none>;
		};

		pwm11m1_pins: pwm11m1-pins {
			rockchip,pins =
				/* pwm11_ir_m1 */
				<1 RK_PC7 3 &pcfg_pull_none>;
		};

		pwm11m2_pins: pwm11m2-pins {
			rockchip,pins =
				/* pwm11_ir_m2 */
				<1 RK_PD3 5 &pcfg_pull_none>;
		};
	};

	rtc {
		rtc_pins: rtc-pins {
			rockchip,pins =
				/* rtc_clko */
				<0 RK_PA0 4 &pcfg_pull_none>;
		};
	};

	sdmmc0: sdmmc0 {
		sdmmc0_bus4: sdmmc0-bus4 {
			rockchip,pins =
				/* sdmmc0_d0 */
				<3 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d1 */
				<3 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d2 */
				<3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d3 */
				<3 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_clk: sdmmc0-clk {
			rockchip,pins =
				/* sdmmc0_clk */
				<3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_cmd: sdmmc0-cmd {
			rockchip,pins =
				/* sdmmc0_cmd */
				<3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_det: sdmmc0-det {
			rockchip,pins =
				/* sdmmc0_det */
				<3 RK_PA1 1 &pcfg_pull_up>;
		};

		sdmmc0_idle_pins: sdmmc0-idle-pins {
			rockchip,pins =
				/* sdmmc0_d0 */
				<3 RK_PA3 0 &pcfg_pull_down>,
				/* sdmmc0_d1 */
				<3 RK_PA2 0 &pcfg_pull_down>,
				/* sdmmc0_d2 */
				<3 RK_PA7 0 &pcfg_pull_down>,
				/* sdmmc0_d3 */
				<3 RK_PA6 0 &pcfg_pull_down>,
				/* sdmmc0_clk */
				<3 RK_PA4 0 &pcfg_pull_down>,
				/* sdmmc0_cmd */
				<3 RK_PA5 0 &pcfg_pull_down>;
		};
	};

	sdmmc1 {
		sdmmc1m0_bus4: sdmmc1m0-bus4 {
			rockchip,pins =
				/* sdmmc1_d0_m0 */
				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d1_m0 */
				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d2_m0 */
				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d3_m0 */
				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m0_clk: sdmmc1m0-clk {
			rockchip,pins =
				/* sdmmc1_clk_m0 */
				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m0_cmd: sdmmc1m0-cmd {
			rockchip,pins =
				/* sdmmc1_cmd_m0 */
				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m1_bus4: sdmmc1m1-bus4 {
			rockchip,pins =
				/* sdmmc1_d0_m1 */
				<1 RK_PC1 5 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d1_m1 */
				<1 RK_PC0 5 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d2_m1 */
				<1 RK_PC5 5 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d3_m1 */
				<1 RK_PC4 5 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m1_clk: sdmmc1m1-clk {
			rockchip,pins =
				/* sdmmc1_clk_m1 */
				<1 RK_PC2 5 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m1_cmd: sdmmc1m1-cmd {
			rockchip,pins =
				/* sdmmc1_cmd_m1 */
				<1 RK_PC3 5 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1m1_idle_pins: sdmmc1m1-idle-pins {
			rockchip,pins =
				/* sdmmc1_d0_m1 */
				<1 RK_PC1 0 &pcfg_pull_down>,
				/* sdmmc1_d1_m1 */
				<1 RK_PC0 0 &pcfg_pull_down>,
				/* sdmmc1_d2_m1 */
				<1 RK_PC5 0 &pcfg_pull_down>,
				/* sdmmc1_d3_m1 */
				<1 RK_PC4 0 &pcfg_pull_down>,
				/* sdmmc1_clk_m1 */
				<1 RK_PC2 0 &pcfg_pull_down>,
				/* sdmmc1_cmd_m1 */
				<1 RK_PC3 0 &pcfg_pull_down>;
		};
	};

	spi0 {
		spi0m0_pins: spi0m0-pins {
			rockchip,pins =
				/* spi0_clk_m0 */
				<1 RK_PC1 4 &pcfg_pull_none>,
				/* spi0_miso_m0 */
				<1 RK_PC3 6 &pcfg_pull_none>,
				/* spi0_mosi_m0 */
				<1 RK_PC2 6 &pcfg_pull_none>;
		};

		spi0m0_cs0: spi0m0-cs0 {
			rockchip,pins =
				/* spi0_cs0n_m0 */
				<1 RK_PC0 4 &pcfg_pull_none>;
		};

		spi0m0_cs1: spi0m0-cs1 {
			rockchip,pins =
				/* spi0_cs1n_m0 */
				<1 RK_PD2 5 &pcfg_pull_none>;
		};
	};

	spi1 {
		spi1m0_pins: spi1m0-pins {
			rockchip,pins =
				/* spi1_clk_m0 */
				<4 RK_PA7 2 &pcfg_pull_none>,
				/* spi1_miso_m0 */
				<4 RK_PA0 2 &pcfg_pull_none>,
				/* spi1_mosi_m0 */
				<4 RK_PA1 2 &pcfg_pull_none>;
		};

		spi1m0_cs0: spi1m0-cs0 {
			rockchip,pins =
				/* spi1_cs0n_m0 */
				<4 RK_PA5 2 &pcfg_pull_none>;
		};

		spi1m0_cs1: spi1m0-cs1 {
			rockchip,pins =
				/* spi1_cs1n_m0 */
				<1 RK_PB1 3 &pcfg_pull_none>;
		};
	};

	uart0 {
		uart0m0_xfer: uart0m0-xfer {
			rockchip,pins =
				/* uart0_rx_m0 */
				<0 RK_PA0 1 &pcfg_pull_up>,
				/* uart0_tx_m0 */
				<0 RK_PA1 1 &pcfg_pull_up>;
		};

		uart0m1_xfer: uart0m1-xfer {
			rockchip,pins =
				/* uart0_rx_m1 */
				<2 RK_PB0 1 &pcfg_pull_up>,
				/* uart0_tx_m1 */
				<2 RK_PB1 1 &pcfg_pull_up>;
		};

		uart0m1_ctsn: uart0m1-ctsn {
			rockchip,pins =
				/* uart0m1_ctsn */
				<2 RK_PA7 1 &pcfg_pull_none>;
		};
		uart0m1_rtsn: uart0m1-rtsn {
			rockchip,pins =
				/* uart0m1_rtsn */
				<2 RK_PA6 1 &pcfg_pull_none>;
		};

		uart0m2_xfer: uart0m2-xfer {
			rockchip,pins =
				/* uart0_rx_m2 */
				<4 RK_PA0 3 &pcfg_pull_up>,
				/* uart0_tx_m2 */
				<4 RK_PA1 3 &pcfg_pull_up>;
		};
	};

	uart1 {
		uart1m0_xfer: uart1m0-xfer {
			rockchip,pins =
				/* uart1_rx_m0 */
				<1 RK_PA4 1 &pcfg_pull_up>,
				/* uart1_tx_m0 */
				<1 RK_PA3 1 &pcfg_pull_up>;
		};

		uart1m0_ctsn: uart1m0-ctsn {
			rockchip,pins =
				/* uart1m0_ctsn */
				<0 RK_PA6 2 &pcfg_pull_none>;
		};
		uart1m0_rtsn: uart1m0-rtsn {
			rockchip,pins =
				/* uart1m0_rtsn */
				<0 RK_PA5 2 &pcfg_pull_none>;
		};

		uart1m1_xfer: uart1m1-xfer {
			rockchip,pins =
				/* uart1_rx_m1 */
				<2 RK_PA5 4 &pcfg_pull_up>,
				/* uart1_tx_m1 */
				<2 RK_PA4 4 &pcfg_pull_up>;
		};

		uart1m1_ctsn: uart1m1-ctsn {
			rockchip,pins =
				/* uart1m1_ctsn */
				<2 RK_PA0 4 &pcfg_pull_none>;
		};
		uart1m1_rtsn: uart1m1-rtsn {
			rockchip,pins =
				/* uart1m1_rtsn */
				<2 RK_PA1 4 &pcfg_pull_none>;
		};

		uart1m2_xfer: uart1m2-xfer {
			rockchip,pins =
				/* uart1_rx_m2 */
				<4 RK_PA7 3 &pcfg_pull_up>,
				/* uart1_tx_m2 */
				<4 RK_PA5 3 &pcfg_pull_up>;
		};
	};

	uart2 {
		uart2m0_xfer: uart2m0-xfer {
			rockchip,pins =
				/* uart2_rx_m0 */
				<3 RK_PA3 2 &pcfg_pull_up>,
				/* uart2_tx_m0 */
				<3 RK_PA2 2 &pcfg_pull_up>;
		};

		uart2m1_xfer: uart2m1-xfer {
			rockchip,pins =
				/* uart2_rx_m1 */
				<1 RK_PB3 2 &pcfg_pull_up>,
				/* uart2_tx_m1 */
				<1 RK_PB2 2 &pcfg_pull_up>;
		};
	};

	uart3 {
		uart3m0_xfer: uart3m0-xfer {
			rockchip,pins =
				/* uart3_rx_m0 */
				<1 RK_PA1 1 &pcfg_pull_up>,
				/* uart3_tx_m0 */
				<1 RK_PA0 1 &pcfg_pull_up>;
		};

		uart3m1_xfer: uart3m1-xfer {
			rockchip,pins =
				/* uart3_rx_m1 */
				<1 RK_PD1 5 &pcfg_pull_up>,
				/* uart3_tx_m1 */
				<1 RK_PD0 5 &pcfg_pull_up>;
		};
	};

	uart4 {
		uart4m0_xfer: uart4m0-xfer {
			rockchip,pins =
				/* uart4_rx_m0 */
				<1 RK_PB0 1 &pcfg_pull_up>,
				/* uart4_tx_m0 */
				<1 RK_PB1 1 &pcfg_pull_up>;
		};

		uart4m1_xfer: uart4m1-xfer {
			rockchip,pins =
				/* uart4_rx_m1 */
				<1 RK_PC4 4 &pcfg_pull_up>,
				/* uart4_tx_m1 */
				<1 RK_PC5 4 &pcfg_pull_up>;
		};

		uart4m1_ctsn: uart4m1-ctsn {
			rockchip,pins =
				/* uart4m1_ctsn */
				<1 RK_PC7 4 &pcfg_pull_none>;
		};
		uart4m1_rtsn: uart4m1-rtsn {
			rockchip,pins =
				/* uart4m1_rtsn */
				<1 RK_PC6 4 &pcfg_pull_none>;
		};
	};

	uart5 {
		uart5m0_xfer: uart5m0-xfer {
			rockchip,pins =
				/* uart5_rx_m0 */
				<3 RK_PA7 2 &pcfg_pull_up>,
				/* uart5_tx_m0 */
				<3 RK_PA6 2 &pcfg_pull_up>;
		};

		uart5m0_ctsn: uart5m0-ctsn {
			rockchip,pins =
				/* uart5m0_ctsn */
				<3 RK_PA5 2 &pcfg_pull_none>;
		};
		uart5m0_rtsn: uart5m0-rtsn {
			rockchip,pins =
				/* uart5m0_rtsn */
				<3 RK_PA4 2 &pcfg_pull_none>;
		};

		uart5m1_xfer: uart5m1-xfer {
			rockchip,pins =
				/* uart5_rx_m1 */
				<1 RK_PD2 4 &pcfg_pull_up>,
				/* uart5_tx_m1 */
				<1 RK_PD3 4 &pcfg_pull_up>;
		};

		uart5m1_ctsn: uart5m1-ctsn {
			rockchip,pins =
				/* uart5m1_ctsn */
				<1 RK_PD1 4 &pcfg_pull_none>;
		};
		uart5m1_rtsn: uart5m1-rtsn {
			rockchip,pins =
				/* uart5m1_rtsn */
				<1 RK_PD0 4 &pcfg_pull_none>;
		};

		uart5m2_xfer: uart5m2-xfer {
			rockchip,pins =
				/* uart5_rx_m2 */
				<3 RK_PD0 2 &pcfg_pull_up>,
				/* uart5_tx_m2 */
				<3 RK_PC7 2 &pcfg_pull_up>;
		};

		uart5m2_ctsn: uart5m2-ctsn {
			rockchip,pins =
				/* uart5m2_ctsn */
				<3 RK_PD2 2 &pcfg_pull_none>;
		};
		uart5m2_rtsn: uart5m2-rtsn {
			rockchip,pins =
				/* uart5m2_rtsn */
				<3 RK_PD1 2 &pcfg_pull_none>;
		};
	};

	vicap {
		vicapm0_pins: vicapm0-pins {
			rockchip,pins =
				/* vicap_clkin_m0 */
				<3 RK_PC2 1 &pcfg_pull_none>,
				/* vicap_clkout_m0 */
				<3 RK_PC4 1 &pcfg_pull_none>,
				/* vicap_d0_m0 */
				<3 RK_PB0 1 &pcfg_pull_none>,
				/* vicap_d1_m0 */
				<3 RK_PB1 1 &pcfg_pull_none>,
				/* vicap_d2_m0 */
				<3 RK_PB2 1 &pcfg_pull_none>,
				/* vicap_d3_m0 */
				<3 RK_PB3 1 &pcfg_pull_none>,
				/* vicap_d4_m0 */
				<3 RK_PB4 1 &pcfg_pull_none>,
				/* vicap_d5_m0 */
				<3 RK_PB5 1 &pcfg_pull_none>,
				/* vicap_d6_m0 */
				<3 RK_PB6 1 &pcfg_pull_none>,
				/* vicap_d7_m0 */
				<3 RK_PB7 1 &pcfg_pull_none>,
				/* vicap_d8_m0 */
				<3 RK_PC0 1 &pcfg_pull_none>,
				/* vicap_d9_m0 */
				<3 RK_PC1 1 &pcfg_pull_none>,
				/* vicap_hsync_m0 */
				<3 RK_PC3 1 &pcfg_pull_none>,
				/* vicap_vsync_m0 */
				<3 RK_PC5 1 &pcfg_pull_none>;
		};

		vicapm1_pins: vicapm1-pins {
			rockchip,pins =
				/* vicap_clkin_m1 */
				<1 RK_PD0 2 &pcfg_pull_none>,
				/* vicap_clkout_m1 */
				<1 RK_PD3 2 &pcfg_pull_none>,
				/* vicap_d0_m1 */
				<1 RK_PA2 3 &pcfg_pull_none>,
				/* vicap_d1_m1 */
				<1 RK_PB1 4 &pcfg_pull_none>,
				/* vicap_d2_m1 */
				<1 RK_PC0 2 &pcfg_pull_none>,
				/* vicap_d3_m1 */
				<1 RK_PC1 2 &pcfg_pull_none>,
				/* vicap_d4_m1 */
				<1 RK_PC2 2 &pcfg_pull_none>,
				/* vicap_d5_m1 */
				<1 RK_PC3 2 &pcfg_pull_none>,
				/* vicap_d6_m1 */
				<1 RK_PC4 2 &pcfg_pull_none>,
				/* vicap_d7_m1 */
				<1 RK_PC5 2 &pcfg_pull_none>,
				/* vicap_d8_m1 */
				<1 RK_PC6 2 &pcfg_pull_none>,
				/* vicap_d9_m1 */
				<1 RK_PC7 2 &pcfg_pull_none>,
				/* vicap_hsync_m1 */
				<1 RK_PD1 2 &pcfg_pull_none>,
				/* vicap_vsync_m1 */
				<1 RK_PD2 2 &pcfg_pull_none>;
		};

		vicap_d10: vicap-d10 {
			rockchip,pins =
				/* vicap_d10 */
				<3 RK_PC6 1 &pcfg_pull_none>;
		};
		vicap_d11: vicap-d11 {
			rockchip,pins =
				/* vicap_d11 */
				<3 RK_PC7 1 &pcfg_pull_none>;
		};
		vicap_d12: vicap-d12 {
			rockchip,pins =
				/* vicap_d12 */
				<3 RK_PD0 1 &pcfg_pull_none>;
		};
		vicap_d13: vicap-d13 {
			rockchip,pins =
				/* vicap_d13 */
				<3 RK_PD1 1 &pcfg_pull_none>;
		};
		vicap_d14: vicap-d14 {
			rockchip,pins =
				/* vicap_d14 */
				<3 RK_PD2 1 &pcfg_pull_none>;
		};
		vicap_d15: vicap-d15 {
			rockchip,pins =
				/* vicap_d15 */
				<3 RK_PD3 1 &pcfg_pull_none>;
		};
	};
};