Home
last modified time | relevance | path

Searched +full:16 +full:bit (Results 1 – 25 of 3337) sorted by relevance

12345678910>>...134

/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
[all …]
H A Dsm750_accel.h25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
43 #define DE_CONTROL_STATUS BIT(31)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/
H A Dmac_reg.h29 #define B_AX_GT0_COUNT_EN BIT(31)
30 #define B_AX_GT0_MODE BIT(30)
31 #define B_AX_GT0_EN BIT(29)
32 #define B_AX_GT0_SORT_EN BIT(28)
41 #define B_AX_GT1_COUNT_EN BIT(31)
42 #define B_AX_GT1_MODE BIT(30)
43 #define B_AX_GT1_EN BIT(29)
44 #define B_AX_GT1_SORT_EN BIT(28)
53 #define B_AX_GT2_COUNT_EN BIT(31)
54 #define B_AX_GT2_MODE BIT(30)
[all …]
H A Dtxdesc.h24 #define AX_TXD_MOREDATA BIT(23)
25 #define AX_TXD_WDINFO_EN BIT(22)
26 #define AX_TXD_PKT_OFFSET BIT(21)
27 #define AX_TXD_FWDL_EN BIT(20)
28 #define AX_TXD_CH_DMA_SH 16
32 #define AX_TXD_STF_MODE BIT(10)
33 #define AX_TXD_WP_INT BIT(9)
34 #define AX_TXD_CHK_EN BIT(8)
35 #define AX_TXD_WD_PAGE BIT(7)
36 #define AX_TXD_HW_AES_IV BIT(6)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/
H A Dmac_reg.h29 #define B_AX_GT0_COUNT_EN BIT(31)
30 #define B_AX_GT0_MODE BIT(30)
31 #define B_AX_GT0_EN BIT(29)
32 #define B_AX_GT0_SORT_EN BIT(28)
41 #define B_AX_GT1_COUNT_EN BIT(31)
42 #define B_AX_GT1_MODE BIT(30)
43 #define B_AX_GT1_EN BIT(29)
44 #define B_AX_GT1_SORT_EN BIT(28)
53 #define B_AX_GT2_COUNT_EN BIT(31)
54 #define B_AX_GT2_MODE BIT(30)
[all …]
H A Dtxdesc.h24 #define AX_TXD_MOREDATA BIT(23)
25 #define AX_TXD_WDINFO_EN BIT(22)
26 #define AX_TXD_PKT_OFFSET BIT(21)
27 #define AX_TXD_FWDL_EN BIT(20)
28 #define AX_TXD_CH_DMA_SH 16
32 #define AX_TXD_STF_MODE BIT(10)
33 #define AX_TXD_WP_INT BIT(9)
34 #define AX_TXD_CHK_EN BIT(8)
35 #define AX_TXD_WD_PAGE BIT(7)
36 #define AX_TXD_HW_AES_IV BIT(6)
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c22 .route_val = BIT(16 + 0) | BIT(0),
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
43 .route_val = BIT(16 + 4),
50 .route_val = BIT(16 + 4) | BIT(4),
57 .route_val = BIT(16 + 3),
64 .route_val = BIT(16 + 3),
71 .route_val = BIT(16 + 3) | BIT(3),
78 .route_val = BIT(16 + 3) | BIT(3),
85 .route_val = BIT(16 + 12) | BIT(16 + 13),
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
58 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/OK3568_Linux_fs/kernel/include/soc/mscc/
H A Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
H A Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/
H A Dispreg.h48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
67 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
68 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mediatek/
H A Dmtk_dpi_regs.h10 #define EN BIT(0)
13 #define RST BIT(0)
16 #define INT_VSYNC_EN BIT(0)
17 #define INT_VDE_EN BIT(1)
18 #define INT_UNDERFLOW_EN BIT(2)
21 #define INT_VSYNC_STA BIT(0)
22 #define INT_VDE_STA BIT(1)
23 #define INT_UNDERFLOW_STA BIT(2)
26 #define BG_ENABLE BIT(0)
27 #define IN_RB_SWAP BIT(1)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h244 // CLASS 16 - FLASH
349 // CLASS 16
527 // CLASS 16
530 // Bit definition//
537 #define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7)
552 #define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7)
557 #define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_SH 16
563 #define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7)
568 #define FWCMD_H2CREG_CNSL_CMD_CMD_ID_SH 16
576 #define FWCMD_H2CREG_FWERR_ACK BIT(7)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h244 // CLASS 16 - FLASH
349 // CLASS 16
527 // CLASS 16
530 // Bit definition//
537 #define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7)
552 #define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7)
557 #define FWCMD_H2CREG_H2CREG_LB_PAYLOAD0_SH 16
563 #define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7)
568 #define FWCMD_H2CREG_CNSL_CMD_CMD_ID_SH 16
576 #define FWCMD_H2CREG_FWERR_ACK BIT(7)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2.h28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34 #define XGMAC_CONFIG_GPSL_SHIFT 16
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
42 #define XGMAC_CONFIG_WD BIT(7)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip-mipi-csi-tx.h12 #define m_CONFIG_DONE BIT(0)
13 #define m_CONFIG_DONE_IMD BIT(4)
14 #define m_CONFIG_DONE_MODE BIT(8)
24 #define m_CSITX_EN BIT(0)
25 #define m_CPHY_EN BIT(1)
26 #define m_DPHY_EN BIT(2)
28 #define m_IDI_48BIT_EN BIT(9)
37 #define m_SOFT_RESET BIT(0)
41 #define m_BYPASS_SELECT BIT(0)
45 #define m_VSYNC_ENABLE BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
H A Dmac.h9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
184 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/vc4/
H A Dvc4_regs.h27 ('D' << 16))
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/vsp1/
H A Dvsp1_regs.h18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
39 #define VI6_WFP_IRQ_STA_DFE BIT(1)
40 #define VI6_WFP_IRQ_STA_FRE BIT(0)
43 #define VI6_DISP_IRQ_ENB_DSTE BIT(8)
[all …]
/OK3568_Linux_fs/u-boot/drivers/serial/
H A Dserial_sh.h26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
52 # define SCIF_ORER 0x0200 /* overrun error bit */
54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66 # define SCIF_ORER 0x0001 /* overrun error bit */
71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
[all …]
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/ocrdma/
H A Docrdma_sli.h77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
153 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
154 /* Rearm bit */
155 #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */
156 /* solicited bit */
157 #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */
164 #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */
166 #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */
[all …]

12345678910>>...134