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/OK3568_Linux_fs/kernel/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8516.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
H A Dpinctrl-mt8167.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/netlogic/
H A Dxlp_evp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
H A Dxlp_svp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3588.h68 unsigned int reserved0[16];/* Address Offset: 0x0240 */
69 unsigned int mode_con00;/* Address Offset: 0x0280 */
70 unsigned int reserved1[31];/* Address Offset: 0x0284 */
71 unsigned int clksel_con[178]; /* Address Offset: 0x0300 */
72 unsigned int reserved2[142];/* Address Offset: 0x05c8 */
73 unsigned int clkgate_con[78];/* Address Offset: 0x0800 */
74 unsigned int reserved3[50];/* Address Offset: 0x0938 */
75 unsigned int softrst_con[78];/* Address Offset: 0x0400 */
76 unsigned int reserved4[50];/* Address Offset: 0x0b38 */
77 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8188eu/include/
H A Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/include/
H A DHal8812PhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 #define rCCAonSec_Jaguar 0x838
36 #define rPwed_TH_Jaguar 0x830
39 #define rBWIndication_Jaguar 0x834
40 #define rL1PeakTH_Jaguar 0x848
41 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
42 #define rRFMOD_Jaguar 0x8ac //RF mode
43 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
H A DHal8814PhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 #define rCCAonSec_Jaguar 0x838
36 #define rPwed_TH_Jaguar 0x830
37 #define rL1_Weight_Jaguar 0x840
40 #define rBWIndication_Jaguar 0x834
41 #define rL1PeakTH_Jaguar 0x848
42 #define rRFMOD_Jaguar 0x8ac //RF mode
43 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/include/
H A DHal8812PhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 #define rCCAonSec_Jaguar 0x838
36 #define rPwed_TH_Jaguar 0x830
39 #define rBWIndication_Jaguar 0x834
40 #define rL1PeakTH_Jaguar 0x848
41 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
42 #define rRFMOD_Jaguar 0x8ac //RF mode
43 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
H A DHal8814PhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 #define rCCAonSec_Jaguar 0x838
36 #define rPwed_TH_Jaguar 0x830
37 #define rL1_Weight_Jaguar 0x840
38 #define r_L1_SBD_start_time 0x844
41 #define rBWIndication_Jaguar 0x834
42 #define rL1PeakTH_Jaguar 0x848
43 #define rRFMOD_Jaguar 0x8ac //RF mode
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/rtl8822b/pci/
H A Drtl8822be_io.c27 #define IO_2K_MASK 0xFFFFF800
28 #define IO_4K_MASK 0xFFFFF000
36 u32 rval = 0; in pci_io_read_129x()
38 u32 translate_val = 0; in pci_io_read_129x()
39 u32 tmp_addr = addr & 0xFFF; in pci_io_read_129x()
41 u32 pci_error_status = 0; in pci_io_read_129x()
42 int retry_cnt = 0; in pci_io_read_129x()
47 /* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68 in pci_io_read_129x()
50 if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) && in pci_io_read_129x()
51 (tmp_addr == 0xC68))) { in pci_io_read_129x()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/os_dep/linux/
H A Dpci_ops_linux.c22 #define IO_2K_MASK 0xFFFFF800
23 #define IO_4K_MASK 0xFFFFF000
32 u32 rval = 0; in pci_io_read_129x()
34 u32 translate_val = 0; in pci_io_read_129x()
35 u32 tmp_addr = addr & 0xFFF; in pci_io_read_129x()
36 u32 pci_error_status = 0; in pci_io_read_129x()
37 int retry_cnt = 0; in pci_io_read_129x()
42 /* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68 in pci_io_read_129x()
45 if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) && in pci_io_read_129x()
46 (tmp_addr == 0xC68))) { in pci_io_read_129x()
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/sirf/
H A Dpinctrl-atlas7.c30 #define N 0
33 #define BANK_DS 0
36 #define CLR_REG(r) ((r) + 0x04)
39 #define FUNC_CLEAR_MASK 0x7
40 #define FUNC_GPIO 0
41 #define FUNC_ANALOGUE 0x8
42 #define ANA_CLEAR_MASK 0x1
46 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
60 #define DS0 BIT(0)
61 #define DSZ 0
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h20 #define EXYNOS_GPIO_ECON_OFFSET 0x700
21 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
22 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
23 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
24 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
25 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
26 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
27 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
28 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
29 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/
H A DHal8812PhyReg.h19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
22 * 3. RF register 0x00-2E
30 #define rCCAonSec_Jaguar 0x838
31 #define rPwed_TH_Jaguar 0x830
34 #define rBWIndication_Jaguar 0x834
35 #define rL1PeakTH_Jaguar 0x848
36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
37 #define rRFMOD_Jaguar 0x8ac /* RF mode */
38 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/include/
H A DHal8812PhyReg.h19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
22 * 3. RF register 0x00-2E
30 #define rCCAonSec_Jaguar 0x838
31 #define rPwed_TH_Jaguar 0x830
34 #define rBWIndication_Jaguar 0x834
35 #define rL1PeakTH_Jaguar 0x848
36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
37 #define rRFMOD_Jaguar 0x8ac /* RF mode */
38 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/
H A DHal8812PhyReg.h19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
22 * 3. RF register 0x00-2E
30 #define rCCAonSec_Jaguar 0x838
31 #define rPwed_TH_Jaguar 0x830
34 #define rBWIndication_Jaguar 0x834
35 #define rL1PeakTH_Jaguar 0x848
36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
37 #define rRFMOD_Jaguar 0x8ac /* RF mode */
38 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/
H A DHal8812PhyReg.h19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
22 * 3. RF register 0x00-2E
30 #define rCCAonSec_Jaguar 0x838
31 #define rPwed_TH_Jaguar 0x830
34 #define rBWIndication_Jaguar 0x834
35 #define rL1PeakTH_Jaguar 0x848
36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
37 #define rRFMOD_Jaguar 0x8ac /* RF mode */
38 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/
H A DHal8812PhyReg.h20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
23 * 3. RF register 0x00-2E
31 #define rCCAonSec_Jaguar 0x838
32 #define rPwed_TH_Jaguar 0x830
35 #define rBWIndication_Jaguar 0x834
36 #define rL1PeakTH_Jaguar 0x848
37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
38 #define rRFMOD_Jaguar 0x8ac /* RF mode */
39 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/
H A DHal8812PhyReg.h20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
23 * 3. RF register 0x00-2E
31 #define rCCAonSec_Jaguar 0x838
32 #define rPwed_TH_Jaguar 0x830
35 #define rBWIndication_Jaguar 0x834
36 #define rL1PeakTH_Jaguar 0x848
37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
38 #define rRFMOD_Jaguar 0x8ac /* RF mode */
39 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/
H A DHal8812PhyReg.h20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
23 * 3. RF register 0x00-2E
31 #define rCCAonSec_Jaguar 0x838
32 #define rPwed_TH_Jaguar 0x830
35 #define rBWIndication_Jaguar 0x834
36 #define rL1PeakTH_Jaguar 0x848
37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
38 #define rRFMOD_Jaguar 0x8ac /* RF mode */
39 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/
H A DHal8812PhyReg.h19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
22 * 3. RF register 0x00-2E
30 #define rCCAonSec_Jaguar 0x838
31 #define rPwed_TH_Jaguar 0x830
34 #define rBWIndication_Jaguar 0x834
35 #define rL1PeakTH_Jaguar 0x848
36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
37 #define rRFMOD_Jaguar 0x8ac /* RF mode */
38 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/
H A DHal8812PhyReg.h20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
23 * 3. RF register 0x00-2E
31 #define rCCAonSec_Jaguar 0x838
32 #define rPwed_TH_Jaguar 0x830
35 #define rBWIndication_Jaguar 0x834
36 #define rL1PeakTH_Jaguar 0x848
37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
38 #define rRFMOD_Jaguar 0x8ac /* RF mode */
39 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/
H A DHal8812PhyReg.h20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
23 * 3. RF register 0x00-2E
31 #define rCCAonSec_Jaguar 0x838
32 #define rPwed_TH_Jaguar 0x830
35 #define rBWIndication_Jaguar 0x834
36 #define rL1PeakTH_Jaguar 0x848
37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
38 #define rRFMOD_Jaguar 0x8ac /* RF mode */
39 #define rADC_Buf_Clk_Jaguar 0x8c4
[all …]

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