1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8812PHYREG_H__ 17 #define __INC_HAL8812PHYREG_H__ 18 /*--------------------------Define Parameters-------------------------------*/ 19 /* 20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 21 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 23 * 3. RF register 0x00-2E 24 * 4. Bit Mask for BB/RF register 25 * 5. Other defintion for BB/RF R/W 26 * */ 27 28 29 /* BB Register Definition */ 30 31 #define rCCAonSec_Jaguar 0x838 32 #define rPwed_TH_Jaguar 0x830 33 34 /* BW and sideband setting */ 35 #define rBWIndication_Jaguar 0x834 36 #define rL1PeakTH_Jaguar 0x848 37 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/ 38 #define rRFMOD_Jaguar 0x8ac /* RF mode */ 39 #define rADC_Buf_Clk_Jaguar 0x8c4 40 #define rRFECTRL_Jaguar 0x900 41 #define bRFMOD_Jaguar 0xc3 42 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */ 43 #define bCCK_System_Jaguar 0x10 44 45 /* Block & Path enable */ 46 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ 47 #define bOFDMEN_Jaguar 0x20000000 48 #define bCCKEN_Jaguar 0x10000000 49 #define rRxPath_Jaguar 0x808 /* Rx antenna */ 50 #define bRxPath_Jaguar 0xff 51 #define rTxPath_Jaguar 0x80c /* Tx antenna */ 52 #define bTxPath_Jaguar 0x0fffffff 53 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ 54 #define bCCK_RX_Jaguar 0x0c000000 55 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ 56 57 /* RF read/write-related */ 58 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ 59 #define bHSSIRead_addr_Jaguar 0xff 60 #define bHSSIRead_trigger_Jaguar 0x100 61 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ 62 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ 63 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ 64 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ 65 #define rRead_data_Jaguar 0xfffff 66 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ 67 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ 68 #define bLSSIWrite_data_Jaguar 0x000fffff 69 #define bLSSIWrite_addr_Jaguar 0x0ff00000 70 71 72 73 /* YN: mask the following register definition temporarily */ 74 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 75 #define rFPGA0_XB_RFInterfaceOE 0x864 76 77 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 78 #define rFPGA0_XCD_RFInterfaceSW 0x874 79 80 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter 81 * #define rFPGA0_XCD_RFParameter 0x87c */ 82 83 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? 84 * #define rFPGA0_AnalogParameter2 0x884 85 * #define rFPGA0_AnalogParameter3 0x888 86 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy 87 * #define rFPGA0_AnalogParameter4 0x88c */ 88 89 90 /* CCK TX scaling */ 91 #define rCCK_TxFilter1_Jaguar 0xa20 92 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 93 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 94 #define rCCK_TxFilter2_Jaguar 0xa24 95 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 96 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 97 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 98 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 99 #define rCCK_TxFilter3_Jaguar 0xa28 100 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 101 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 102 103 104 /* YN: mask the following register definition temporarily 105 * #define rPdp_AntA 0xb00 106 * #define rPdp_AntA_4 0xb04 107 * #define rConfig_Pmpd_AntA 0xb28 108 * #define rConfig_AntA 0xb68 109 * #define rConfig_AntB 0xb6c 110 * #define rPdp_AntB 0xb70 111 * #define rPdp_AntB_4 0xb74 112 * #define rConfig_Pmpd_AntB 0xb98 113 * #define rAPK 0xbd8 */ 114 115 /* RXIQC */ 116 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ 117 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ 118 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ 119 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ 120 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ 121 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ 122 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ 123 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ 124 125 126 /* DIG-related */ 127 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ 128 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ 129 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ 130 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ 131 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ 132 #define b_FalseAlarm_Jaguar 0xffff 133 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ 134 #define bCCK_CCA_Jaguar 0x00ff0000 135 136 /* Tx Power Ttraining-related */ 137 #define rA_TxPwrTraing_Jaguar 0xc54 138 #define rB_TxPwrTraing_Jaguar 0xe54 139 140 /* Report-related */ 141 #define rOFDM_ShortCFOAB_Jaguar 0xf60 142 #define rOFDM_LongCFOAB_Jaguar 0xf64 143 #define rOFDM_EndCFOAB_Jaguar 0xf70 144 #define rOFDM_AGCReport_Jaguar 0xf84 145 #define rOFDM_RxSNR_Jaguar 0xf88 146 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 147 #define rOFDM_SIGReport_Jaguar 0xf90 148 149 /* Misc functions */ 150 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */ 151 #define bEDCCA_Jaguar 0xffff 152 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */ 153 #define bAGC_table_Jaguar 0x3 154 #define b_sel5g_Jaguar 0x1000 /* sel5g */ 155 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ 156 #define rFc_area_Jaguar 0x860 /* fc_area */ 157 #define bFc_area_Jaguar 0x1ffe000 158 #define rSingleTone_ContTx_Jaguar 0x914 159 160 /* RFE */ 161 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ 162 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ 163 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ 164 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ 165 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ 166 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ 167 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 168 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 169 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 170 #define bMask_RFEInv_Jaguar 0x3ff00000 171 #define bMask_AntselPathFollow_Jaguar 0x00030000 172 173 /* TX AGC */ 174 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 175 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 176 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 177 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 178 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 179 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 180 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 181 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 182 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 183 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 184 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 185 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 186 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 187 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 188 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 189 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 190 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 191 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 192 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 193 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 194 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 195 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 196 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 197 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 198 #define bTxAGC_byte0_Jaguar 0xff 199 #define bTxAGC_byte1_Jaguar 0xff00 200 #define bTxAGC_byte2_Jaguar 0xff0000 201 #define bTxAGC_byte3_Jaguar 0xff000000 202 203 /* IQK YN: temporaily mask this part 204 * #define rFPGA0_IQK 0xe28 205 * #define rTx_IQK_Tone_A 0xe30 206 * #define rRx_IQK_Tone_A 0xe34 207 * #define rTx_IQK_PI_A 0xe38 208 * #define rRx_IQK_PI_A 0xe3c */ 209 210 /* #define rTx_IQK 0xe40 */ 211 /* #define rRx_IQK 0xe44 */ 212 /* #define rIQK_AGC_Pts 0xe48 */ 213 /* #define rIQK_AGC_Rsp 0xe4c */ 214 /* #define rTx_IQK_Tone_B 0xe50 */ 215 /* #define rRx_IQK_Tone_B 0xe54 */ 216 /* #define rTx_IQK_PI_B 0xe58 */ 217 /* #define rRx_IQK_PI_B 0xe5c */ 218 /* #define rIQK_AGC_Cont 0xe60 */ 219 220 221 /* AFE-related */ 222 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ 223 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ 224 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 225 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 226 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 227 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 228 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 229 #define rA_Rx2Rx_BT_Jaguar 0xc7c 230 #define rA_sleep_nav_Jaguar 0xc80 231 #define rA_pmpd_Jaguar 0xc84 232 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ 233 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ 234 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 235 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 236 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 237 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 238 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 239 #define rB_Rx2Rx_BT_Jaguar 0xe7c 240 #define rB_sleep_nav_Jaguar 0xe80 241 #define rB_pmpd_Jaguar 0xe84 242 243 244 /* YN: mask these registers temporaily 245 * #define rTx_Power_Before_IQK_A 0xe94 246 * #define rTx_Power_After_IQK_A 0xe9c */ 247 248 /* #define rRx_Power_Before_IQK_A 0xea0 */ 249 /* #define rRx_Power_Before_IQK_A_2 0xea4 */ 250 /* #define rRx_Power_After_IQK_A 0xea8 */ 251 /* #define rRx_Power_After_IQK_A_2 0xeac */ 252 253 /* #define rTx_Power_Before_IQK_B 0xeb4 */ 254 /* #define rTx_Power_After_IQK_B 0xebc */ 255 256 /* #define rRx_Power_Before_IQK_B 0xec0 */ 257 /* #define rRx_Power_Before_IQK_B_2 0xec4 */ 258 /* #define rRx_Power_After_IQK_B 0xec8 */ 259 /* #define rRx_Power_After_IQK_B_2 0xecc */ 260 261 262 /* RSSI Dump */ 263 #define rA_RSSIDump_Jaguar 0xBF0 264 #define rB_RSSIDump_Jaguar 0xBF1 265 #define rS1_RXevmDump_Jaguar 0xBF4 266 #define rS2_RXevmDump_Jaguar 0xBF5 267 #define rA_RXsnrDump_Jaguar 0xBF6 268 #define rB_RXsnrDump_Jaguar 0xBF7 269 #define rA_CfoShortDump_Jaguar 0xBF8 270 #define rB_CfoShortDump_Jaguar 0xBFA 271 #define rA_CfoLongDump_Jaguar 0xBEC 272 #define rB_CfoLongDump_Jaguar 0xBEE 273 274 275 /* RF Register 276 * */ 277 #define RF_AC_Jaguar 0x00 /* */ 278 #define RF_RF_Top_Jaguar 0x07 /* */ 279 #define RF_TXLOK_Jaguar 0x08 /* */ 280 #define RF_TXAPK_Jaguar 0x0B 281 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ 282 #define RF_RCK1_Jaguar 0x1c /* */ 283 #define RF_RCK2_Jaguar 0x1d 284 #define RF_RCK3_Jaguar 0x1e 285 #define RF_ModeTableAddr 0x30 286 #define RF_ModeTableData0 0x31 287 #define RF_ModeTableData1 0x32 288 #define RF_TxLCTank_Jaguar 0x54 289 #define RF_APK_Jaguar 0x63 290 #define RF_LCK 0xB4 291 #define RF_WeLut_Jaguar 0xEF 292 293 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 294 #define bRF_CHNLBW_BW 0xc00 295 296 297 /* 298 * RL6052 Register definition 299 * */ 300 #define RF_AC 0x00 /* */ 301 #define RF_IPA_A 0x0C /* */ 302 #define RF_TXBIAS_A 0x0D 303 #define RF_BS_PA_APSET_G9_G11 0x0E 304 #define RF_MODE1 0x10 /* */ 305 #define RF_MODE2 0x11 /* */ 306 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 307 #define RF_RCK_OS 0x30 /* RF TX PA control */ 308 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 309 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 310 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 311 #define RF_0x52 0x52 312 #define RF_WE_LUT 0xEF 313 314 #define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 315 #define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 316 317 /* 318 * Bit Mask 319 * 320 * 1. Page1(0x100) */ 321 #define bBBResetB 0x100 /* Useless now? */ 322 #define bGlobalResetB 0x200 323 #define bOFDMTxStart 0x4 324 #define bCCKTxStart 0x8 325 #define bCRC32Debug 0x100 326 #define bPMACLoopback 0x10 327 #define bTxLSIG 0xffffff 328 #define bOFDMTxRate 0xf 329 #define bOFDMTxReserved 0x10 330 #define bOFDMTxLength 0x1ffe0 331 #define bOFDMTxParity 0x20000 332 #define bTxHTSIG1 0xffffff 333 #define bTxHTMCSRate 0x7f 334 #define bTxHTBW 0x80 335 #define bTxHTLength 0xffff00 336 #define bTxHTSIG2 0xffffff 337 #define bTxHTSmoothing 0x1 338 #define bTxHTSounding 0x2 339 #define bTxHTReserved 0x4 340 #define bTxHTAggreation 0x8 341 #define bTxHTSTBC 0x30 342 #define bTxHTAdvanceCoding 0x40 343 #define bTxHTShortGI 0x80 344 #define bTxHTNumberHT_LTF 0x300 345 #define bTxHTCRC8 0x3fc00 346 #define bCounterReset 0x10000 347 #define bNumOfOFDMTx 0xffff 348 #define bNumOfCCKTx 0xffff0000 349 #define bTxIdleInterval 0xffff 350 #define bOFDMService 0xffff0000 351 #define bTxMACHeader 0xffffffff 352 #define bTxDataInit 0xff 353 #define bTxHTMode 0x100 354 #define bTxDataType 0x30000 355 #define bTxRandomSeed 0xffffffff 356 #define bCCKTxPreamble 0x1 357 #define bCCKTxSFD 0xffff0000 358 #define bCCKTxSIG 0xff 359 #define bCCKTxService 0xff00 360 #define bCCKLengthExt 0x8000 361 #define bCCKTxLength 0xffff0000 362 #define bCCKTxCRC16 0xffff 363 #define bCCKTxStatus 0x1 364 #define bOFDMTxStatus 0x2 365 366 367 /* 368 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 369 * 1. Page1(0x100) 370 * */ 371 #define rPMAC_Reset 0x100 372 #define rPMAC_TxStart 0x104 373 #define rPMAC_TxLegacySIG 0x108 374 #define rPMAC_TxHTSIG1 0x10c 375 #define rPMAC_TxHTSIG2 0x110 376 #define rPMAC_PHYDebug 0x114 377 #define rPMAC_TxPacketNum 0x118 378 #define rPMAC_TxIdle 0x11c 379 #define rPMAC_TxMACHeader0 0x120 380 #define rPMAC_TxMACHeader1 0x124 381 #define rPMAC_TxMACHeader2 0x128 382 #define rPMAC_TxMACHeader3 0x12c 383 #define rPMAC_TxMACHeader4 0x130 384 #define rPMAC_TxMACHeader5 0x134 385 #define rPMAC_TxDataType 0x138 386 #define rPMAC_TxRandomSeed 0x13c 387 #define rPMAC_CCKPLCPPreamble 0x140 388 #define rPMAC_CCKPLCPHeader 0x144 389 #define rPMAC_CCKCRC16 0x148 390 #define rPMAC_OFDMRxCRC32OK 0x170 391 #define rPMAC_OFDMRxCRC32Er 0x174 392 #define rPMAC_OFDMRxParityEr 0x178 393 #define rPMAC_OFDMRxCRC8Er 0x17c 394 #define rPMAC_CCKCRxRC16Er 0x180 395 #define rPMAC_CCKCRxRC32Er 0x184 396 #define rPMAC_CCKCRxRC32OK 0x188 397 #define rPMAC_TxStatus 0x18c 398 399 /* 400 * 3. Page8(0x800) 401 * */ 402 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 403 404 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 405 #define rFPGA0_PSDFunction 0x808 406 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 407 408 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 409 #define rFPGA0_XA_HSSIParameter2 0x824 410 #define rFPGA0_XB_HSSIParameter1 0x828 411 #define rFPGA0_XB_HSSIParameter2 0x82c 412 413 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 414 #define rFPGA0_XCD_SwitchControl 0x85c 415 416 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 417 #define rFPGA0_XCD_RFParameter 0x87c 418 419 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 420 #define rFPGA0_AnalogParameter2 0x884 421 #define rFPGA0_AnalogParameter3 0x888 422 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 423 #define rFPGA0_AnalogParameter4 0x88c 424 #define rFPGA0_XB_LSSIReadBack 0x8a4 425 #define rFPGA0_XCD_RFPara 0x8b4 426 427 /* 428 * 4. Page9(0x900) 429 * */ 430 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 431 432 #define rFPGA1_TxBlock 0x904 /* Useless now */ 433 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 434 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 435 436 /* 437 * PageA(0xA00) 438 * */ 439 #define rCCK0_System 0xa00 440 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 441 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 442 #define rCCK0_TxFilter1 0xa20 443 #define rCCK0_TxFilter2 0xa24 444 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 445 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 446 447 /* 448 * PageB(0xB00) 449 * */ 450 #define rPdp_AntA 0xb00 451 #define rPdp_AntA_4 0xb04 452 #define rConfig_Pmpd_AntA 0xb28 453 #define rConfig_AntA 0xb68 454 #define rConfig_AntB 0xb6c 455 #define rPdp_AntB 0xb70 456 #define rPdp_AntB_4 0xb74 457 #define rConfig_Pmpd_AntB 0xb98 458 #define rAPK 0xbd8 459 460 /* 461 * 6. PageC(0xC00) 462 * */ 463 #define rOFDM0_LSTF 0xc00 464 465 #define rOFDM0_TRxPathEnable 0xc04 466 #define rOFDM0_TRMuxPar 0xc08 467 #define rOFDM0_TRSWIsolation 0xc0c 468 469 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 470 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 471 #define rOFDM0_XBRxAFE 0xc18 472 #define rOFDM0_XBRxIQImbalance 0xc1c 473 #define rOFDM0_XCRxAFE 0xc20 474 #define rOFDM0_XCRxIQImbalance 0xc24 475 #define rOFDM0_XDRxAFE 0xc28 476 #define rOFDM0_XDRxIQImbalance 0xc2c 477 478 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 479 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 480 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 481 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 482 483 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 484 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 485 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 486 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 487 488 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 489 #define rOFDM0_XAAGCCore2 0xc54 490 #define rOFDM0_XBAGCCore1 0xc58 491 #define rOFDM0_XBAGCCore2 0xc5c 492 #define rOFDM0_XCAGCCore1 0xc60 493 #define rOFDM0_XCAGCCore2 0xc64 494 #define rOFDM0_XDAGCCore1 0xc68 495 #define rOFDM0_XDAGCCore2 0xc6c 496 497 #define rOFDM0_AGCParameter1 0xc70 498 #define rOFDM0_AGCParameter2 0xc74 499 #define rOFDM0_AGCRSSITable 0xc78 500 #define rOFDM0_HTSTFAGC 0xc7c 501 502 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 503 #define rOFDM0_XATxAFE 0xc84 504 #define rOFDM0_XBTxIQImbalance 0xc88 505 #define rOFDM0_XBTxAFE 0xc8c 506 #define rOFDM0_XCTxIQImbalance 0xc90 507 #define rOFDM0_XCTxAFE 0xc94 508 #define rOFDM0_XDTxIQImbalance 0xc98 509 #define rOFDM0_XDTxAFE 0xc9c 510 511 #define rOFDM0_RxIQExtAnta 0xca0 512 #define rOFDM0_TxCoeff1 0xca4 513 #define rOFDM0_TxCoeff2 0xca8 514 #define rOFDM0_TxCoeff3 0xcac 515 #define rOFDM0_TxCoeff4 0xcb0 516 #define rOFDM0_TxCoeff5 0xcb4 517 #define rOFDM0_TxCoeff6 0xcb8 518 #define rOFDM0_RxHPParameter 0xce0 519 #define rOFDM0_TxPseudoNoiseWgt 0xce4 520 #define rOFDM0_FrameSync 0xcf0 521 #define rOFDM0_DFSReport 0xcf4 522 523 /* 524 * 7. PageD(0xD00) 525 * */ 526 #define rOFDM1_LSTF 0xd00 527 #define rOFDM1_TRxPathEnable 0xd04 528 529 /* 530 * 8. PageE(0xE00) 531 * */ 532 #define rTxAGC_A_Rate18_06 0xe00 533 #define rTxAGC_A_Rate54_24 0xe04 534 #define rTxAGC_A_CCK1_Mcs32 0xe08 535 #define rTxAGC_A_Mcs03_Mcs00 0xe10 536 #define rTxAGC_A_Mcs07_Mcs04 0xe14 537 #define rTxAGC_A_Mcs11_Mcs08 0xe18 538 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 539 540 #define rTxAGC_B_Rate18_06 0x830 541 #define rTxAGC_B_Rate54_24 0x834 542 #define rTxAGC_B_CCK1_55_Mcs32 0x838 543 #define rTxAGC_B_Mcs03_Mcs00 0x83c 544 #define rTxAGC_B_Mcs07_Mcs04 0x848 545 #define rTxAGC_B_Mcs11_Mcs08 0x84c 546 #define rTxAGC_B_Mcs15_Mcs12 0x868 547 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 548 549 #define rFPGA0_IQK 0xe28 550 #define rTx_IQK_Tone_A 0xe30 551 #define rRx_IQK_Tone_A 0xe34 552 #define rTx_IQK_PI_A 0xe38 553 #define rRx_IQK_PI_A 0xe3c 554 555 #define rTx_IQK 0xe40 556 #define rRx_IQK 0xe44 557 #define rIQK_AGC_Pts 0xe48 558 #define rIQK_AGC_Rsp 0xe4c 559 #define rTx_IQK_Tone_B 0xe50 560 #define rRx_IQK_Tone_B 0xe54 561 #define rTx_IQK_PI_B 0xe58 562 #define rRx_IQK_PI_B 0xe5c 563 #define rIQK_AGC_Cont 0xe60 564 565 #define rBlue_Tooth 0xe6c 566 #define rRx_Wait_CCA 0xe70 567 #define rTx_CCK_RFON 0xe74 568 #define rTx_CCK_BBON 0xe78 569 #define rTx_OFDM_RFON 0xe7c 570 #define rTx_OFDM_BBON 0xe80 571 #define rTx_To_Rx 0xe84 572 #define rTx_To_Tx 0xe88 573 #define rRx_CCK 0xe8c 574 575 #define rTx_Power_Before_IQK_A 0xe94 576 #define rTx_Power_After_IQK_A 0xe9c 577 578 #define rRx_Power_Before_IQK_A 0xea0 579 #define rRx_Power_Before_IQK_A_2 0xea4 580 #define rRx_Power_After_IQK_A 0xea8 581 #define rRx_Power_After_IQK_A_2 0xeac 582 583 #define rTx_Power_Before_IQK_B 0xeb4 584 #define rTx_Power_After_IQK_B 0xebc 585 586 #define rRx_Power_Before_IQK_B 0xec0 587 #define rRx_Power_Before_IQK_B_2 0xec4 588 #define rRx_Power_After_IQK_B 0xec8 589 #define rRx_Power_After_IQK_B_2 0xecc 590 591 #define rRx_OFDM 0xed0 592 #define rRx_Wait_RIFS 0xed4 593 #define rRx_TO_Rx 0xed8 594 #define rStandby 0xedc 595 #define rSleep 0xee0 596 #define rPMPD_ANAEN 0xeec 597 598 599 /* 2. Page8(0x800) */ 600 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 601 #define bJapanMode 0x2 602 #define bCCKTxSC 0x30 603 #define bCCKEn 0x1000000 604 #define bOFDMEn 0x2000000 605 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 606 #define bXCTxAGC 0xf000 607 #define bXDTxAGC 0xf0000 608 609 /* 4. PageA(0xA00) */ 610 #define bCCKBBMode 0x3 /* Useless */ 611 #define bCCKTxPowerSaving 0x80 612 #define bCCKRxPowerSaving 0x40 613 614 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 615 616 #define bCCKScramble 0x8 /* Useless */ 617 #define bCCKAntDiversity 0x8000 618 #define bCCKCarrierRecovery 0x4000 619 #define bCCKTxRate 0x3000 620 #define bCCKDCCancel 0x0800 621 #define bCCKISICancel 0x0400 622 #define bCCKMatchFilter 0x0200 623 #define bCCKEqualizer 0x0100 624 #define bCCKPreambleDetect 0x800000 625 #define bCCKFastFalseCCA 0x400000 626 #define bCCKChEstStart 0x300000 627 #define bCCKCCACount 0x080000 628 #define bCCKcs_lim 0x070000 629 #define bCCKBistMode 0x80000000 630 #define bCCKCCAMask 0x40000000 631 #define bCCKTxDACPhase 0x4 632 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 633 #define bCCKr_cp_mode0 0x0100 634 #define bCCKTxDCOffset 0xf0 635 #define bCCKRxDCOffset 0xf 636 #define bCCKCCAMode 0xc000 637 #define bCCKFalseCS_lim 0x3f00 638 #define bCCKCS_ratio 0xc00000 639 #define bCCKCorgBit_sel 0x300000 640 #define bCCKPD_lim 0x0f0000 641 #define bCCKNewCCA 0x80000000 642 #define bCCKRxHPofIG 0x8000 643 #define bCCKRxIG 0x7f00 644 #define bCCKLNAPolarity 0x800000 645 #define bCCKRx1stGain 0x7f0000 646 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 647 #define bCCKRxAGCSatLevel 0x1f000000 648 #define bCCKRxAGCSatCount 0xe0 649 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 650 #define bCCKFixedRxAGC 0x8000 651 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 652 #define bCCKAntennaPolarity 0x2000 653 #define bCCKTxFilterType 0x0c00 654 #define bCCKRxAGCReportType 0x0300 655 #define bCCKRxDAGCEn 0x80000000 656 #define bCCKRxDAGCPeriod 0x20000000 657 #define bCCKRxDAGCSatLevel 0x1f000000 658 #define bCCKTimingRecovery 0x800000 659 #define bCCKTxC0 0x3f0000 660 #define bCCKTxC1 0x3f000000 661 #define bCCKTxC2 0x3f 662 #define bCCKTxC3 0x3f00 663 #define bCCKTxC4 0x3f0000 664 #define bCCKTxC5 0x3f000000 665 #define bCCKTxC6 0x3f 666 #define bCCKTxC7 0x3f00 667 #define bCCKDebugPort 0xff0000 668 #define bCCKDACDebug 0x0f000000 669 #define bCCKFalseAlarmEnable 0x8000 670 #define bCCKFalseAlarmRead 0x4000 671 #define bCCKTRSSI 0x7f 672 #define bCCKRxAGCReport 0xfe 673 #define bCCKRxReport_AntSel 0x80000000 674 #define bCCKRxReport_MFOff 0x40000000 675 #define bCCKRxRxReport_SQLoss 0x20000000 676 #define bCCKRxReport_Pktloss 0x10000000 677 #define bCCKRxReport_Lockedbit 0x08000000 678 #define bCCKRxReport_RateError 0x04000000 679 #define bCCKRxReport_RxRate 0x03000000 680 #define bCCKRxFACounterLower 0xff 681 #define bCCKRxFACounterUpper 0xff000000 682 #define bCCKRxHPAGCStart 0xe000 683 #define bCCKRxHPAGCFinal 0x1c00 684 #define bCCKRxFalseAlarmEnable 0x8000 685 #define bCCKFACounterFreeze 0x4000 686 #define bCCKTxPathSel 0x10000000 687 #define bCCKDefaultRxPath 0xc000000 688 #define bCCKOptionRxPath 0x3000000 689 690 /* 6. PageE(0xE00) */ 691 #define bSTBCEn 0x4 /* Useless */ 692 #define bAntennaMapping 0x10 693 #define bNss 0x20 694 #define bCFOAntSumD 0x200 695 #define bPHYCounterReset 0x8000000 696 #define bCFOReportGet 0x4000000 697 #define bOFDMContinueTx 0x10000000 698 #define bOFDMSingleCarrier 0x20000000 699 #define bOFDMSingleTone 0x40000000 700 701 702 /* 703 * Other Definition 704 * */ 705 706 #define bEnable 0x1 /* Useless */ 707 #define bDisable 0x0 708 709 /* byte endable for srwrite */ 710 #define bByte0 0x1 /* Useless */ 711 #define bByte1 0x2 712 #define bByte2 0x4 713 #define bByte3 0x8 714 #define bWord0 0x3 715 #define bWord1 0xc 716 #define bDWord 0xf 717 718 /* for PutRegsetting & GetRegSetting BitMask */ 719 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 720 #define bMaskByte1 0xff00 721 #define bMaskByte2 0xff0000 722 #define bMaskByte3 0xff000000 723 #define bMaskHWord 0xffff0000 724 #define bMaskLWord 0x0000ffff 725 #define bMaskDWord 0xffffffff 726 #define bMaskH3Bytes 0xffffff00 727 #define bMask12Bits 0xfff 728 #define bMaskH4Bits 0xf0000000 729 #define bMaskOFDM_D 0xffc00000 730 #define bMaskCCK 0x3f3f3f3f 731 732 733 /*--------------------------Define Parameters-------------------------------*/ 734 735 736 #endif 737