1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8812PHYREG_H__ 16 #define __INC_HAL8812PHYREG_H__ 17 /*--------------------------Define Parameters-------------------------------*/ 18 /* 19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 20 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 22 * 3. RF register 0x00-2E 23 * 4. Bit Mask for BB/RF register 24 * 5. Other defintion for BB/RF R/W 25 * */ 26 27 28 /* BB Register Definition */ 29 30 #define rCCAonSec_Jaguar 0x838 31 #define rPwed_TH_Jaguar 0x830 32 33 /* BW and sideband setting */ 34 #define rBWIndication_Jaguar 0x834 35 #define rL1PeakTH_Jaguar 0x848 36 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/ 37 #define rRFMOD_Jaguar 0x8ac /* RF mode */ 38 #define rADC_Buf_Clk_Jaguar 0x8c4 39 #define rRFECTRL_Jaguar 0x900 40 #define bRFMOD_Jaguar 0xc3 41 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */ 42 #define bCCK_System_Jaguar 0x10 43 44 /* Block & Path enable */ 45 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ 46 #define bOFDMEN_Jaguar 0x20000000 47 #define bCCKEN_Jaguar 0x10000000 48 #define rRxPath_Jaguar 0x808 /* Rx antenna */ 49 #define bRxPath_Jaguar 0xff 50 #define rTxPath_Jaguar 0x80c /* Tx antenna */ 51 #define bTxPath_Jaguar 0x0fffffff 52 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ 53 #define bCCK_RX_Jaguar 0x0c000000 54 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ 55 56 /* RF read/write-related */ 57 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ 58 #define bHSSIRead_addr_Jaguar 0xff 59 #define bHSSIRead_trigger_Jaguar 0x100 60 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ 61 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ 62 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ 63 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ 64 #define rRead_data_Jaguar 0xfffff 65 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ 66 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ 67 #define bLSSIWrite_data_Jaguar 0x000fffff 68 #define bLSSIWrite_addr_Jaguar 0x0ff00000 69 70 71 72 /* YN: mask the following register definition temporarily */ 73 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 74 #define rFPGA0_XB_RFInterfaceOE 0x864 75 76 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 77 #define rFPGA0_XCD_RFInterfaceSW 0x874 78 79 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter 80 * #define rFPGA0_XCD_RFParameter 0x87c */ 81 82 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? 83 * #define rFPGA0_AnalogParameter2 0x884 84 * #define rFPGA0_AnalogParameter3 0x888 85 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy 86 * #define rFPGA0_AnalogParameter4 0x88c */ 87 88 89 /* CCK TX scaling */ 90 #define rCCK_TxFilter1_Jaguar 0xa20 91 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 92 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 93 #define rCCK_TxFilter2_Jaguar 0xa24 94 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 95 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 96 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 97 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 98 #define rCCK_TxFilter3_Jaguar 0xa28 99 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 100 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 101 102 103 /* YN: mask the following register definition temporarily 104 * #define rPdp_AntA 0xb00 105 * #define rPdp_AntA_4 0xb04 106 * #define rConfig_Pmpd_AntA 0xb28 107 * #define rConfig_AntA 0xb68 108 * #define rConfig_AntB 0xb6c 109 * #define rPdp_AntB 0xb70 110 * #define rPdp_AntB_4 0xb74 111 * #define rConfig_Pmpd_AntB 0xb98 112 * #define rAPK 0xbd8 */ 113 114 /* RXIQC */ 115 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ 116 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ 117 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ 118 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ 119 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ 120 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ 121 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ 122 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ 123 124 125 /* DIG-related */ 126 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ 127 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ 128 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ 129 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ 130 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ 131 #define b_FalseAlarm_Jaguar 0xffff 132 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ 133 #define bCCK_CCA_Jaguar 0x00ff0000 134 135 /* Tx Power Ttraining-related */ 136 #define rA_TxPwrTraing_Jaguar 0xc54 137 #define rB_TxPwrTraing_Jaguar 0xe54 138 139 /* Report-related */ 140 #define rOFDM_ShortCFOAB_Jaguar 0xf60 141 #define rOFDM_LongCFOAB_Jaguar 0xf64 142 #define rOFDM_EndCFOAB_Jaguar 0xf70 143 #define rOFDM_AGCReport_Jaguar 0xf84 144 #define rOFDM_RxSNR_Jaguar 0xf88 145 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 146 #define rOFDM_SIGReport_Jaguar 0xf90 147 148 /* Misc functions */ 149 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */ 150 #define bEDCCA_Jaguar 0xffff 151 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */ 152 #define bAGC_table_Jaguar 0x3 153 #define b_sel5g_Jaguar 0x1000 /* sel5g */ 154 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ 155 #define rFc_area_Jaguar 0x860 /* fc_area */ 156 #define bFc_area_Jaguar 0x1ffe000 157 #define rSingleTone_ContTx_Jaguar 0x914 158 159 /* RFE */ 160 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ 161 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ 162 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ 163 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ 164 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ 165 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ 166 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 167 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 168 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 169 #define bMask_RFEInv_Jaguar 0x3ff00000 170 #define bMask_AntselPathFollow_Jaguar 0x00030000 171 172 /* TX AGC */ 173 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 174 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 175 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 176 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 177 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 178 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 179 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 180 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 181 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 182 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 183 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 184 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 185 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 186 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 187 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 188 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 189 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 190 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 191 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 192 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 193 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 194 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 195 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 196 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 197 #define bTxAGC_byte0_Jaguar 0xff 198 #define bTxAGC_byte1_Jaguar 0xff00 199 #define bTxAGC_byte2_Jaguar 0xff0000 200 #define bTxAGC_byte3_Jaguar 0xff000000 201 202 /* IQK YN: temporaily mask this part 203 * #define rFPGA0_IQK 0xe28 204 * #define rTx_IQK_Tone_A 0xe30 205 * #define rRx_IQK_Tone_A 0xe34 206 * #define rTx_IQK_PI_A 0xe38 207 * #define rRx_IQK_PI_A 0xe3c */ 208 209 /* #define rTx_IQK 0xe40 */ 210 /* #define rRx_IQK 0xe44 */ 211 /* #define rIQK_AGC_Pts 0xe48 */ 212 /* #define rIQK_AGC_Rsp 0xe4c */ 213 /* #define rTx_IQK_Tone_B 0xe50 */ 214 /* #define rRx_IQK_Tone_B 0xe54 */ 215 /* #define rTx_IQK_PI_B 0xe58 */ 216 /* #define rRx_IQK_PI_B 0xe5c */ 217 /* #define rIQK_AGC_Cont 0xe60 */ 218 219 220 /* AFE-related */ 221 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ 222 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ 223 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 224 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 225 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 226 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 227 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 228 #define rA_Rx2Rx_BT_Jaguar 0xc7c 229 #define rA_sleep_nav_Jaguar 0xc80 230 #define rA_pmpd_Jaguar 0xc84 231 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ 232 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ 233 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 234 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 235 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 236 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 237 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 238 #define rB_Rx2Rx_BT_Jaguar 0xe7c 239 #define rB_sleep_nav_Jaguar 0xe80 240 #define rB_pmpd_Jaguar 0xe84 241 242 243 /* YN: mask these registers temporaily 244 * #define rTx_Power_Before_IQK_A 0xe94 245 * #define rTx_Power_After_IQK_A 0xe9c */ 246 247 /* #define rRx_Power_Before_IQK_A 0xea0 */ 248 /* #define rRx_Power_Before_IQK_A_2 0xea4 */ 249 /* #define rRx_Power_After_IQK_A 0xea8 */ 250 /* #define rRx_Power_After_IQK_A_2 0xeac */ 251 252 /* #define rTx_Power_Before_IQK_B 0xeb4 */ 253 /* #define rTx_Power_After_IQK_B 0xebc */ 254 255 /* #define rRx_Power_Before_IQK_B 0xec0 */ 256 /* #define rRx_Power_Before_IQK_B_2 0xec4 */ 257 /* #define rRx_Power_After_IQK_B 0xec8 */ 258 /* #define rRx_Power_After_IQK_B_2 0xecc */ 259 260 261 /* RSSI Dump */ 262 #define rA_RSSIDump_Jaguar 0xBF0 263 #define rB_RSSIDump_Jaguar 0xBF1 264 #define rS1_RXevmDump_Jaguar 0xBF4 265 #define rS2_RXevmDump_Jaguar 0xBF5 266 #define rA_RXsnrDump_Jaguar 0xBF6 267 #define rB_RXsnrDump_Jaguar 0xBF7 268 #define rA_CfoShortDump_Jaguar 0xBF8 269 #define rB_CfoShortDump_Jaguar 0xBFA 270 #define rA_CfoLongDump_Jaguar 0xBEC 271 #define rB_CfoLongDump_Jaguar 0xBEE 272 273 274 /* RF Register 275 * */ 276 #define RF_AC_Jaguar 0x00 /* */ 277 #define RF_RF_Top_Jaguar 0x07 /* */ 278 #define RF_TXLOK_Jaguar 0x08 /* */ 279 #define RF_TXAPK_Jaguar 0x0B 280 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ 281 #define RF_RCK1_Jaguar 0x1c /* */ 282 #define RF_RCK2_Jaguar 0x1d 283 #define RF_RCK3_Jaguar 0x1e 284 #define RF_ModeTableAddr 0x30 285 #define RF_ModeTableData0 0x31 286 #define RF_ModeTableData1 0x32 287 #define RF_TxLCTank_Jaguar 0x54 288 #define RF_APK_Jaguar 0x63 289 #define RF_LCK 0xB4 290 #define RF_WeLut_Jaguar 0xEF 291 292 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 293 #define bRF_CHNLBW_BW 0xc00 294 295 296 /* 297 * RL6052 Register definition 298 * */ 299 #define RF_AC 0x00 /* */ 300 #define RF_IPA_A 0x0C /* */ 301 #define RF_TXBIAS_A 0x0D 302 #define RF_BS_PA_APSET_G9_G11 0x0E 303 #define RF_MODE1 0x10 /* */ 304 #define RF_MODE2 0x11 /* */ 305 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 306 #define RF_RCK_OS 0x30 /* RF TX PA control */ 307 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 308 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 309 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 310 #define RF_0x52 0x52 311 #define RF_WE_LUT 0xEF 312 313 #define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 314 #define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 315 316 /* 317 * Bit Mask 318 * 319 * 1. Page1(0x100) */ 320 #define bBBResetB 0x100 /* Useless now? */ 321 #define bGlobalResetB 0x200 322 #define bOFDMTxStart 0x4 323 #define bCCKTxStart 0x8 324 #define bCRC32Debug 0x100 325 #define bPMACLoopback 0x10 326 #define bTxLSIG 0xffffff 327 #define bOFDMTxRate 0xf 328 #define bOFDMTxReserved 0x10 329 #define bOFDMTxLength 0x1ffe0 330 #define bOFDMTxParity 0x20000 331 #define bTxHTSIG1 0xffffff 332 #define bTxHTMCSRate 0x7f 333 #define bTxHTBW 0x80 334 #define bTxHTLength 0xffff00 335 #define bTxHTSIG2 0xffffff 336 #define bTxHTSmoothing 0x1 337 #define bTxHTSounding 0x2 338 #define bTxHTReserved 0x4 339 #define bTxHTAggreation 0x8 340 #define bTxHTSTBC 0x30 341 #define bTxHTAdvanceCoding 0x40 342 #define bTxHTShortGI 0x80 343 #define bTxHTNumberHT_LTF 0x300 344 #define bTxHTCRC8 0x3fc00 345 #define bCounterReset 0x10000 346 #define bNumOfOFDMTx 0xffff 347 #define bNumOfCCKTx 0xffff0000 348 #define bTxIdleInterval 0xffff 349 #define bOFDMService 0xffff0000 350 #define bTxMACHeader 0xffffffff 351 #define bTxDataInit 0xff 352 #define bTxHTMode 0x100 353 #define bTxDataType 0x30000 354 #define bTxRandomSeed 0xffffffff 355 #define bCCKTxPreamble 0x1 356 #define bCCKTxSFD 0xffff0000 357 #define bCCKTxSIG 0xff 358 #define bCCKTxService 0xff00 359 #define bCCKLengthExt 0x8000 360 #define bCCKTxLength 0xffff0000 361 #define bCCKTxCRC16 0xffff 362 #define bCCKTxStatus 0x1 363 #define bOFDMTxStatus 0x2 364 365 366 /* 367 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 368 * 1. Page1(0x100) 369 * */ 370 #define rPMAC_Reset 0x100 371 #define rPMAC_TxStart 0x104 372 #define rPMAC_TxLegacySIG 0x108 373 #define rPMAC_TxHTSIG1 0x10c 374 #define rPMAC_TxHTSIG2 0x110 375 #define rPMAC_PHYDebug 0x114 376 #define rPMAC_TxPacketNum 0x118 377 #define rPMAC_TxIdle 0x11c 378 #define rPMAC_TxMACHeader0 0x120 379 #define rPMAC_TxMACHeader1 0x124 380 #define rPMAC_TxMACHeader2 0x128 381 #define rPMAC_TxMACHeader3 0x12c 382 #define rPMAC_TxMACHeader4 0x130 383 #define rPMAC_TxMACHeader5 0x134 384 #define rPMAC_TxDataType 0x138 385 #define rPMAC_TxRandomSeed 0x13c 386 #define rPMAC_CCKPLCPPreamble 0x140 387 #define rPMAC_CCKPLCPHeader 0x144 388 #define rPMAC_CCKCRC16 0x148 389 #define rPMAC_OFDMRxCRC32OK 0x170 390 #define rPMAC_OFDMRxCRC32Er 0x174 391 #define rPMAC_OFDMRxParityEr 0x178 392 #define rPMAC_OFDMRxCRC8Er 0x17c 393 #define rPMAC_CCKCRxRC16Er 0x180 394 #define rPMAC_CCKCRxRC32Er 0x184 395 #define rPMAC_CCKCRxRC32OK 0x188 396 #define rPMAC_TxStatus 0x18c 397 398 /* 399 * 3. Page8(0x800) 400 * */ 401 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 402 403 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 404 #define rFPGA0_PSDFunction 0x808 405 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 406 407 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 408 #define rFPGA0_XA_HSSIParameter2 0x824 409 #define rFPGA0_XB_HSSIParameter1 0x828 410 #define rFPGA0_XB_HSSIParameter2 0x82c 411 412 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 413 #define rFPGA0_XCD_SwitchControl 0x85c 414 415 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 416 #define rFPGA0_XCD_RFParameter 0x87c 417 418 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 419 #define rFPGA0_AnalogParameter2 0x884 420 #define rFPGA0_AnalogParameter3 0x888 421 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 422 #define rFPGA0_AnalogParameter4 0x88c 423 #define rFPGA0_XB_LSSIReadBack 0x8a4 424 #define rFPGA0_XCD_RFPara 0x8b4 425 426 /* 427 * 4. Page9(0x900) 428 * */ 429 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 430 431 #define rFPGA1_TxBlock 0x904 /* Useless now */ 432 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 433 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 434 435 /* 436 * PageA(0xA00) 437 * */ 438 #define rCCK0_System 0xa00 439 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 440 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 441 #define rCCK0_TxFilter1 0xa20 442 #define rCCK0_TxFilter2 0xa24 443 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 444 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 445 446 /* 447 * PageB(0xB00) 448 * */ 449 #define rPdp_AntA 0xb00 450 #define rPdp_AntA_4 0xb04 451 #define rConfig_Pmpd_AntA 0xb28 452 #define rConfig_AntA 0xb68 453 #define rConfig_AntB 0xb6c 454 #define rPdp_AntB 0xb70 455 #define rPdp_AntB_4 0xb74 456 #define rConfig_Pmpd_AntB 0xb98 457 #define rAPK 0xbd8 458 459 /* 460 * 6. PageC(0xC00) 461 * */ 462 #define rOFDM0_LSTF 0xc00 463 464 #define rOFDM0_TRxPathEnable 0xc04 465 #define rOFDM0_TRMuxPar 0xc08 466 #define rOFDM0_TRSWIsolation 0xc0c 467 468 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 469 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 470 #define rOFDM0_XBRxAFE 0xc18 471 #define rOFDM0_XBRxIQImbalance 0xc1c 472 #define rOFDM0_XCRxAFE 0xc20 473 #define rOFDM0_XCRxIQImbalance 0xc24 474 #define rOFDM0_XDRxAFE 0xc28 475 #define rOFDM0_XDRxIQImbalance 0xc2c 476 477 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 478 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 479 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 480 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 481 482 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 483 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 484 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 485 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 486 487 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 488 #define rOFDM0_XAAGCCore2 0xc54 489 #define rOFDM0_XBAGCCore1 0xc58 490 #define rOFDM0_XBAGCCore2 0xc5c 491 #define rOFDM0_XCAGCCore1 0xc60 492 #define rOFDM0_XCAGCCore2 0xc64 493 #define rOFDM0_XDAGCCore1 0xc68 494 #define rOFDM0_XDAGCCore2 0xc6c 495 496 #define rOFDM0_AGCParameter1 0xc70 497 #define rOFDM0_AGCParameter2 0xc74 498 #define rOFDM0_AGCRSSITable 0xc78 499 #define rOFDM0_HTSTFAGC 0xc7c 500 501 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 502 #define rOFDM0_XATxAFE 0xc84 503 #define rOFDM0_XBTxIQImbalance 0xc88 504 #define rOFDM0_XBTxAFE 0xc8c 505 #define rOFDM0_XCTxIQImbalance 0xc90 506 #define rOFDM0_XCTxAFE 0xc94 507 #define rOFDM0_XDTxIQImbalance 0xc98 508 #define rOFDM0_XDTxAFE 0xc9c 509 510 #define rOFDM0_RxIQExtAnta 0xca0 511 #define rOFDM0_TxCoeff1 0xca4 512 #define rOFDM0_TxCoeff2 0xca8 513 #define rOFDM0_TxCoeff3 0xcac 514 #define rOFDM0_TxCoeff4 0xcb0 515 #define rOFDM0_TxCoeff5 0xcb4 516 #define rOFDM0_TxCoeff6 0xcb8 517 #define rOFDM0_RxHPParameter 0xce0 518 #define rOFDM0_TxPseudoNoiseWgt 0xce4 519 #define rOFDM0_FrameSync 0xcf0 520 #define rOFDM0_DFSReport 0xcf4 521 522 /* 523 * 7. PageD(0xD00) 524 * */ 525 #define rOFDM1_LSTF 0xd00 526 #define rOFDM1_TRxPathEnable 0xd04 527 528 /* 529 * 8. PageE(0xE00) 530 * */ 531 #define rTxAGC_A_Rate18_06 0xe00 532 #define rTxAGC_A_Rate54_24 0xe04 533 #define rTxAGC_A_CCK1_Mcs32 0xe08 534 #define rTxAGC_A_Mcs03_Mcs00 0xe10 535 #define rTxAGC_A_Mcs07_Mcs04 0xe14 536 #define rTxAGC_A_Mcs11_Mcs08 0xe18 537 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 538 539 #define rTxAGC_B_Rate18_06 0x830 540 #define rTxAGC_B_Rate54_24 0x834 541 #define rTxAGC_B_CCK1_55_Mcs32 0x838 542 #define rTxAGC_B_Mcs03_Mcs00 0x83c 543 #define rTxAGC_B_Mcs07_Mcs04 0x848 544 #define rTxAGC_B_Mcs11_Mcs08 0x84c 545 #define rTxAGC_B_Mcs15_Mcs12 0x868 546 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 547 548 #define rFPGA0_IQK 0xe28 549 #define rTx_IQK_Tone_A 0xe30 550 #define rRx_IQK_Tone_A 0xe34 551 #define rTx_IQK_PI_A 0xe38 552 #define rRx_IQK_PI_A 0xe3c 553 554 #define rTx_IQK 0xe40 555 #define rRx_IQK 0xe44 556 #define rIQK_AGC_Pts 0xe48 557 #define rIQK_AGC_Rsp 0xe4c 558 #define rTx_IQK_Tone_B 0xe50 559 #define rRx_IQK_Tone_B 0xe54 560 #define rTx_IQK_PI_B 0xe58 561 #define rRx_IQK_PI_B 0xe5c 562 #define rIQK_AGC_Cont 0xe60 563 564 #define rBlue_Tooth 0xe6c 565 #define rRx_Wait_CCA 0xe70 566 #define rTx_CCK_RFON 0xe74 567 #define rTx_CCK_BBON 0xe78 568 #define rTx_OFDM_RFON 0xe7c 569 #define rTx_OFDM_BBON 0xe80 570 #define rTx_To_Rx 0xe84 571 #define rTx_To_Tx 0xe88 572 #define rRx_CCK 0xe8c 573 574 #define rTx_Power_Before_IQK_A 0xe94 575 #define rTx_Power_After_IQK_A 0xe9c 576 577 #define rRx_Power_Before_IQK_A 0xea0 578 #define rRx_Power_Before_IQK_A_2 0xea4 579 #define rRx_Power_After_IQK_A 0xea8 580 #define rRx_Power_After_IQK_A_2 0xeac 581 582 #define rTx_Power_Before_IQK_B 0xeb4 583 #define rTx_Power_After_IQK_B 0xebc 584 585 #define rRx_Power_Before_IQK_B 0xec0 586 #define rRx_Power_Before_IQK_B_2 0xec4 587 #define rRx_Power_After_IQK_B 0xec8 588 #define rRx_Power_After_IQK_B_2 0xecc 589 590 #define rRx_OFDM 0xed0 591 #define rRx_Wait_RIFS 0xed4 592 #define rRx_TO_Rx 0xed8 593 #define rStandby 0xedc 594 #define rSleep 0xee0 595 #define rPMPD_ANAEN 0xeec 596 597 598 /* 2. Page8(0x800) */ 599 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 600 #define bJapanMode 0x2 601 #define bCCKTxSC 0x30 602 #define bCCKEn 0x1000000 603 #define bOFDMEn 0x2000000 604 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 605 #define bXCTxAGC 0xf000 606 #define bXDTxAGC 0xf0000 607 608 /* 4. PageA(0xA00) */ 609 #define bCCKBBMode 0x3 /* Useless */ 610 #define bCCKTxPowerSaving 0x80 611 #define bCCKRxPowerSaving 0x40 612 613 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 614 615 #define bCCKScramble 0x8 /* Useless */ 616 #define bCCKAntDiversity 0x8000 617 #define bCCKCarrierRecovery 0x4000 618 #define bCCKTxRate 0x3000 619 #define bCCKDCCancel 0x0800 620 #define bCCKISICancel 0x0400 621 #define bCCKMatchFilter 0x0200 622 #define bCCKEqualizer 0x0100 623 #define bCCKPreambleDetect 0x800000 624 #define bCCKFastFalseCCA 0x400000 625 #define bCCKChEstStart 0x300000 626 #define bCCKCCACount 0x080000 627 #define bCCKcs_lim 0x070000 628 #define bCCKBistMode 0x80000000 629 #define bCCKCCAMask 0x40000000 630 #define bCCKTxDACPhase 0x4 631 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 632 #define bCCKr_cp_mode0 0x0100 633 #define bCCKTxDCOffset 0xf0 634 #define bCCKRxDCOffset 0xf 635 #define bCCKCCAMode 0xc000 636 #define bCCKFalseCS_lim 0x3f00 637 #define bCCKCS_ratio 0xc00000 638 #define bCCKCorgBit_sel 0x300000 639 #define bCCKPD_lim 0x0f0000 640 #define bCCKNewCCA 0x80000000 641 #define bCCKRxHPofIG 0x8000 642 #define bCCKRxIG 0x7f00 643 #define bCCKLNAPolarity 0x800000 644 #define bCCKRx1stGain 0x7f0000 645 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 646 #define bCCKRxAGCSatLevel 0x1f000000 647 #define bCCKRxAGCSatCount 0xe0 648 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 649 #define bCCKFixedRxAGC 0x8000 650 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 651 #define bCCKAntennaPolarity 0x2000 652 #define bCCKTxFilterType 0x0c00 653 #define bCCKRxAGCReportType 0x0300 654 #define bCCKRxDAGCEn 0x80000000 655 #define bCCKRxDAGCPeriod 0x20000000 656 #define bCCKRxDAGCSatLevel 0x1f000000 657 #define bCCKTimingRecovery 0x800000 658 #define bCCKTxC0 0x3f0000 659 #define bCCKTxC1 0x3f000000 660 #define bCCKTxC2 0x3f 661 #define bCCKTxC3 0x3f00 662 #define bCCKTxC4 0x3f0000 663 #define bCCKTxC5 0x3f000000 664 #define bCCKTxC6 0x3f 665 #define bCCKTxC7 0x3f00 666 #define bCCKDebugPort 0xff0000 667 #define bCCKDACDebug 0x0f000000 668 #define bCCKFalseAlarmEnable 0x8000 669 #define bCCKFalseAlarmRead 0x4000 670 #define bCCKTRSSI 0x7f 671 #define bCCKRxAGCReport 0xfe 672 #define bCCKRxReport_AntSel 0x80000000 673 #define bCCKRxReport_MFOff 0x40000000 674 #define bCCKRxRxReport_SQLoss 0x20000000 675 #define bCCKRxReport_Pktloss 0x10000000 676 #define bCCKRxReport_Lockedbit 0x08000000 677 #define bCCKRxReport_RateError 0x04000000 678 #define bCCKRxReport_RxRate 0x03000000 679 #define bCCKRxFACounterLower 0xff 680 #define bCCKRxFACounterUpper 0xff000000 681 #define bCCKRxHPAGCStart 0xe000 682 #define bCCKRxHPAGCFinal 0x1c00 683 #define bCCKRxFalseAlarmEnable 0x8000 684 #define bCCKFACounterFreeze 0x4000 685 #define bCCKTxPathSel 0x10000000 686 #define bCCKDefaultRxPath 0xc000000 687 #define bCCKOptionRxPath 0x3000000 688 689 /* 6. PageE(0xE00) */ 690 #define bSTBCEn 0x4 /* Useless */ 691 #define bAntennaMapping 0x10 692 #define bNss 0x20 693 #define bCFOAntSumD 0x200 694 #define bPHYCounterReset 0x8000000 695 #define bCFOReportGet 0x4000000 696 #define bOFDMContinueTx 0x10000000 697 #define bOFDMSingleCarrier 0x20000000 698 #define bOFDMSingleTone 0x40000000 699 700 701 /* 702 * Other Definition 703 * */ 704 705 #define bEnable 0x1 /* Useless */ 706 #define bDisable 0x0 707 708 /* byte endable for srwrite */ 709 #define bByte0 0x1 /* Useless */ 710 #define bByte1 0x2 711 #define bByte2 0x4 712 #define bByte3 0x8 713 #define bWord0 0x3 714 #define bWord1 0xc 715 #define bDWord 0xf 716 717 /* for PutRegsetting & GetRegSetting BitMask */ 718 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 719 #define bMaskByte1 0xff00 720 #define bMaskByte2 0xff0000 721 #define bMaskByte3 0xff000000 722 #define bMaskHWord 0xffff0000 723 #define bMaskLWord 0x0000ffff 724 #define bMaskDWord 0xffffffff 725 #define bMaskH3Bytes 0xffffff00 726 #define bMask12Bits 0xfff 727 #define bMaskH4Bits 0xf0000000 728 #define bMaskOFDM_D 0xffc00000 729 #define bMaskCCK 0x3f3f3f3f 730 731 732 /*--------------------------Define Parameters-------------------------------*/ 733 734 735 #endif 736