1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __INC_HAL8814PHYREG_H__ 21 #define __INC_HAL8814PHYREG_H__ 22 /*--------------------------Define Parameters-------------------------------*/ 23 // 24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 25 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 27 // 3. RF register 0x00-2E 28 // 4. Bit Mask for BB/RF register 29 // 5. Other defintion for BB/RF R/W 30 // 31 32 33 /* BB Register Definition */ 34 35 #define rCCAonSec_Jaguar 0x838 36 #define rPwed_TH_Jaguar 0x830 37 #define rL1_Weight_Jaguar 0x840 38 39 // BW and sideband setting 40 #define rBWIndication_Jaguar 0x834 41 #define rL1PeakTH_Jaguar 0x848 42 #define rRFMOD_Jaguar 0x8ac //RF mode 43 #define rADC_Buf_Clk_Jaguar 0x8c4 44 #define rADC_Buf_40_Clk_Jaguar2 0x8c8 45 #define rRFECTRL_Jaguar 0x900 46 #define bRFMOD_Jaguar 0xc3 47 #define rCCK_System_Jaguar 0xa00 // for cck sideband 48 #define bCCK_System_Jaguar 0x10 49 50 // Block & Path enable 51 #define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable 52 #define bOFDMEN_Jaguar 0x20000000 53 #define bCCKEN_Jaguar 0x10000000 54 #define rRxPath_Jaguar 0x808 // Rx antenna 55 #define bRxPath_Jaguar 0xff 56 #define rTxPath_Jaguar 0x80c // Tx antenna 57 #define bTxPath_Jaguar 0x0fffffff 58 #define rCCK_RX_Jaguar 0xa04 // for cck rx path selection 59 #define bCCK_RX_Jaguar 0x0c000000 60 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length 61 62 #define rRxPath_Jaguar2 0xa04 // Rx antenna 63 #define rTxAnt_1Nsts_Jaguar2 0x93c // Tx antenna for 1Nsts 64 #define rTxAnt_23Nsts_Jaguar2 0x940 // Tx antenna for 2Nsts and 3Nsts 65 66 67 // RF read/write-related 68 #define rHSSIRead_Jaguar 0x8b0 // RF read addr 69 #define bHSSIRead_addr_Jaguar 0xff 70 #define bHSSIRead_trigger_Jaguar 0x100 71 #define rA_PIRead_Jaguar 0xd04 // RF readback with PI 72 #define rB_PIRead_Jaguar 0xd44 // RF readback with PI 73 #define rA_SIRead_Jaguar 0xd08 // RF readback with SI 74 #define rB_SIRead_Jaguar 0xd48 // RF readback with SI 75 #define rRead_data_Jaguar 0xfffff 76 #define rA_LSSIWrite_Jaguar 0xc90 // RF write addr 77 #define rB_LSSIWrite_Jaguar 0xe90 // RF write addr 78 #define bLSSIWrite_data_Jaguar 0x000fffff 79 #define bLSSIWrite_addr_Jaguar 0x0ff00000 80 81 #define rC_PIRead_Jaguar2 0xd84 // RF readback with PI 82 #define rD_PIRead_Jaguar2 0xdC4 // RF readback with PI 83 #define rC_SIRead_Jaguar2 0xd88 // RF readback with SI 84 #define rD_SIRead_Jaguar2 0xdC8 // RF readback with SI 85 #define rC_LSSIWrite_Jaguar2 0x1890 // RF write addr 86 #define rD_LSSIWrite_Jaguar2 0x1A90 // RF write addr 87 88 89 // YN: mask the following register definition temporarily 90 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch 91 #define rFPGA0_XB_RFInterfaceOE 0x864 92 93 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control 94 #define rFPGA0_XCD_RFInterfaceSW 0x874 95 96 //#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter 97 //#define rFPGA0_XCD_RFParameter 0x87c 98 99 //#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? 100 //#define rFPGA0_AnalogParameter2 0x884 101 //#define rFPGA0_AnalogParameter3 0x888 102 //#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy 103 //#define rFPGA0_AnalogParameter4 0x88c 104 105 106 // CCK TX scaling 107 #define rCCK_TxFilter1_Jaguar 0xa20 108 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 109 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 110 #define rCCK_TxFilter2_Jaguar 0xa24 111 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 112 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 113 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 114 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 115 #define rCCK_TxFilter3_Jaguar 0xa28 116 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 117 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 118 /* NBI & CSI Mask setting */ 119 #define rCSI_Mask_Setting1_Jaguar 0x874 120 #define rCSI_Fix_Mask0_Jaguar 0x880 121 #define rCSI_Fix_Mask1_Jaguar 0x884 122 #define rCSI_Fix_Mask2_Jaguar 0x888 123 #define rCSI_Fix_Mask3_Jaguar 0x88c 124 #define rCSI_Fix_Mask4_Jaguar 0x890 125 #define rCSI_Fix_Mask5_Jaguar 0x894 126 #define rCSI_Fix_Mask6_Jaguar 0x898 127 #define rCSI_Fix_Mask7_Jaguar 0x89c 128 #define rNBI_Setting_Jaguar 0x87c 129 130 131 // YN: mask the following register definition temporarily 132 //#define rPdp_AntA 0xb00 133 //#define rPdp_AntA_4 0xb04 134 //#define rConfig_Pmpd_AntA 0xb28 135 //#define rConfig_AntA 0xb68 136 //#define rConfig_AntB 0xb6c 137 //#define rPdp_AntB 0xb70 138 //#define rPdp_AntB_4 0xb74 139 //#define rConfig_Pmpd_AntB 0xb98 140 //#define rAPK 0xbd8 141 142 // RXIQC 143 #define rA_RxIQC_AB_Jaguar 0xc10 //RxIQ imblance matrix coeff. A & B 144 #define rA_RxIQC_CD_Jaguar 0xc14 //RxIQ imblance matrix coeff. C & D 145 #define rA_TxScale_Jaguar 0xc1c // Pah_A TX scaling factor 146 #define rB_TxScale_Jaguar 0xe1c // Path_B TX scaling factor 147 #define rB_RxIQC_AB_Jaguar 0xe10 //RxIQ imblance matrix coeff. A & B 148 #define rB_RxIQC_CD_Jaguar 0xe14 //RxIQ imblance matrix coeff. C & D 149 #define b_RxIQC_AC_Jaguar 0x02ff // bit mask for IQC matrix element A & C 150 #define b_RxIQC_BD_Jaguar 0x02ff0000 // bit mask for IQC matrix element A & C 151 152 #define rC_TxScale_Jaguar2 0x181c // Pah_C TX scaling factor 153 #define rD_TxScale_Jaguar2 0x1A1c // Path_D TX scaling factor 154 #define rRF_TxGainOffset 0x55 155 156 // DIG-related 157 #define rA_IGI_Jaguar 0xc50 // Initial Gain for path-A 158 #define rB_IGI_Jaguar 0xe50 // Initial Gain for path-B 159 #define rC_IGI_Jaguar2 0x1850 // Initial Gain for path-C 160 #define rD_IGI_Jaguar2 0x1A50 // Initial Gain for path-D 161 162 #define rOFDM_FalseAlarm1_Jaguar 0xf48 // counter for break 163 #define rOFDM_FalseAlarm2_Jaguar 0xf4c // counter for spoofing 164 #define rCCK_FalseAlarm_Jaguar 0xa5c // counter for cck false alarm 165 #define b_FalseAlarm_Jaguar 0xffff 166 #define rCCK_CCA_Jaguar 0xa08 // cca threshold 167 #define bCCK_CCA_Jaguar 0x00ff0000 168 169 // Tx Power Ttraining-related 170 #define rA_TxPwrTraing_Jaguar 0xc54 171 #define rB_TxPwrTraing_Jaguar 0xe54 172 173 // Report-related 174 #define rOFDM_ShortCFOAB_Jaguar 0xf60 175 #define rOFDM_LongCFOAB_Jaguar 0xf64 176 #define rOFDM_EndCFOAB_Jaguar 0xf70 177 #define rOFDM_AGCReport_Jaguar 0xf84 178 #define rOFDM_RxSNR_Jaguar 0xf88 179 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 180 #define rOFDM_SIGReport_Jaguar 0xf90 181 182 // Misc functions 183 #define rEDCCA_Jaguar 0x8a4 // EDCCA 184 #define bEDCCA_Jaguar 0xffff 185 #define rAGC_table_Jaguar 0x82c // AGC tabel select 186 #define bAGC_table_Jaguar 0x3 187 #define b_sel5g_Jaguar 0x1000 // sel5g 188 #define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA 189 #define rFc_area_Jaguar 0x860 // fc_area 190 #define bFc_area_Jaguar 0x1ffe000 191 #define rSingleTone_ContTx_Jaguar 0x914 192 193 #define rAGC_table_Jaguar2 0x958 // AGC tabel select 194 #define rDMA_trigger_Jaguar2 0x95C // ADC sample mode 195 196 197 // RFE 198 #define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux 199 #define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux 200 #define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol 201 #define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control 202 #define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol 203 #define rB_RFE_Jaguar 0xeb8 // Path_B RFE control 204 #define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control 205 #define bMask_RFEInv_Jaguar 0x3ff00000 206 #define bMask_AntselPathFollow_Jaguar 0x00030000 207 208 #define rC_RFE_Pinmux_Jaguar 0x18B4 // Path_C RFE cotrol pinmux 209 #define rD_RFE_Pinmux_Jaguar 0x1AB4 // Path_D RFE cotrol pinmux 210 #define rA_RFE_Sel_Jaguar2 0x1990 211 212 213 214 // TX AGC 215 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 216 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 217 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 218 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 219 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 220 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 221 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 222 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 223 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 224 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 225 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 226 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 227 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 228 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 229 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 230 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 231 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 232 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 233 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 234 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 235 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 236 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 237 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 238 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 239 #define bTxAGC_byte0_Jaguar 0xff 240 #define bTxAGC_byte1_Jaguar 0xff00 241 #define bTxAGC_byte2_Jaguar 0xff0000 242 #define bTxAGC_byte3_Jaguar 0xff000000 243 244 245 // TX AGC 246 #define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20 247 #define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24 248 #define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28 249 #define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c 250 #define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30 251 #define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34 252 #define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38 253 #define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8 254 #define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc 255 #define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c 256 #define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40 257 #define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44 258 #define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48 259 #define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c 260 #define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0 261 #define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4 262 #define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8 263 #define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20 264 #define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24 265 #define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28 266 #define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c 267 #define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30 268 #define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34 269 #define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38 270 #define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8 271 #define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc 272 #define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c 273 #define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40 274 #define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44 275 #define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48 276 #define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c 277 #define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0 278 #define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4 279 #define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8 280 #define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820 281 #define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824 282 #define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828 283 #define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c 284 #define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830 285 #define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834 286 #define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838 287 #define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8 288 #define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc 289 #define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c 290 #define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840 291 #define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844 292 #define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848 293 #define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c 294 #define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0 295 #define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4 296 #define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8 297 #define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20 298 #define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24 299 #define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28 300 #define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c 301 #define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30 302 #define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34 303 #define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38 304 #define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8 305 #define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc 306 #define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c 307 #define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40 308 #define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44 309 #define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48 310 #define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c 311 #define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0 312 #define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4 313 #define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8 314 // IQK YN: temporaily mask this part 315 //#define rFPGA0_IQK 0xe28 316 //#define rTx_IQK_Tone_A 0xe30 317 //#define rRx_IQK_Tone_A 0xe34 318 //#define rTx_IQK_PI_A 0xe38 319 //#define rRx_IQK_PI_A 0xe3c 320 321 //#define rTx_IQK 0xe40 322 //#define rRx_IQK 0xe44 323 //#define rIQK_AGC_Pts 0xe48 324 //#define rIQK_AGC_Rsp 0xe4c 325 //#define rTx_IQK_Tone_B 0xe50 326 //#define rRx_IQK_Tone_B 0xe54 327 //#define rTx_IQK_PI_B 0xe58 328 //#define rRx_IQK_PI_B 0xe5c 329 //#define rIQK_AGC_Cont 0xe60 330 331 332 // AFE-related 333 #define rA_AFEPwr1_Jaguar 0xc60 // dynamic AFE power control 334 #define rA_AFEPwr2_Jaguar 0xc64 // dynamic AFE power control 335 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 336 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 337 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 338 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 339 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 340 #define rA_Rx2Rx_BT_Jaguar 0xc7c 341 #define rA_sleep_nav_Jaguar 0xc80 342 #define rA_pmpd_Jaguar 0xc84 343 #define rB_AFEPwr1_Jaguar 0xe60 // dynamic AFE power control 344 #define rB_AFEPwr2_Jaguar 0xe64 // dynamic AFE power control 345 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 346 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 347 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 348 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 349 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 350 #define rB_Rx2Rx_BT_Jaguar 0xe7c 351 #define rB_sleep_nav_Jaguar 0xe80 352 #define rB_pmpd_Jaguar 0xe84 353 354 355 // YN: mask these registers temporaily 356 //#define rTx_Power_Before_IQK_A 0xe94 357 //#define rTx_Power_After_IQK_A 0xe9c 358 359 //#define rRx_Power_Before_IQK_A 0xea0 360 //#define rRx_Power_Before_IQK_A_2 0xea4 361 //#define rRx_Power_After_IQK_A 0xea8 362 //#define rRx_Power_After_IQK_A_2 0xeac 363 364 //#define rTx_Power_Before_IQK_B 0xeb4 365 //#define rTx_Power_After_IQK_B 0xebc 366 367 //#define rRx_Power_Before_IQK_B 0xec0 368 //#define rRx_Power_Before_IQK_B_2 0xec4 369 //#define rRx_Power_After_IQK_B 0xec8 370 //#define rRx_Power_After_IQK_B_2 0xecc 371 372 373 // RSSI Dump 374 #define rA_RSSIDump_Jaguar 0xBF0 375 #define rB_RSSIDump_Jaguar 0xBF1 376 #define rS1_RXevmDump_Jaguar 0xBF4 377 #define rS2_RXevmDump_Jaguar 0xBF5 378 #define rA_RXsnrDump_Jaguar 0xBF6 379 #define rB_RXsnrDump_Jaguar 0xBF7 380 #define rA_CfoShortDump_Jaguar 0xBF8 381 #define rB_CfoShortDump_Jaguar 0xBFA 382 #define rA_CfoLongDump_Jaguar 0xBEC 383 #define rB_CfoLongDump_Jaguar 0xBEE 384 385 386 // RF Register 387 // 388 #define RF_AC_Jaguar 0x00 // 389 #define RF_RF_Top_Jaguar 0x07 // 390 #define RF_TXLOK_Jaguar 0x08 // 391 #define RF_TXAPK_Jaguar 0x0B 392 #define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch 393 #define RF_RCK1_Jaguar 0x1c // 394 #define RF_RCK2_Jaguar 0x1d 395 #define RF_RCK3_Jaguar 0x1e 396 #define RF_ModeTableAddr 0x30 397 #define RF_ModeTableData0 0x31 398 #define RF_ModeTableData1 0x32 399 #define RF_TxLCTank_Jaguar 0x54 400 #define RF_APK_Jaguar 0x63 401 #define RF_LCK 0xB4 402 #define RF_WeLut_Jaguar 0xEF 403 404 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 405 #define bRF_CHNLBW_BW 0xc00 406 407 408 // 409 // RL6052 Register definition 410 // 411 #define RF_AC 0x00 // 412 #define RF_IPA_A 0x0C // 413 #define RF_TXBIAS_A 0x0D 414 #define RF_BS_PA_APSET_G9_G11 0x0E 415 #define RF_MODE1 0x10 // 416 #define RF_MODE2 0x11 // 417 #define RF_CHNLBW 0x18 // RF channel and BW switch 418 #define RF_RCK_OS 0x30 // RF TX PA control 419 #define RF_TXPA_G1 0x31 // RF TX PA control 420 #define RF_TXPA_G2 0x32 // RF TX PA control 421 #define RF_TXPA_G3 0x33 // RF TX PA control 422 #define RF_0x52 0x52 423 #define RF_WE_LUT 0xEF 424 425 // 426 //Bit Mask 427 // 428 // 1. Page1(0x100) 429 #define bBBResetB 0x100 // Useless now? 430 #define bGlobalResetB 0x200 431 #define bOFDMTxStart 0x4 432 #define bCCKTxStart 0x8 433 #define bCRC32Debug 0x100 434 #define bPMACLoopback 0x10 435 #define bTxLSIG 0xffffff 436 #define bOFDMTxRate 0xf 437 #define bOFDMTxReserved 0x10 438 #define bOFDMTxLength 0x1ffe0 439 #define bOFDMTxParity 0x20000 440 #define bTxHTSIG1 0xffffff 441 #define bTxHTMCSRate 0x7f 442 #define bTxHTBW 0x80 443 #define bTxHTLength 0xffff00 444 #define bTxHTSIG2 0xffffff 445 #define bTxHTSmoothing 0x1 446 #define bTxHTSounding 0x2 447 #define bTxHTReserved 0x4 448 #define bTxHTAggreation 0x8 449 #define bTxHTSTBC 0x30 450 #define bTxHTAdvanceCoding 0x40 451 #define bTxHTShortGI 0x80 452 #define bTxHTNumberHT_LTF 0x300 453 #define bTxHTCRC8 0x3fc00 454 #define bCounterReset 0x10000 455 #define bNumOfOFDMTx 0xffff 456 #define bNumOfCCKTx 0xffff0000 457 #define bTxIdleInterval 0xffff 458 #define bOFDMService 0xffff0000 459 #define bTxMACHeader 0xffffffff 460 #define bTxDataInit 0xff 461 #define bTxHTMode 0x100 462 #define bTxDataType 0x30000 463 #define bTxRandomSeed 0xffffffff 464 #define bCCKTxPreamble 0x1 465 #define bCCKTxSFD 0xffff0000 466 #define bCCKTxSIG 0xff 467 #define bCCKTxService 0xff00 468 #define bCCKLengthExt 0x8000 469 #define bCCKTxLength 0xffff0000 470 #define bCCKTxCRC16 0xffff 471 #define bCCKTxStatus 0x1 472 #define bOFDMTxStatus 0x2 473 474 475 // 476 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 477 // 1. Page1(0x100) 478 // 479 #define rPMAC_Reset 0x100 480 #define rPMAC_TxStart 0x104 481 #define rPMAC_TxLegacySIG 0x108 482 #define rPMAC_TxHTSIG1 0x10c 483 #define rPMAC_TxHTSIG2 0x110 484 #define rPMAC_PHYDebug 0x114 485 #define rPMAC_TxPacketNum 0x118 486 #define rPMAC_TxIdle 0x11c 487 #define rPMAC_TxMACHeader0 0x120 488 #define rPMAC_TxMACHeader1 0x124 489 #define rPMAC_TxMACHeader2 0x128 490 #define rPMAC_TxMACHeader3 0x12c 491 #define rPMAC_TxMACHeader4 0x130 492 #define rPMAC_TxMACHeader5 0x134 493 #define rPMAC_TxDataType 0x138 494 #define rPMAC_TxRandomSeed 0x13c 495 #define rPMAC_CCKPLCPPreamble 0x140 496 #define rPMAC_CCKPLCPHeader 0x144 497 #define rPMAC_CCKCRC16 0x148 498 #define rPMAC_OFDMRxCRC32OK 0x170 499 #define rPMAC_OFDMRxCRC32Er 0x174 500 #define rPMAC_OFDMRxParityEr 0x178 501 #define rPMAC_OFDMRxCRC8Er 0x17c 502 #define rPMAC_CCKCRxRC16Er 0x180 503 #define rPMAC_CCKCRxRC32Er 0x184 504 #define rPMAC_CCKCRxRC32OK 0x188 505 #define rPMAC_TxStatus 0x18c 506 507 // 508 // 3. Page8(0x800) 509 // 510 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? 511 512 #define rFPGA0_TxInfo 0x804 // Status report?? 513 #define rFPGA0_PSDFunction 0x808 514 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? 515 516 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register 517 #define rFPGA0_XA_HSSIParameter2 0x824 518 #define rFPGA0_XB_HSSIParameter1 0x828 519 #define rFPGA0_XB_HSSIParameter2 0x82c 520 521 #define rFPGA0_XA_LSSIParameter 0x840 522 #define rFPGA0_XB_LSSIParameter 0x844 523 524 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch 525 #define rFPGA0_XCD_SwitchControl 0x85c 526 527 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter 528 #define rFPGA0_XCD_RFParameter 0x87c 529 530 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? 531 #define rFPGA0_AnalogParameter2 0x884 532 #define rFPGA0_AnalogParameter3 0x888 533 #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy 534 #define rFPGA0_AnalogParameter4 0x88c 535 536 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback 537 #define rFPGA0_XB_LSSIReadBack 0x8a4 538 #define rFPGA0_XC_LSSIReadBack 0x8a8 539 #define rFPGA0_XD_LSSIReadBack 0x8ac 540 541 #define rFPGA0_XCD_RFPara 0x8b4 542 #define rFPGA0_PSDReport 0x8b4 // Useless now 543 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback 544 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback 545 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value 546 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now 547 548 // 549 // 4. Page9(0x900) 550 // 551 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? 552 553 #define rFPGA1_TxBlock 0x904 // Useless now 554 #define rFPGA1_DebugSelect 0x908 // Useless now 555 #define rFPGA1_TxInfo 0x90c // Useless now // Status report?? 556 557 // 558 // PageA(0xA00) 559 // 560 #define rCCK0_System 0xa00 561 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI 562 #define rCCK0_DSPParameter2 0xa1c //SQ threshold 563 #define rCCK0_TxFilter1 0xa20 564 #define rCCK0_TxFilter2 0xa24 565 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 566 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report 567 568 // 569 // PageB(0xB00) 570 // 571 #define rPdp_AntA 0xb00 572 #define rPdp_AntA_4 0xb04 573 #define rConfig_Pmpd_AntA 0xb28 574 #define rConfig_AntA 0xb68 575 #define rConfig_AntB 0xb6c 576 #define rPdp_AntB 0xb70 577 #define rPdp_AntB_4 0xb74 578 #define rConfig_Pmpd_AntB 0xb98 579 #define rAPK 0xbd8 580 581 // 582 // 6. PageC(0xC00) 583 // 584 #define rOFDM0_LSTF 0xc00 585 586 #define rOFDM0_TRxPathEnable 0xc04 587 #define rOFDM0_TRMuxPar 0xc08 588 #define rOFDM0_TRSWIsolation 0xc0c 589 590 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter 591 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix 592 #define rOFDM0_XBRxAFE 0xc18 593 #define rOFDM0_XBRxIQImbalance 0xc1c 594 #define rOFDM0_XCRxAFE 0xc20 595 #define rOFDM0_XCRxIQImbalance 0xc24 596 #define rOFDM0_XDRxAFE 0xc28 597 #define rOFDM0_XDRxIQImbalance 0xc2c 598 599 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain 600 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. 601 #define rOFDM0_RxDetector3 0xc38 //Frame Sync. 602 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI 603 604 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path 605 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC 606 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold 607 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA 608 609 #define rOFDM0_XAAGCCore1 0xc50 // DIG 610 #define rOFDM0_XAAGCCore2 0xc54 611 #define rOFDM0_XBAGCCore1 0xc58 612 #define rOFDM0_XBAGCCore2 0xc5c 613 #define rOFDM0_XCAGCCore1 0xc60 614 #define rOFDM0_XCAGCCore2 0xc64 615 #define rOFDM0_XDAGCCore1 0xc68 616 #define rOFDM0_XDAGCCore2 0xc6c 617 618 #define rOFDM0_AGCParameter1 0xc70 619 #define rOFDM0_AGCParameter2 0xc74 620 #define rOFDM0_AGCRSSITable 0xc78 621 #define rOFDM0_HTSTFAGC 0xc7c 622 623 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG 624 #define rOFDM0_XATxAFE 0xc84 625 #define rOFDM0_XBTxIQImbalance 0xc88 626 #define rOFDM0_XBTxAFE 0xc8c 627 #define rOFDM0_XCTxIQImbalance 0xc90 628 #define rOFDM0_XCTxAFE 0xc94 629 #define rOFDM0_XDTxIQImbalance 0xc98 630 #define rOFDM0_XDTxAFE 0xc9c 631 632 #define rOFDM0_RxIQExtAnta 0xca0 633 #define rOFDM0_TxCoeff1 0xca4 634 #define rOFDM0_TxCoeff2 0xca8 635 #define rOFDM0_TxCoeff3 0xcac 636 #define rOFDM0_TxCoeff4 0xcb0 637 #define rOFDM0_TxCoeff5 0xcb4 638 #define rOFDM0_TxCoeff6 0xcb8 639 #define rOFDM0_RxHPParameter 0xce0 640 #define rOFDM0_TxPseudoNoiseWgt 0xce4 641 #define rOFDM0_FrameSync 0xcf0 642 #define rOFDM0_DFSReport 0xcf4 643 644 // 645 // 7. PageD(0xD00) 646 // 647 #define rOFDM1_LSTF 0xd00 648 #define rOFDM1_TRxPathEnable 0xd04 649 650 // 651 // 8. PageE(0xE00) 652 // 653 #define rTxAGC_A_Rate18_06 0xe00 654 #define rTxAGC_A_Rate54_24 0xe04 655 #define rTxAGC_A_CCK1_Mcs32 0xe08 656 #define rTxAGC_A_Mcs03_Mcs00 0xe10 657 #define rTxAGC_A_Mcs07_Mcs04 0xe14 658 #define rTxAGC_A_Mcs11_Mcs08 0xe18 659 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 660 661 #define rTxAGC_B_Rate18_06 0x830 662 #define rTxAGC_B_Rate54_24 0x834 663 #define rTxAGC_B_CCK1_55_Mcs32 0x838 664 #define rTxAGC_B_Mcs03_Mcs00 0x83c 665 #define rTxAGC_B_Mcs07_Mcs04 0x848 666 #define rTxAGC_B_Mcs11_Mcs08 0x84c 667 #define rTxAGC_B_Mcs15_Mcs12 0x868 668 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 669 670 #define rFPGA0_IQK 0xe28 671 #define rTx_IQK_Tone_A 0xe30 672 #define rRx_IQK_Tone_A 0xe34 673 #define rTx_IQK_PI_A 0xe38 674 #define rRx_IQK_PI_A 0xe3c 675 676 #define rTx_IQK 0xe40 677 #define rRx_IQK 0xe44 678 #define rIQK_AGC_Pts 0xe48 679 #define rIQK_AGC_Rsp 0xe4c 680 #define rTx_IQK_Tone_B 0xe50 681 #define rRx_IQK_Tone_B 0xe54 682 #define rTx_IQK_PI_B 0xe58 683 #define rRx_IQK_PI_B 0xe5c 684 #define rIQK_AGC_Cont 0xe60 685 686 #define rBlue_Tooth 0xe6c 687 #define rRx_Wait_CCA 0xe70 688 #define rTx_CCK_RFON 0xe74 689 #define rTx_CCK_BBON 0xe78 690 #define rTx_OFDM_RFON 0xe7c 691 #define rTx_OFDM_BBON 0xe80 692 #define rTx_To_Rx 0xe84 693 #define rTx_To_Tx 0xe88 694 #define rRx_CCK 0xe8c 695 696 #define rTx_Power_Before_IQK_A 0xe94 697 #define rTx_Power_After_IQK_A 0xe9c 698 699 #define rRx_Power_Before_IQK_A 0xea0 700 #define rRx_Power_Before_IQK_A_2 0xea4 701 #define rRx_Power_After_IQK_A 0xea8 702 #define rRx_Power_After_IQK_A_2 0xeac 703 704 #define rTx_Power_Before_IQK_B 0xeb4 705 #define rTx_Power_After_IQK_B 0xebc 706 707 #define rRx_Power_Before_IQK_B 0xec0 708 #define rRx_Power_Before_IQK_B_2 0xec4 709 #define rRx_Power_After_IQK_B 0xec8 710 #define rRx_Power_After_IQK_B_2 0xecc 711 712 #define rRx_OFDM 0xed0 713 #define rRx_Wait_RIFS 0xed4 714 #define rRx_TO_Rx 0xed8 715 #define rStandby 0xedc 716 #define rSleep 0xee0 717 #define rPMPD_ANAEN 0xeec 718 719 720 // 2. Page8(0x800) 721 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD 722 #define bJapanMode 0x2 723 #define bCCKTxSC 0x30 724 #define bCCKEn 0x1000000 725 #define bOFDMEn 0x2000000 726 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage 727 #define bXCTxAGC 0xf000 728 #define bXDTxAGC 0xf0000 729 730 // 4. PageA(0xA00) 731 #define bCCKBBMode 0x3 // Useless 732 #define bCCKTxPowerSaving 0x80 733 #define bCCKRxPowerSaving 0x40 734 735 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch 736 737 #define bCCKScramble 0x8 // Useless 738 #define bCCKAntDiversity 0x8000 739 #define bCCKCarrierRecovery 0x4000 740 #define bCCKTxRate 0x3000 741 #define bCCKDCCancel 0x0800 742 #define bCCKISICancel 0x0400 743 #define bCCKMatchFilter 0x0200 744 #define bCCKEqualizer 0x0100 745 #define bCCKPreambleDetect 0x800000 746 #define bCCKFastFalseCCA 0x400000 747 #define bCCKChEstStart 0x300000 748 #define bCCKCCACount 0x080000 749 #define bCCKcs_lim 0x070000 750 #define bCCKBistMode 0x80000000 751 #define bCCKCCAMask 0x40000000 752 #define bCCKTxDACPhase 0x4 753 #define bCCKRxADCPhase 0x20000000 //r_rx_clk 754 #define bCCKr_cp_mode0 0x0100 755 #define bCCKTxDCOffset 0xf0 756 #define bCCKRxDCOffset 0xf 757 #define bCCKCCAMode 0xc000 758 #define bCCKFalseCS_lim 0x3f00 759 #define bCCKCS_ratio 0xc00000 760 #define bCCKCorgBit_sel 0x300000 761 #define bCCKPD_lim 0x0f0000 762 #define bCCKNewCCA 0x80000000 763 #define bCCKRxHPofIG 0x8000 764 #define bCCKRxIG 0x7f00 765 #define bCCKLNAPolarity 0x800000 766 #define bCCKRx1stGain 0x7f0000 767 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity 768 #define bCCKRxAGCSatLevel 0x1f000000 769 #define bCCKRxAGCSatCount 0xe0 770 #define bCCKRxRFSettle 0x1f //AGCsamp_dly 771 #define bCCKFixedRxAGC 0x8000 772 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 773 #define bCCKAntennaPolarity 0x2000 774 #define bCCKTxFilterType 0x0c00 775 #define bCCKRxAGCReportType 0x0300 776 #define bCCKRxDAGCEn 0x80000000 777 #define bCCKRxDAGCPeriod 0x20000000 778 #define bCCKRxDAGCSatLevel 0x1f000000 779 #define bCCKTimingRecovery 0x800000 780 #define bCCKTxC0 0x3f0000 781 #define bCCKTxC1 0x3f000000 782 #define bCCKTxC2 0x3f 783 #define bCCKTxC3 0x3f00 784 #define bCCKTxC4 0x3f0000 785 #define bCCKTxC5 0x3f000000 786 #define bCCKTxC6 0x3f 787 #define bCCKTxC7 0x3f00 788 #define bCCKDebugPort 0xff0000 789 #define bCCKDACDebug 0x0f000000 790 #define bCCKFalseAlarmEnable 0x8000 791 #define bCCKFalseAlarmRead 0x4000 792 #define bCCKTRSSI 0x7f 793 #define bCCKRxAGCReport 0xfe 794 #define bCCKRxReport_AntSel 0x80000000 795 #define bCCKRxReport_MFOff 0x40000000 796 #define bCCKRxRxReport_SQLoss 0x20000000 797 #define bCCKRxReport_Pktloss 0x10000000 798 #define bCCKRxReport_Lockedbit 0x08000000 799 #define bCCKRxReport_RateError 0x04000000 800 #define bCCKRxReport_RxRate 0x03000000 801 #define bCCKRxFACounterLower 0xff 802 #define bCCKRxFACounterUpper 0xff000000 803 #define bCCKRxHPAGCStart 0xe000 804 #define bCCKRxHPAGCFinal 0x1c00 805 #define bCCKRxFalseAlarmEnable 0x8000 806 #define bCCKFACounterFreeze 0x4000 807 #define bCCKTxPathSel 0x10000000 808 #define bCCKDefaultRxPath 0xc000000 809 #define bCCKOptionRxPath 0x3000000 810 811 #define RF_T_METER_88E 0x42 // 812 813 // 6. PageE(0xE00) 814 #define bSTBCEn 0x4 // Useless 815 #define bAntennaMapping 0x10 816 #define bNss 0x20 817 #define bCFOAntSumD 0x200 818 #define bPHYCounterReset 0x8000000 819 #define bCFOReportGet 0x4000000 820 #define bOFDMContinueTx 0x10000000 821 #define bOFDMSingleCarrier 0x20000000 822 #define bOFDMSingleTone 0x40000000 823 824 825 // 826 // Other Definition 827 // 828 829 #define bEnable 0x1 // Useless 830 #define bDisable 0x0 831 832 //byte endable for srwrite 833 #define bByte0 0x1 // Useless 834 #define bByte1 0x2 835 #define bByte2 0x4 836 #define bByte3 0x8 837 #define bWord0 0x3 838 #define bWord1 0xc 839 #define bDWord 0xf 840 841 //for PutRegsetting & GetRegSetting BitMask 842 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f 843 #define bMaskByte1 0xff00 844 #define bMaskByte2 0xff0000 845 #define bMaskByte3 0xff000000 846 #define bMaskHWord 0xffff0000 847 #define bMaskLWord 0x0000ffff 848 #define bMaskDWord 0xffffffff 849 #define bMaskH3Bytes 0xffffff00 850 #define bMask12Bits 0xfff 851 #define bMaskH4Bits 0xf0000000 852 #define bMaskOFDM_D 0xffc00000 853 #define bMaskCCK 0x3f3f3f3f 854 855 856 /*--------------------------Define Parameters-------------------------------*/ 857 858 859 #endif 860 861