Searched +full:0 +full:x70010000 (Results 1 – 9 of 9) sorted by relevance
36 #define CONFIG_SYS_FSL_ESDHC_ADDR 045 #define CONFIG_FEC_MXC_PHYADDR 0x1F51 #define CONFIG_MXC_USB_FLAGS 060 #define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */61 #define CONFIG_SYS_TEXT_BASE 0x7780000064 "fdt_addr_r=0x71ff0000\0" \65 "pxefile_addr_r=0x73000000\0" \66 "ramdisk_addr_r=0x72000000\0" \67 "console=ttymxc1,115200\0" \68 "uenv=/boot/uEnv.txt\0" \[all …]
48 #define CONFIG_SYS_FSL_ESDHC_ADDR 056 #define CONFIG_FEC_MXC_PHYADDR 0x1F66 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */67 #define CONFIG_SYS_TEXT_BASE 0x7780000070 "script=boot.scr\0" \71 "uimage=uImage\0" \72 "mmcdev=0\0" \73 "mmcpart=2\0" \74 "mmcroot=/dev/mmcblk0p3 rw\0" \75 "mmcrootfstype=ext3 rootwait\0" \[all …]
40 #define CONFIG_SYS_FSL_ESDHC_ADDR 049 #define CONFIG_FEC_MXC_PHYADDR 0x1F59 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */60 #define CONFIG_SYS_TEXT_BASE 0x7780000063 "script=boot.scr\0" \64 "uimage=uImage\0" \65 "mmcdev=0\0" \66 "mmcpart=2\0" \67 "mmcroot=/dev/mmcblk0p3 rw\0" \68 "mmcrootfstype=ext3 rootwait\0" \[all …]
34 #define CONFIG_SYS_FSL_ESDHC_ADDR 042 #define CONFIG_FEC_MXC_PHYADDR 0x1F48 #define CONFIG_MXC_USB_FLAGS 063 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x4864 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x876 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */77 #define CONFIG_SYS_TEXT_BASE 0x7780000080 "script=boot.scr\0" \81 "image=zImage\0" \82 "fdt_addr=0x71000000\0" \[all …]
48 #define CONFIG_SYS_FSL_ESDHC_ADDR 068 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */69 #define CONFIG_SYS_TEXT_BASE 0x7780000072 "script=boot.scr\0" \73 "uimage=zImage\0" \74 "console=ttymxc0\0" \75 "fdt_high=0xffffffff\0" \76 "initrd_high=0xffffffff\0" \77 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \78 "fdt_addr=0x78000000\0" \[all …]
10 #define CG6_FBC 0x7000000011 #define CG6_TEC 0x7000100012 #define CG6_BTREGS 0x7000200013 #define CG6_FHC 0x7000400014 #define CG6_THC 0x7000500015 #define CG6_ROM 0x7000600016 #define CG6_RAM 0x7001600017 #define CG6_DHC 0x8000000019 #define CG3_MMAP_OFFSET 0x400000022 #define TCX_RAM8BIT 0x00000000[all …]
72 Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).73 enum: [0, 1, 2]90 #size-cells = <0>;92 reg = <0x70010000 0x4000>;
13 #define FBTYPE_SUN1BW 0 /* mono */58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)61 int index; /* first element (0 origin) */124 #define FB_WID_SHARED_8 0196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */225 #define CG6_FBC 0x70000000226 #define CG6_TEC 0x70001000227 #define CG6_BTREGS 0x70002000228 #define CG6_FHC 0x70004000229 #define CG6_THC 0x70005000[all …]
46 reg = <0xe0000000 0x4000>;52 #clock-cells = <0>;58 #clock-cells = <0>;59 clock-frequency = <0>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;77 #size-cells = <0>;78 cpu: cpu@0 {81 reg = <0>;[all …]