1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Shawn Guo <shawnguo@kernel.org> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "/schemas/spi/spi-controller.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - const: fsl,imx1-cspi 19*4882a593Smuzhiyun - const: fsl,imx21-cspi 20*4882a593Smuzhiyun - const: fsl,imx27-cspi 21*4882a593Smuzhiyun - const: fsl,imx31-cspi 22*4882a593Smuzhiyun - const: fsl,imx35-cspi 23*4882a593Smuzhiyun - const: fsl,imx51-ecspi 24*4882a593Smuzhiyun - const: fsl,imx53-ecspi 25*4882a593Smuzhiyun - items: 26*4882a593Smuzhiyun - enum: 27*4882a593Smuzhiyun - fsl,imx50-ecspi 28*4882a593Smuzhiyun - fsl,imx6q-ecspi 29*4882a593Smuzhiyun - fsl,imx6sx-ecspi 30*4882a593Smuzhiyun - fsl,imx6sl-ecspi 31*4882a593Smuzhiyun - fsl,imx6sll-ecspi 32*4882a593Smuzhiyun - fsl,imx6ul-ecspi 33*4882a593Smuzhiyun - fsl,imx7d-ecspi 34*4882a593Smuzhiyun - fsl,imx8mq-ecspi 35*4882a593Smuzhiyun - fsl,imx8mm-ecspi 36*4882a593Smuzhiyun - fsl,imx8mn-ecspi 37*4882a593Smuzhiyun - fsl,imx8mp-ecspi 38*4882a593Smuzhiyun - const: fsl,imx51-ecspi 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun reg: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun interrupts: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clocks: 47*4882a593Smuzhiyun items: 48*4882a593Smuzhiyun - description: SoC SPI ipg clock 49*4882a593Smuzhiyun - description: SoC SPI per clock 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clock-names: 52*4882a593Smuzhiyun items: 53*4882a593Smuzhiyun - const: ipg 54*4882a593Smuzhiyun - const: per 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun dmas: 57*4882a593Smuzhiyun items: 58*4882a593Smuzhiyun - description: DMA controller phandle and request line for RX 59*4882a593Smuzhiyun - description: DMA controller phandle and request line for TX 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun dma-names: 62*4882a593Smuzhiyun items: 63*4882a593Smuzhiyun - const: rx 64*4882a593Smuzhiyun - const: tx 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun fsl,spi-rdy-drctl: 67*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 68*4882a593Smuzhiyun description: | 69*4882a593Smuzhiyun Integer, representing the value of DRCTL, the register controlling 70*4882a593Smuzhiyun the SPI_READY handling. Note that to enable the DRCTL consideration, 71*4882a593Smuzhiyun the SPI_READY mode-flag needs to be set too. 72*4882a593Smuzhiyun Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). 73*4882a593Smuzhiyun enum: [0, 1, 2] 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunrequired: 76*4882a593Smuzhiyun - compatible 77*4882a593Smuzhiyun - reg 78*4882a593Smuzhiyun - interrupts 79*4882a593Smuzhiyun - clocks 80*4882a593Smuzhiyun - clock-names 81*4882a593Smuzhiyun 82*4882a593SmuzhiyununevaluatedProperties: false 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunexamples: 85*4882a593Smuzhiyun - | 86*4882a593Smuzhiyun #include <dt-bindings/clock/imx5-clock.h> 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun spi@70010000 { 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun compatible = "fsl,imx51-ecspi"; 92*4882a593Smuzhiyun reg = <0x70010000 0x4000>; 93*4882a593Smuzhiyun interrupts = <36>; 94*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 95*4882a593Smuzhiyun <&clks IMX5_CLK_ECSPI1_PER_GATE>; 96*4882a593Smuzhiyun clock-names = "ipg", "per"; 97*4882a593Smuzhiyun }; 98