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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
77 "^pll[0|1]-refclk$":
88 const: 0
114 const: 0
134 const: 0
148 "^serdes@[0-9a-f]+$":
182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
186 ranges = <0x5000000 0x5000000 0x10000>;
190 #clock-cells = <0>;
196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Devb_ast2500.h15 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
16 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
21 #define CONFIG_SYS_LOAD_ADDR 0x83000000
23 #define CONFIG_ENV_SIZE 0x20000
H A Dsmdkv310.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000
26 #define CONFIG_SYS_TEXT_BASE 0x43E00000
29 #define S5P_CHECK_SLEEP 0x00000BAD
30 #define S5P_CHECK_DIDLE 0xBAD00000
31 #define S5P_CHECK_LPA 0xABAD0000
35 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
42 #define COPY_BL2_FNPTR_ADDR 0x00002488
44 #define CONFIG_SPL_TEXT_BASE 0x02021410
46 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
49 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
[all …]
H A Dexynos5-common.h23 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
30 #define S5P_CHECK_SLEEP 0x00000BAD
31 #define S5P_CHECK_DIDLE 0xBAD00000
32 #define S5P_CHECK_LPA 0xABAD0000
35 #define INFORM0_OFFSET 0x800
36 #define INFORM1_OFFSET 0x804
37 #define INFORM2_OFFSET 0x808
38 #define INFORM3_OFFSET 0x80c
41 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
47 #define COPY_BL2_FNPTR_ADDR 0x02020030
[all …]
H A Ds5pc210_universal.h22 #define CONFIG_SYS_SDRAM_BASE 0x40000000
33 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
40 #define CONFIG_SYS_MONITOR_BASE 0x00000000
44 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
45 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
60 ",-(UBI)\0"
68 ",-(UMS)\0"
89 "onenand erase 0x0 0x100000;" \
90 "onenand write 0x42008000 0x0 0x100000\0" \
92 "onenand erase 0xc00000 0x500000;" \
[all …]
H A Dtrats.h22 #define CONFIG_SYS_PL310_BASE 0x10502000
27 #define CONFIG_SYS_SDRAM_BASE 0x40000000
29 #define CONFIG_SYS_TEXT_BASE 0x63300000
34 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
37 #define CONFIG_SYS_TEXT_BASE 0x63300000
45 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
52 #define CONFIG_SYS_MONITOR_BASE 0x00000000
83 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
86 "u-boot raw 0x80 0x400;" \
[all …]
H A Ds5p_goni.h29 #define CONFIG_SYS_SDRAM_BASE 0x30000000
32 #define CONFIG_SYS_TEXT_BASE 0x34800000
63 #define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
64 #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
65 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
66 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
77 ",60m(qboot)\0"
89 "u-boot raw 0x80 0x400;" \
90 "uImage ext4 0 2;" \
91 "exynos3-goni.dtb ext4 0 2;" \
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dhisi504-nand.txt31 reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
32 interrupts = <0 379 4>;
40 partition@0 {
42 reg = <0x00000000 0x00400000>;
/OK3568_Linux_fs/buildroot/board/globalscale/espressobin/
H A Dreadme.txt14 |# 0 1 #|
66 > setenv kernel_addr 0x5000000
67 > setenv fdt_addr 0x1800000
69 > setenv console console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000
70 …> setenv bootcmd 'mmc dev 0; ext4load mmc 0:1 $kernel_addr $image_name;ext4load mmc 0:1 $fdt_addr …
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Dgpu.txt50 reg = <0xfdb00000 0x10000>;
63 iommus = <&gpu_iommu 0>;
69 reg = <0xfdd00000 0x2000>,
70 <0xfec00000 0x180000>;
82 gpu_sram: gpu-sram@0 {
83 reg = <0x0 0x100000>;
84 ranges = <0 0 0xfec00000 0x100000>;
98 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
108 iommus = <&adreno_smmu 0>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos5250-smdk5250.dts49 reg = <0x5000000 0x100>;
64 reg = <0x1a>;
71 reg = <0x9>;
106 samsung,vl-cmd-allow-len = <0xf>;
111 samsung,dual-lcd-enabled = <0>;
115 samsung,lt-status = <0>;
117 samsung,master-mode = <0>;
118 samsung,bist-mode = <0>;
119 samsung,bist-pattern = <0>;
120 samsung,h-sync-polarity = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
19 #clock-cells = <0>;
21 clock-frequency = <0>;
28 reg = <0x0 0x70000000 0x0 0x800000>;
31 ranges = <0x0 0x0 0x70000000 0x800000>;
33 atf-sram@0 {
34 reg = <0x0 0x20000>;
40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi26 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
41 reg = <0x1>;
42 clocks = <&clockgen 1 0>;
50 reg = <0x2>;
51 clocks = <&clockgen 1 0>;
59 reg = <0x3>;
60 clocks = <&clockgen 1 0>;
[all …]
H A Dfsl-ls208xa.dtsi32 #size-cells = <0>;
37 reg = <0x00000000 0x80000000 0 0x80000000>;
43 #clock-cells = <0>;
50 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
53 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
54 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
60 interrupts = <1 9 0x4>;
65 reg = <0x0 0x6020000 0 0x20000>;
[all …]
H A Dfsl-ls1028a.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
42 reg = <0x1>;
44 clocks = <&clockgen 1 0>;
65 arm,psci-suspend-param = <0x0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 reg = <0x0 0xf1f0000 0x0 0xffff>;
[all …]
H A Dfsl-lx2160a.dtsi11 /memreserve/ 0x80000000 0x00010000;
25 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
34 d-cache-size = <0x8000>;
37 i-cache-size = <0xC000>;
49 reg = <0x1>;
50 clocks = <&clockgen 1 0>;
51 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmBIF_MM_INDACCESS_CNTL 0x1500
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c57 #define smnPCIE_LC_SPEED_CNTL 0x11140290
58 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
62 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
64 …DF_CS_AON0_DramBaseAddress0 0x0044
65 …ne mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
68 …AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
69 …AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
70 …AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
71 …AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
72 …AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
[all …]