1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Samsung Electronics 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_H 10*4882a593Smuzhiyun #define __CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "exynos4-common.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #undef CONFIG_BOARD_COMMON 15*4882a593Smuzhiyun #undef CONFIG_USB_GADGET_DWC2_OTG_PHY 16*4882a593Smuzhiyun #undef CONFIG_REVISION_TAG 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* High Level Configuration Options */ 19*4882a593Smuzhiyun #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 20*4882a593Smuzhiyun #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Mach Type */ 23*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x40000000 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x43E00000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Handling Sleep Mode*/ 29*4882a593Smuzhiyun #define S5P_CHECK_SLEEP 0x00000BAD 30*4882a593Smuzhiyun #define S5P_CHECK_DIDLE 0xBAD00000 31*4882a593Smuzhiyun #define S5P_CHECK_LPA 0xABAD0000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* select serial console configuration */ 34*4882a593Smuzhiyun #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ 35*4882a593Smuzhiyun #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 38*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* MMC SPL */ 41*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 42*4882a593Smuzhiyun #define COPY_BL2_FNPTR_ADDR 0x00002488 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x02021410 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Miscellaneous configurable options */ 49*4882a593Smuzhiyun #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 50*4882a593Smuzhiyun /* memtest works on */ 51*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 52*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 53*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* SMDKV310 has 4 bank of DRAM */ 56*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 4 57*4882a593Smuzhiyun #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ 58*4882a593Smuzhiyun #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 59*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 60*4882a593Smuzhiyun #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 61*4882a593Smuzhiyun #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 62*4882a593Smuzhiyun #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 63*4882a593Smuzhiyun #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 64*4882a593Smuzhiyun #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 65*4882a593Smuzhiyun #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* FLASH and environment organization */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CONFIG_CLK_1000_400_200 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* MIU (Memory Interleaving Unit) */ 72*4882a593Smuzhiyun #define CONFIG_MIU_2BIT_INTERLEAVED 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 0 75*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 76*4882a593Smuzhiyun #define RESERVE_BLOCK_SIZE (512) 77*4882a593Smuzhiyun #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 78*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* U-Boot copy size from boot Media to DRAM.*/ 85*4882a593Smuzhiyun #define COPY_BL2_SIZE 0x80000 86*4882a593Smuzhiyun #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 87*4882a593Smuzhiyun #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Ethernet Controllor Driver */ 90*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET 91*4882a593Smuzhiyun #define CONFIG_SMC911X 92*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE 0x5000000 93*4882a593Smuzhiyun #define CONFIG_SMC911X_16_BIT 94*4882a593Smuzhiyun #define CONFIG_ENV_SROM_BANK 1 95*4882a593Smuzhiyun #endif /*CONFIG_CMD_NET*/ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __CONFIG_H */ 98