Lines Matching +full:0 +full:x5000000
32 #size-cells = <0>;
37 reg = <0x00000000 0x80000000 0 0x80000000>;
43 #clock-cells = <0>;
50 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
53 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
54 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
60 interrupts = <1 9 0x4>;
65 reg = <0x0 0x6020000 0 0x20000>;
71 reg = <0x0 0x1e60000 0x0 0x4>;
77 offset = <0x0>;
78 mask = <0x2>;
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
265 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
269 reg = <0 0x1300000 0 0xa0000>;
276 reg = <0x0 0x1e00000 0x0 0x10000>;
282 reg = <0x0 0x1f80000 0x0 0x10000>;
283 interrupts = <0 23 0x4>;
284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
285 fsl,tmu-calibration = <0x00000000 0x00000026
286 0x00000001 0x0000002d
287 0x00000002 0x00000032
288 0x00000003 0x00000039
289 0x00000004 0x0000003f
290 0x00000005 0x00000046
291 0x00000006 0x0000004d
292 0x00000007 0x00000054
293 0x00000008 0x0000005a
294 0x00000009 0x00000061
295 0x0000000a 0x0000006a
296 0x0000000b 0x00000071
298 0x00010000 0x00000025
299 0x00010001 0x0000002c
300 0x00010002 0x00000035
301 0x00010003 0x0000003d
302 0x00010004 0x00000045
303 0x00010005 0x0000004e
304 0x00010006 0x00000057
305 0x00010007 0x00000061
306 0x00010008 0x0000006b
307 0x00010009 0x00000076
309 0x00020000 0x00000029
310 0x00020001 0x00000033
311 0x00020002 0x0000003d
312 0x00020003 0x00000049
313 0x00020004 0x00000056
314 0x00020005 0x00000061
315 0x00020006 0x0000006d
317 0x00030000 0x00000021
318 0x00030001 0x0000002a
319 0x00030002 0x0000003c
320 0x00030003 0x0000004e>;
327 reg = <0x0 0x21c0500 0x0 0x100>;
329 interrupts = <0 32 0x4>; /* Level high type */
334 reg = <0x0 0x21c0600 0x0 0x100>;
336 interrupts = <0 32 0x4>; /* Level high type */
341 reg = <0x0 0x21d0500 0x0 0x100>;
343 interrupts = <0 33 0x4>; /* Level high type */
348 reg = <0x0 0x21d0600 0x0 0x100>;
350 interrupts = <0 33 0x4>; /* Level high type */
355 reg = <0x0 0xc000000 0x0 0x1000>;
362 reg = <0x0 0xc010000 0x0 0x1000>;
369 reg = <0x0 0xc100000 0x0 0x1000>;
376 reg = <0x0 0xc110000 0x0 0x1000>;
383 reg = <0x0 0xc200000 0x0 0x1000>;
390 reg = <0x0 0xc210000 0x0 0x1000>;
397 reg = <0x0 0xc300000 0x0 0x1000>;
404 reg = <0x0 0xc310000 0x0 0x1000>;
410 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
414 ranges = <0x0 0x00 0x8000000 0x100000>;
415 reg = <0x00 0x8000000 0x0 0x100000>;
420 compatible = "fsl,sec-v5.0-job-ring",
421 "fsl,sec-v4.0-job-ring";
422 reg = <0x10000 0x10000>;
427 compatible = "fsl,sec-v5.0-job-ring",
428 "fsl,sec-v4.0-job-ring";
429 reg = <0x20000 0x10000>;
434 compatible = "fsl,sec-v5.0-job-ring",
435 "fsl,sec-v4.0-job-ring";
436 reg = <0x30000 0x10000>;
441 compatible = "fsl,sec-v5.0-job-ring",
442 "fsl,sec-v4.0-job-ring";
443 reg = <0x40000 0x10000>;
450 reg = <0x00000000 0x08340020 0 0x2>;
455 reg = <0x0 0x8b95000 0x0 0x100>;
463 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
464 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
466 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
472 * Region type 0x0 - MC portals
473 * Region type 0x1 - QBMAN portals
475 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
476 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
483 #size-cells = <0>;
487 reg = <0x1>;
492 reg = <0x2>;
497 reg = <0x3>;
502 reg = <0x4>;
507 reg = <0x5>;
512 reg = <0x6>;
517 reg = <0x7>;
522 reg = <0x8>;
527 reg = <0x9>;
532 reg = <0xa>;
537 reg = <0xb>;
542 reg = <0xc>;
547 reg = <0xd>;
552 reg = <0xe>;
557 reg = <0xf>;
562 reg = <0x10>;
569 reg = <0 0x5000000 0 0x800000>;
572 stream-match-mask = <0x7C00>;
574 interrupts = <0 13 4>, /* global secure fault */
575 <0 14 4>, /* combined secure interrupt */
576 <0 15 4>, /* global non-secure fault */
577 <0 16 4>, /* combined non-secure interrupt */
578 /* performance counter interrupts 0-7 */
579 <0 211 4>, <0 212 4>,
580 <0 213 4>, <0 214 4>,
581 <0 215 4>, <0 216 4>,
582 <0 217 4>, <0 218 4>,
584 <0 146 4>, <0 147 4>,
585 <0 148 4>, <0 149 4>,
586 <0 150 4>, <0 151 4>,
587 <0 152 4>, <0 153 4>,
588 <0 154 4>, <0 155 4>,
589 <0 156 4>, <0 157 4>,
590 <0 158 4>, <0 159 4>,
591 <0 160 4>, <0 161 4>,
592 <0 162 4>, <0 163 4>,
593 <0 164 4>, <0 165 4>,
594 <0 166 4>, <0 167 4>,
595 <0 168 4>, <0 169 4>,
596 <0 170 4>, <0 171 4>,
597 <0 172 4>, <0 173 4>,
598 <0 174 4>, <0 175 4>,
599 <0 176 4>, <0 177 4>,
600 <0 178 4>, <0 179 4>,
601 <0 180 4>, <0 181 4>,
602 <0 182 4>, <0 183 4>,
603 <0 184 4>, <0 185 4>,
604 <0 186 4>, <0 187 4>,
605 <0 188 4>, <0 189 4>,
606 <0 190 4>, <0 191 4>,
607 <0 192 4>, <0 193 4>,
608 <0 194 4>, <0 195 4>,
609 <0 196 4>, <0 197 4>,
610 <0 198 4>, <0 199 4>,
611 <0 200 4>, <0 201 4>,
612 <0 202 4>, <0 203 4>,
613 <0 204 4>, <0 205 4>,
614 <0 206 4>, <0 207 4>,
615 <0 208 4>, <0 209 4>;
622 #size-cells = <0>;
623 reg = <0x0 0x2100000 0x0 0x10000>;
624 interrupts = <0 26 0x4>; /* Level high type */
633 reg = <0x0 0x2140000 0x0 0x10000>;
634 interrupts = <0 28 0x4>; /* Level high type */
644 reg = <0x0 0x2300000 0x0 0x10000>;
645 interrupts = <0 36 0x4>; /* Level high type */
655 reg = <0x0 0x2310000 0x0 0x10000>;
656 interrupts = <0 36 0x4>; /* Level high type */
666 reg = <0x0 0x2320000 0x0 0x10000>;
667 interrupts = <0 37 0x4>; /* Level high type */
677 reg = <0x0 0x2330000 0x0 0x10000>;
678 interrupts = <0 37 0x4>; /* Level high type */
690 #size-cells = <0>;
691 reg = <0x0 0x2000000 0x0 0x10000>;
692 interrupts = <0 34 0x4>; /* Level high type */
701 #size-cells = <0>;
702 reg = <0x0 0x2010000 0x0 0x10000>;
703 interrupts = <0 34 0x4>; /* Level high type */
712 #size-cells = <0>;
713 reg = <0x0 0x2020000 0x0 0x10000>;
714 interrupts = <0 35 0x4>; /* Level high type */
723 #size-cells = <0>;
724 reg = <0x0 0x2030000 0x0 0x10000>;
725 interrupts = <0 35 0x4>; /* Level high type */
732 reg = <0x0 0x2240000 0x0 0x20000>;
733 interrupts = <0 21 0x4>; /* Level high type */
738 ranges = <0 0 0x5 0x80000000 0x08000000
739 2 0 0x5 0x30000000 0x00010000
740 3 0 0x5 0x20000000 0x00010000>;
746 #size-cells = <0>;
747 reg = <0x0 0x20c0000 0x0 0x10000>,
748 <0x0 0x20000000 0x0 0x10000000>;
759 interrupts = <0 108 0x4>; /* Level high type */
766 bus-range = <0x0 0xff>;
769 interrupt-map-mask = <0 0 0 7>;
770 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
771 <0000 0 0 2 &gic 0 0 0 110 4>,
772 <0000 0 0 3 &gic 0 0 0 111 4>,
773 <0000 0 0 4 &gic 0 0 0 112 4>;
774 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
781 interrupts = <0 113 0x4>; /* Level high type */
788 bus-range = <0x0 0xff>;
791 interrupt-map-mask = <0 0 0 7>;
792 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
793 <0000 0 0 2 &gic 0 0 0 115 4>,
794 <0000 0 0 3 &gic 0 0 0 116 4>,
795 <0000 0 0 4 &gic 0 0 0 117 4>;
796 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
803 interrupts = <0 118 0x4>; /* Level high type */
810 bus-range = <0x0 0xff>;
813 interrupt-map-mask = <0 0 0 7>;
814 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
815 <0000 0 0 2 &gic 0 0 0 120 4>,
816 <0000 0 0 3 &gic 0 0 0 121 4>,
817 <0000 0 0 4 &gic 0 0 0 122 4>;
818 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
825 interrupts = <0 123 0x4>; /* Level high type */
832 bus-range = <0x0 0xff>;
835 interrupt-map-mask = <0 0 0 7>;
836 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
837 <0000 0 0 2 &gic 0 0 0 125 4>,
838 <0000 0 0 3 &gic 0 0 0 126 4>,
839 <0000 0 0 4 &gic 0 0 0 127 4>;
840 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
847 reg = <0x0 0x3200000 0x0 0x10000>;
848 interrupts = <0 133 0x4>; /* Level high type */
856 reg = <0x0 0x3210000 0x0 0x10000>;
857 interrupts = <0 136 0x4>; /* Level high type */
865 reg = <0x0 0x3100000 0x0 0x10000>;
866 interrupts = <0 80 0x4>; /* Level high type */
868 snps,quirk-frame-length-adjustment = <0x20>;
876 reg = <0x0 0x3110000 0x0 0x10000>;
877 interrupts = <0 81 0x4>; /* Level high type */
879 snps,quirk-frame-length-adjustment = <0x20>;
886 reg = <0x0 0x04000000 0x0 0x01000000>;
887 interrupts = <0 12 4>;
892 reg = <0x0 0x1e34040 0x0 0x18>;
899 reg = <0x0 0x2800000 0x0 0x10000>;
900 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
907 reg = <0x0 0x1080000 0x0 0x1000>;
908 interrupts = <0 17 0x4>;
914 reg = <0x0 0x1090000 0x0 0x1000>;
915 interrupts = <0 18 0x4>;