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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-385.dtsi20 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
45 bus-range = <0x00 0xff>;
48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
H A Darmada-xp-mv78230.dtsi26 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
33 clocks = <&cpuclk 0>;
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
[all …]
H A Darmada-380.dtsi20 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
46 bus-range = <0x00 0xff>;
49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-385.dtsi57 #size-cells = <0>;
60 cpu@0 {
63 reg = <0>;
88 bus-range = <0x00 0xff>;
91 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
92 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
93 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
94 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
95 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
96 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
H A Darmada-xp-mv78230.dtsi63 #size-cells = <0>;
66 cpu@0 {
69 reg = <0>;
70 clocks = <&cpuclk 0>;
85 * MV78230 has 2 PCIe units Gen2.0: One unit can be
98 bus-range = <0x00 0xff>;
101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
[all …]
H A Darmada-380.dtsi57 #size-cells = <0>;
60 cpu@0 {
63 reg = <0>;
83 bus-range = <0x00 0xff>;
86 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
87 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
88 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
89 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
90 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
H A Darmada-xp-mv78260.dtsi64 #size-cells = <0>;
67 cpu@0 {
70 reg = <0>;
71 clocks = <&cpuclk 0>;
86 * MV78260 has 3 PCIe units Gen2.0: Two units can be
99 bus-range = <0x00 0xff>;
102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi65 #size-cells = <0>;
68 cpu@0 {
71 reg = <0>;
72 clocks = <&cpuclk 0>;
103 * MV78460 has 4 PCIe units Gen2.0: Two units can be
116 bus-range = <0x00 0xff>;
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dbcmdevs_legacy.h28 #define BCM_DNGL_BL_PID_4322 0xbd13
29 #define BCM_DNGL_BL_PID_4319 0xbd16
30 #define BCM_DNGL_BL_PID_43236 0xbd17
31 #define BCM_DNGL_BL_PID_43143 0xbd1e
32 #define BCM_DNGL_BL_PID_43242 0xbd1f
33 #define BCM_DNGL_BL_PID_4350 0xbd23
34 #define BCM_DNGL_BL_PID_43569 0xbd27
37 #define BCM4335_D11AC_ID 0x43ae
38 #define BCM4335_D11AC2G_ID 0x43af
39 #define BCM4335_D11AC5G_ID 0x43b0
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Dbcmdevs_legacy.h28 #define BCM_DNGL_BL_PID_4322 0xbd13
29 #define BCM_DNGL_BL_PID_4319 0xbd16
30 #define BCM_DNGL_BL_PID_43236 0xbd17
31 #define BCM_DNGL_BL_PID_43143 0xbd1e
32 #define BCM_DNGL_BL_PID_43242 0xbd1f
33 #define BCM_DNGL_BL_PID_4350 0xbd23
34 #define BCM_DNGL_BL_PID_43569 0xbd27
37 #define BCM4335_D11AC_ID 0x43ae
38 #define BCM4335_D11AC2G_ID 0x43af
39 #define BCM4335_D11AC5G_ID 0x43b0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver
100 int ret = 0; in rockchip_combphy_pcie_init()
115 int ret = 0; in rockchip_combphy_usb3_init()
130 int ret = 0; in rockchip_combphy_sata_init()
145 int ret = 0; in rockchip_combphy_sgmii_init()
178 return 0; in rockchip_combphy_set_mode()
188 if (ret < 0 && ret != -ENOSYS) in rockchip_combphy_init()
200 return 0; in rockchip_combphy_init()
219 return 0; in rockchip_combphy_exit()
231 priv->mode = args->args[0]; in rockchip_combphy_xlate()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.h36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
39 #define VCN_DEC_KMD_CMD 0x80000000
40 #define VCN_DEC_CMD_FENCE 0x00000000
41 #define VCN_DEC_CMD_TRAP 0x00000001
42 #define VCN_DEC_CMD_WRITE_REG 0x00000004
43 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
44 #define VCN_DEC_CMD_PACKET_START 0x0000000a
45 #define VCN_DEC_CMD_PACKET_END 0x0000000b
47 #define VCN_ENC_CMD_NO_OP 0x00000000
48 #define VCN_ENC_CMD_END 0x00000001
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA combphy driver
136 int ret = 0; in rockchip_combphy_pcie_init()
148 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
150 writel(val, priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
159 int ret = 0; in rockchip_combphy_usb3_init()
184 int ret = 0; in rockchip_combphy_sata_init()
199 int ret = 0; in rockchip_combphy_sgmii_init()
232 return 0; in rockchip_combphy_set_mode()
268 return 0; in rockchip_combphy_init()
287 return 0; in rockchip_combphy_exit()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/meson/vdec/
H A Dcodec_hevc_common.c13 #define MMU_COMPRESS_HEADER_SIZE 0x48000
14 #define MMU_MAP_SIZE 0x4800
17 0x0401, 0x8401, 0x0800, 0x0402,
18 0x9002, 0x1423, 0x8CC3, 0x1423,
19 0x8804, 0x9825, 0x0800, 0x04FE,
20 0x8406, 0x8411, 0x1800, 0x8408,
21 0x8409, 0x8C2A, 0x9C2B, 0x1C00,
22 0x840F, 0x8407, 0x8000, 0x8408,
23 0x2000, 0xA800, 0x8410, 0x04DE,
24 0x840C, 0x840D, 0xAC00, 0xA000,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml228 reg = <0x98000000 0x800000>;
237 ti,bootreg = <&scm_conf 0x304 0>;
243 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
244 resets = <&prm_tesla 0>, <&prm_tesla 1>;
261 reg = <0 0x95800000 0 0x3800000>;
273 reg = <0x55020000 0x10000>;
280 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
298 reg = <0x0 0x99000000 0x0 0x4000000>;
310 reg = <0x40800000 0x48000>,
311 <0x40e00000 0x8000>,
[all …]

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