1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Include file for Marvell Armada 380 SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Lior Amsalem <alior@marvell.com> 8*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 9*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "armada-38x.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Marvell Armada 380 family SoC"; 16*4882a593Smuzhiyun compatible = "marvell,armada380"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cpus { 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <0>; 21*4882a593Smuzhiyun enable-method = "marvell,armada-380-smp"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpu@0 { 24*4882a593Smuzhiyun device_type = "cpu"; 25*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 26*4882a593Smuzhiyun reg = <0>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun soc { 31*4882a593Smuzhiyun internal-regs { 32*4882a593Smuzhiyun pinctrl@18000 { 33*4882a593Smuzhiyun compatible = "marvell,mv88f6810-pinctrl"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun pcie { 38*4882a593Smuzhiyun compatible = "marvell,armada-370-pcie"; 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun device_type = "pci"; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #address-cells = <3>; 43*4882a593Smuzhiyun #size-cells = <2>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun msi-parent = <&mpic>; 46*4882a593Smuzhiyun bus-range = <0x00 0xff>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ranges = 49*4882a593Smuzhiyun <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50*4882a593Smuzhiyun 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51*4882a593Smuzhiyun 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52*4882a593Smuzhiyun 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53*4882a593Smuzhiyun 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54*4882a593Smuzhiyun 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 55*4882a593Smuzhiyun 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 56*4882a593Smuzhiyun 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 57*4882a593Smuzhiyun 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 58*4882a593Smuzhiyun 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* x1 port */ 61*4882a593Smuzhiyun pcie@1,0 { 62*4882a593Smuzhiyun device_type = "pci"; 63*4882a593Smuzhiyun assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 64*4882a593Smuzhiyun reg = <0x0800 0 0 0 0>; 65*4882a593Smuzhiyun #address-cells = <3>; 66*4882a593Smuzhiyun #size-cells = <2>; 67*4882a593Smuzhiyun #interrupt-cells = <1>; 68*4882a593Smuzhiyun ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 69*4882a593Smuzhiyun 0x81000000 0 0 0x81000000 0x1 0 1 0>; 70*4882a593Smuzhiyun bus-range = <0x00 0xff>; 71*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 72*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 73*4882a593Smuzhiyun marvell,pcie-port = <0>; 74*4882a593Smuzhiyun marvell,pcie-lane = <0>; 75*4882a593Smuzhiyun clocks = <&gateclk 8>; 76*4882a593Smuzhiyun status = "disabled"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* x1 port */ 80*4882a593Smuzhiyun pcie@2,0 { 81*4882a593Smuzhiyun device_type = "pci"; 82*4882a593Smuzhiyun assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 83*4882a593Smuzhiyun reg = <0x1000 0 0 0 0>; 84*4882a593Smuzhiyun #address-cells = <3>; 85*4882a593Smuzhiyun #size-cells = <2>; 86*4882a593Smuzhiyun #interrupt-cells = <1>; 87*4882a593Smuzhiyun ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 88*4882a593Smuzhiyun 0x81000000 0 0 0x81000000 0x2 0 1 0>; 89*4882a593Smuzhiyun bus-range = <0x00 0xff>; 90*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 91*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 92*4882a593Smuzhiyun marvell,pcie-port = <1>; 93*4882a593Smuzhiyun marvell,pcie-lane = <0>; 94*4882a593Smuzhiyun clocks = <&gateclk 5>; 95*4882a593Smuzhiyun status = "disabled"; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* x1 port */ 99*4882a593Smuzhiyun pcie@3,0 { 100*4882a593Smuzhiyun device_type = "pci"; 101*4882a593Smuzhiyun assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 102*4882a593Smuzhiyun reg = <0x1800 0 0 0 0>; 103*4882a593Smuzhiyun #address-cells = <3>; 104*4882a593Smuzhiyun #size-cells = <2>; 105*4882a593Smuzhiyun #interrupt-cells = <1>; 106*4882a593Smuzhiyun ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 107*4882a593Smuzhiyun 0x81000000 0 0 0x81000000 0x3 0 1 0>; 108*4882a593Smuzhiyun bus-range = <0x00 0xff>; 109*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 110*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 111*4882a593Smuzhiyun marvell,pcie-port = <2>; 112*4882a593Smuzhiyun marvell,pcie-lane = <0>; 113*4882a593Smuzhiyun clocks = <&gateclk 6>; 114*4882a593Smuzhiyun status = "disabled"; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun}; 119