Lines Matching +full:0 +full:x48000
63 #size-cells = <0>;
66 cpu@0 {
69 reg = <0>;
70 clocks = <&cpuclk 0>;
85 * MV78230 has 2 PCIe units Gen2.0: One unit can be
98 bus-range = <0x00 0xff>;
101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
105 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
106 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
107 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
108 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
109 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
110 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
111 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
112 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
113 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
114 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
115 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
117 pcie@1,0 {
119 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
120 reg = <0x0800 0 0 0 0>;
124 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
125 0x81000000 0 0 0x81000000 0x1 0 1 0>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 58>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
134 pcie@2,0 {
136 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
137 reg = <0x1000 0 0 0 0>;
141 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
142 0x81000000 0 0 0x81000000 0x2 0 1 0>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 59>;
145 marvell,pcie-port = <0>;
151 pcie@3,0 {
153 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
154 reg = <0x1800 0 0 0 0>;
158 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
159 0x81000000 0 0 0x81000000 0x3 0 1 0>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 60>;
162 marvell,pcie-port = <0>;
168 pcie@4,0 {
170 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
171 reg = <0x2000 0 0 0 0>;
175 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
176 0x81000000 0 0 0x81000000 0x4 0 1 0>;
177 interrupt-map-mask = <0 0 0 0>;
178 interrupt-map = <0 0 0 0 &mpic 61>;
179 marvell,pcie-port = <0>;
185 pcie@5,0 {
187 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
188 reg = <0x2800 0 0 0 0>;
192 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
193 0x81000000 0 0 0x81000000 0x5 0 1 0>;
194 interrupt-map-mask = <0 0 0 0>;
195 interrupt-map = <0 0 0 0 &mpic 62>;
197 marvell,pcie-lane = <0>;
206 reg = <0x18100 0x40>;
217 reg = <0x18140 0x40>;