1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: OMAP4+ Remoteproc Devices 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Suman Anna <s-anna@ti.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The OMAP family of SoCs usually have one or more slave processor sub-systems 14*4882a593Smuzhiyun that are used to offload some of the processor-intensive tasks, or to manage 15*4882a593Smuzhiyun other hardware accelerators, for achieving various system level goals. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun The processor cores in the sub-system are usually behind an IOMMU, and may 18*4882a593Smuzhiyun contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 19*4882a593Smuzhiyun caches, an Interrupt Controller, a Cache Controller etc. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor 22*4882a593Smuzhiyun sub-system. The DSP processor sub-system can contain any of the TI's C64x, 23*4882a593Smuzhiyun C66x or C67x family of DSP cores as the main execution unit. The IPU processor 24*4882a593Smuzhiyun sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core 25*4882a593Smuzhiyun Cortex-M4 processors. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun Each remote processor sub-system is represented as a single DT node. Each node 28*4882a593Smuzhiyun has a number of required or optional properties that enable the OS running on 29*4882a593Smuzhiyun the host processor (MPU) to perform the device management of the remote 30*4882a593Smuzhiyun processor and to communicate with the remote processor. The various properties 31*4882a593Smuzhiyun can be classified as constant or variable. The constant properties are 32*4882a593Smuzhiyun dictated by the SoC and does not change from one board to another having the 33*4882a593Smuzhiyun same SoC. Examples of constant properties include 'iommus', 'reg'. The 34*4882a593Smuzhiyun variable properties are dictated by the system integration aspects such as 35*4882a593Smuzhiyun memory on the board, or configuration used within the corresponding firmware 36*4882a593Smuzhiyun image. Examples of variable properties include 'mboxes', 'memory-region', 37*4882a593Smuzhiyun 'timers', 'watchdog-timers' etc. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunproperties: 40*4882a593Smuzhiyun compatible: 41*4882a593Smuzhiyun enum: 42*4882a593Smuzhiyun - ti,omap4-dsp 43*4882a593Smuzhiyun - ti,omap5-dsp 44*4882a593Smuzhiyun - ti,dra7-dsp 45*4882a593Smuzhiyun - ti,omap4-ipu 46*4882a593Smuzhiyun - ti,omap5-ipu 47*4882a593Smuzhiyun - ti,dra7-ipu 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun iommus: 50*4882a593Smuzhiyun minItems: 1 51*4882a593Smuzhiyun maxItems: 2 52*4882a593Smuzhiyun description: | 53*4882a593Smuzhiyun phandles to OMAP IOMMU nodes, that need to be programmed 54*4882a593Smuzhiyun for this remote processor to access any external RAM memory or 55*4882a593Smuzhiyun other peripheral device address spaces. This property usually 56*4882a593Smuzhiyun has only a single phandle. Multiple phandles are used only in 57*4882a593Smuzhiyun cases where the sub-system has different ports for different 58*4882a593Smuzhiyun sub-modules within the processor sub-system (eg: DRA7 DSPs), 59*4882a593Smuzhiyun and need the same programming in both the MMUs. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun mboxes: 62*4882a593Smuzhiyun minItems: 1 63*4882a593Smuzhiyun maxItems: 2 64*4882a593Smuzhiyun description: | 65*4882a593Smuzhiyun OMAP Mailbox specifier denoting the sub-mailbox, to be used for 66*4882a593Smuzhiyun communication with the remote processor. The specifier format is 67*4882a593Smuzhiyun as per the bindings, 68*4882a593Smuzhiyun Documentation/devicetree/bindings/mailbox/omap-mailbox.txt 69*4882a593Smuzhiyun This property should match with the sub-mailbox node used in 70*4882a593Smuzhiyun the firmware image. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun clocks: 73*4882a593Smuzhiyun description: | 74*4882a593Smuzhiyun Main functional clock for the remote processor 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun resets: 77*4882a593Smuzhiyun description: | 78*4882a593Smuzhiyun Reset handles for the remote processor 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun firmware-name: 81*4882a593Smuzhiyun description: | 82*4882a593Smuzhiyun Default name of the firmware to load to the remote processor. 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun# Optional properties: 85*4882a593Smuzhiyun# -------------------- 86*4882a593Smuzhiyun# Some of these properties are mandatory on some SoCs, and some are optional 87*4882a593Smuzhiyun# depending on the configuration of the firmware image to be executed on the 88*4882a593Smuzhiyun# remote processor. The conditions are mentioned for each property. 89*4882a593Smuzhiyun# 90*4882a593Smuzhiyun# The following are the optional properties: 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun memory-region: 93*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 94*4882a593Smuzhiyun description: | 95*4882a593Smuzhiyun phandle to the reserved memory node to be associated 96*4882a593Smuzhiyun with the remoteproc device. The reserved memory node 97*4882a593Smuzhiyun can be a CMA memory node, and should be defined as 98*4882a593Smuzhiyun per the bindings, 99*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun reg: 102*4882a593Smuzhiyun description: | 103*4882a593Smuzhiyun Address space for any remoteproc memories present on 104*4882a593Smuzhiyun the SoC. Should contain an entry for each value in 105*4882a593Smuzhiyun 'reg-names'. These are mandatory for all DSP and IPU 106*4882a593Smuzhiyun processors that have them (OMAP4/OMAP5 DSPs do not have 107*4882a593Smuzhiyun any RAMs) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun reg-names: 110*4882a593Smuzhiyun description: | 111*4882a593Smuzhiyun Required names for each of the address spaces defined in 112*4882a593Smuzhiyun the 'reg' property. Expects the names from the following 113*4882a593Smuzhiyun list, in the specified order, each representing the corresponding 114*4882a593Smuzhiyun internal RAM memory region. 115*4882a593Smuzhiyun minItems: 1 116*4882a593Smuzhiyun maxItems: 3 117*4882a593Smuzhiyun items: 118*4882a593Smuzhiyun - const: l2ram 119*4882a593Smuzhiyun - const: l1pram 120*4882a593Smuzhiyun - const: l1dram 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun ti,bootreg: 123*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 124*4882a593Smuzhiyun description: | 125*4882a593Smuzhiyun Should be a triple of the phandle to the System Control 126*4882a593Smuzhiyun Configuration region that contains the boot address 127*4882a593Smuzhiyun register, the register offset of the boot address 128*4882a593Smuzhiyun register within the System Control module, and the bit 129*4882a593Smuzhiyun shift within the register. This property is required for 130*4882a593Smuzhiyun all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs. 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun ti,autosuspend-delay-ms: 133*4882a593Smuzhiyun description: | 134*4882a593Smuzhiyun Custom autosuspend delay for the remoteproc in milliseconds. 135*4882a593Smuzhiyun Recommended values is preferable to be in the order of couple 136*4882a593Smuzhiyun of seconds. A negative value can also be used to disable the 137*4882a593Smuzhiyun autosuspend behavior. 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun ti,timers: 140*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 141*4882a593Smuzhiyun description: | 142*4882a593Smuzhiyun One or more phandles to OMAP DMTimer nodes, that serve 143*4882a593Smuzhiyun as System/Tick timers for the OS running on the remote 144*4882a593Smuzhiyun processors. This will usually be a single timer if the 145*4882a593Smuzhiyun processor sub-system is running in SMP mode, or one per 146*4882a593Smuzhiyun core in the processor sub-system. This can also be used 147*4882a593Smuzhiyun to reserve specific timers to be dedicated to the 148*4882a593Smuzhiyun remote processors. 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun This property is mandatory on remote processors requiring 151*4882a593Smuzhiyun external tick wakeup, and to support Power Management 152*4882a593Smuzhiyun features. The timers to be used should match with the 153*4882a593Smuzhiyun timers used in the firmware image. 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun ti,watchdog-timers: 156*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 157*4882a593Smuzhiyun description: | 158*4882a593Smuzhiyun One or more phandles to OMAP DMTimer nodes, used to 159*4882a593Smuzhiyun serve as Watchdog timers for the processor cores. This 160*4882a593Smuzhiyun will usually be one per executing processor core, even 161*4882a593Smuzhiyun if the processor sub-system is running a SMP OS. 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun The timers to be used should match with the watchdog 164*4882a593Smuzhiyun timers used in the firmware image. 165*4882a593Smuzhiyun 166*4882a593Smuzhiyunif: 167*4882a593Smuzhiyun properties: 168*4882a593Smuzhiyun compatible: 169*4882a593Smuzhiyun enum: 170*4882a593Smuzhiyun - ti,dra7-dsp 171*4882a593Smuzhiyunthen: 172*4882a593Smuzhiyun properties: 173*4882a593Smuzhiyun reg: 174*4882a593Smuzhiyun minItems: 3 175*4882a593Smuzhiyun maxItems: 3 176*4882a593Smuzhiyun required: 177*4882a593Smuzhiyun - reg 178*4882a593Smuzhiyun - reg-names 179*4882a593Smuzhiyun - ti,bootreg 180*4882a593Smuzhiyun 181*4882a593Smuzhiyunelse: 182*4882a593Smuzhiyun if: 183*4882a593Smuzhiyun properties: 184*4882a593Smuzhiyun compatible: 185*4882a593Smuzhiyun enum: 186*4882a593Smuzhiyun - ti,omap4-ipu 187*4882a593Smuzhiyun - ti,omap5-ipu 188*4882a593Smuzhiyun - ti,dra7-ipu 189*4882a593Smuzhiyun then: 190*4882a593Smuzhiyun properties: 191*4882a593Smuzhiyun reg: 192*4882a593Smuzhiyun minItems: 1 193*4882a593Smuzhiyun maxItems: 1 194*4882a593Smuzhiyun ti,bootreg: false 195*4882a593Smuzhiyun required: 196*4882a593Smuzhiyun - reg 197*4882a593Smuzhiyun - reg-names 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun else: 200*4882a593Smuzhiyun properties: 201*4882a593Smuzhiyun reg: false 202*4882a593Smuzhiyun required: 203*4882a593Smuzhiyun - ti,bootreg 204*4882a593Smuzhiyun 205*4882a593Smuzhiyunrequired: 206*4882a593Smuzhiyun - compatible 207*4882a593Smuzhiyun - iommus 208*4882a593Smuzhiyun - mboxes 209*4882a593Smuzhiyun - clocks 210*4882a593Smuzhiyun - resets 211*4882a593Smuzhiyun - firmware-name 212*4882a593Smuzhiyun 213*4882a593SmuzhiyunadditionalProperties: false 214*4882a593Smuzhiyun 215*4882a593Smuzhiyunexamples: 216*4882a593Smuzhiyun - | 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun //Example 1: OMAP4 DSP 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* DSP Reserved Memory node */ 221*4882a593Smuzhiyun #include <dt-bindings/clock/omap4.h> 222*4882a593Smuzhiyun reserved-memory { 223*4882a593Smuzhiyun #address-cells = <1>; 224*4882a593Smuzhiyun #size-cells = <1>; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun dsp_memory_region: dsp-memory@98000000 { 227*4882a593Smuzhiyun compatible = "shared-dma-pool"; 228*4882a593Smuzhiyun reg = <0x98000000 0x800000>; 229*4882a593Smuzhiyun reusable; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* DSP node */ 234*4882a593Smuzhiyun ocp { 235*4882a593Smuzhiyun dsp: dsp { 236*4882a593Smuzhiyun compatible = "ti,omap4-dsp"; 237*4882a593Smuzhiyun ti,bootreg = <&scm_conf 0x304 0>; 238*4882a593Smuzhiyun iommus = <&mmu_dsp>; 239*4882a593Smuzhiyun mboxes = <&mailbox &mbox_dsp>; 240*4882a593Smuzhiyun memory-region = <&dsp_memory_region>; 241*4882a593Smuzhiyun ti,timers = <&timer5>; 242*4882a593Smuzhiyun ti,watchdog-timers = <&timer6>; 243*4882a593Smuzhiyun clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; 244*4882a593Smuzhiyun resets = <&prm_tesla 0>, <&prm_tesla 1>; 245*4882a593Smuzhiyun firmware-name = "omap4-dsp-fw.xe64T"; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun - |+ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun //Example 2: OMAP5 IPU 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* IPU Reserved Memory node */ 254*4882a593Smuzhiyun #include <dt-bindings/clock/omap5.h> 255*4882a593Smuzhiyun reserved-memory { 256*4882a593Smuzhiyun #address-cells = <2>; 257*4882a593Smuzhiyun #size-cells = <2>; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun ipu_memory_region: ipu-memory@95800000 { 260*4882a593Smuzhiyun compatible = "shared-dma-pool"; 261*4882a593Smuzhiyun reg = <0 0x95800000 0 0x3800000>; 262*4882a593Smuzhiyun reusable; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* IPU node */ 267*4882a593Smuzhiyun ocp { 268*4882a593Smuzhiyun #address-cells = <1>; 269*4882a593Smuzhiyun #size-cells = <1>; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun ipu: ipu@55020000 { 272*4882a593Smuzhiyun compatible = "ti,omap5-ipu"; 273*4882a593Smuzhiyun reg = <0x55020000 0x10000>; 274*4882a593Smuzhiyun reg-names = "l2ram"; 275*4882a593Smuzhiyun iommus = <&mmu_ipu>; 276*4882a593Smuzhiyun mboxes = <&mailbox &mbox_ipu>; 277*4882a593Smuzhiyun memory-region = <&ipu_memory_region>; 278*4882a593Smuzhiyun ti,timers = <&timer3>, <&timer4>; 279*4882a593Smuzhiyun ti,watchdog-timers = <&timer9>, <&timer11>; 280*4882a593Smuzhiyun clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; 281*4882a593Smuzhiyun resets = <&prm_core 2>; 282*4882a593Smuzhiyun firmware-name = "omap5-ipu-fw.xem4"; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun - |+ 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun //Example 3: DRA7xx/AM57xx DSP 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* DSP1 Reserved Memory node */ 291*4882a593Smuzhiyun #include <dt-bindings/clock/dra7.h> 292*4882a593Smuzhiyun reserved-memory { 293*4882a593Smuzhiyun #address-cells = <2>; 294*4882a593Smuzhiyun #size-cells = <2>; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun dsp1_memory_region: dsp1-memory@99000000 { 297*4882a593Smuzhiyun compatible = "shared-dma-pool"; 298*4882a593Smuzhiyun reg = <0x0 0x99000000 0x0 0x4000000>; 299*4882a593Smuzhiyun reusable; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun /* DSP1 node */ 304*4882a593Smuzhiyun ocp { 305*4882a593Smuzhiyun #address-cells = <1>; 306*4882a593Smuzhiyun #size-cells = <1>; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun dsp1: dsp@40800000 { 309*4882a593Smuzhiyun compatible = "ti,dra7-dsp"; 310*4882a593Smuzhiyun reg = <0x40800000 0x48000>, 311*4882a593Smuzhiyun <0x40e00000 0x8000>, 312*4882a593Smuzhiyun <0x40f00000 0x8000>; 313*4882a593Smuzhiyun reg-names = "l2ram", "l1pram", "l1dram"; 314*4882a593Smuzhiyun ti,bootreg = <&scm_conf 0x55c 0>; 315*4882a593Smuzhiyun iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 316*4882a593Smuzhiyun mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; 317*4882a593Smuzhiyun memory-region = <&dsp1_memory_region>; 318*4882a593Smuzhiyun ti,timers = <&timer5>; 319*4882a593Smuzhiyun ti,watchdog-timers = <&timer10>; 320*4882a593Smuzhiyun resets = <&prm_dsp1 0>; 321*4882a593Smuzhiyun clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 322*4882a593Smuzhiyun firmware-name = "dra7-dsp1-fw.xe66"; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun }; 325