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/OK3568_Linux_fs/u-boot/board/topic/zynq/zynq-topic-miamilite/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x202
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
/OK3568_Linux_fs/u-boot/board/topic/zynq/zynq-topic-miami/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x1210 // MIO configuration
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x210
10 0xf8000720 0x202
[all …]
/OK3568_Linux_fs/u-boot/board/topic/zynq/zynq-topic-miamiplus/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
2 0xf8000700 0x1202 // MIO configuration
3 0xf8000704 0x1202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/goya/
H A Dgoya_coresight.c20 #define SPMU_EVENT_TYPES_OFFSET 0x400
222 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
227 return 0; in goya_coresight_timeout()
245 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
253 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
254 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
255 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
256 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
257 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
258 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/gaudi/
H A Dgaudi_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
383 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in gaudi_coresight_timeout()
388 return 0; in gaudi_coresight_timeout()
406 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
414 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
415 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
416 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
417 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
418 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
419 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/host/
H A Dssb-hcd.c45 if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { in ssb_hcd_5354wa()
47 ssb_write32(dev, 0x894, 0x00fe00fe); in ssb_hcd_5354wa()
50 ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); in ssb_hcd_5354wa()
65 ssb_write32(dev, 0x200, 0x7ff); in ssb_hcd_usb20wa()
68 ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); in ssb_hcd_usb20wa()
69 ssb_read32(dev, 0x400); in ssb_hcd_usb20wa()
72 ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); in ssb_hcd_usb20wa()
73 ssb_read32(dev, 0x304); in ssb_hcd_usb20wa()
84 u32 flags = 0; in ssb_hcd_init_chip()
109 memset(hci_res, 0, sizeof(hci_res)); in ssb_hcd_create_pdev()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dvexpress-v2p-ca5s.dts16 arm,hbi = <0x225>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
55 reg = <0x80000000 0x40000000>;
63 /* Chipselect 2 is physically at 0x18000000 */
67 reg = <0x18000000 0x00800000>;
74 reg = <0x2a110000 0x1000>;
75 interrupts = <0 85 4>;
[all …]
H A Dqcom-msm8960.dtsi18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
21 cpu@0 {
25 reg = <0>;
49 reg = <0x0 0x0>;
54 interrupts = <1 10 0x304>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
91 reg = <0x02000000 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Daidmp.h35 #define MFGID_ARM 0x43b
36 #define MFGID_BRCM 0x4bf
37 #define MFGID_MIPS 0x4a7
40 #define CC_SIM 0
43 #define CC_VERIF 0xb
44 #define CC_OPTIMO 0xd
45 #define CC_GEN 0xe
46 #define CC_PRIMECELL 0xf
49 #define ER_EROMENTRY 0x000
50 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Daidmp.h28 #define MFGID_ARM 0x43b
29 #define MFGID_BRCM 0x4bf
30 #define MFGID_MIPS 0x4a7
33 #define CC_SIM 0
36 #define CC_VERIF 0xb
37 #define CC_OPTIMO 0xd
38 #define CC_GEN 0xe
39 #define CC_PRIMECELL 0xf
42 #define ER_EROMENTRY 0x000
43 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Daidmp.h28 #define MFGID_ARM 0x43b
29 #define MFGID_BRCM 0x4bf
30 #define MFGID_MIPS 0x4a7
33 #define CC_SIM 0
36 #define CC_VERIF 0xb
37 #define CC_OPTIMO 0xd
38 #define CC_GEN 0xe
39 #define CC_PRIMECELL 0xf
42 #define ER_EROMENTRY 0x000
43 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/
H A Dcoresight-tpiu.c22 #define TPIU_SUPP_PORTSZ 0x000
23 #define TPIU_CURR_PORTSZ 0x004
24 #define TPIU_SUPP_TRIGMODES 0x100
25 #define TPIU_TRIG_CNTRVAL 0x104
26 #define TPIU_TRIG_MULT 0x108
27 #define TPIU_SUPP_TESTPATM 0x200
28 #define TPIU_CURR_TESTPATM 0x204
29 #define TPIU_TEST_PATREPCNTR 0x208
30 #define TPIU_FFSR 0x300
31 #define TPIU_FFCR 0x304
[all …]
H A Dcoresight-tmc.h16 #define TMC_RSZ 0x004
17 #define TMC_STS 0x00c
18 #define TMC_RRD 0x010
19 #define TMC_RRP 0x014
20 #define TMC_RWP 0x018
21 #define TMC_TRG 0x01c
22 #define TMC_CTL 0x020
23 #define TMC_RWD 0x024
24 #define TMC_MODE 0x028
25 #define TMC_LBUFLEVEL 0x02c
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/r7780mp/
H A Dr7780mp.h14 #define FPGA_BASE 0xa4000000
15 #define FPGA_IRLMSK (FPGA_BASE + 0x00)
16 #define FPGA_IRLMON (FPGA_BASE + 0x02)
17 #define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
18 #define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
19 #define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
20 #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
21 #define FPGA_RSTCTL (FPGA_BASE + 0x0C)
22 #define FPGA_PCIBD (FPGA_BASE + 0x0E)
23 #define FPGA_PCICD (FPGA_BASE + 0x10)
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/ux500/
H A Dboards.txt51 reg = <0x80150000 0x2000>;
59 reg = <0xa0411000 0x1000>,
60 <0xa0410100 0x100>;
65 reg = <0xa0410000 0x100>;
70 reg = <0xa0410600 0x20>;
71 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
79 #clock-cells = <0>;
/OK3568_Linux_fs/kernel/drivers/clk/st/
H A Dclkgen-fsyn.c26 #define PLL_BW_GOODREF (0L)
78 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
79 CLKGEN_FIELD(0x2f0, 0x1, 1),
80 CLKGEN_FIELD(0x2f0, 0x1, 2),
81 CLKGEN_FIELD(0x2f0, 0x1, 3) },
82 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
83 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
84 CLKGEN_FIELD(0x2f0, 0x1, 9),
85 CLKGEN_FIELD(0x2f0, 0x1, 10),
86 CLKGEN_FIELD(0x2f0, 0x1, 11) },
[all …]
/OK3568_Linux_fs/kernel/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpsc_defs.h15 unsigned int pid; /* 0x000 */
16 unsigned char rsvd0[16]; /* 0x004 */
17 unsigned char rsvd1[4]; /* 0x014 */
18 unsigned int inteval; /* 0x018 */
19 unsigned char rsvd2[36]; /* 0x01C */
20 unsigned int merrpr0; /* 0x040 */
21 unsigned int merrpr1; /* 0x044 */
22 unsigned char rsvd3[8]; /* 0x048 */
23 unsigned int merrcr0; /* 0x050 */
24 unsigned int merrcr1; /* 0x054 */
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/netlogic/xlp-hal/
H A Dcpucontrol.h38 #define CPU_BLOCKID_IFU 0
49 #define IFU_BRUB_RESERVE 0x007
51 #define ICU_DEFEATURE 0x100
53 #define LSU_DEFEATURE 0x304
54 #define LSU_DEBUG_ADDR 0x305
55 #define LSU_DEBUG_DATA0 0x306
56 #define LSU_CERRLOG_REGID 0x309
57 #define SCHED_DEFEATURE 0x700
60 #define MAP_THREADMODE 0x00
61 #define MAP_EXT_EBASE_ENABLE 0x04
[all …]

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