1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 3*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _DV_PSC_DEFS_H_ 8*4882a593Smuzhiyun #define _DV_PSC_DEFS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Power/Sleep Ctrl Register structure 12*4882a593Smuzhiyun * See sprufb3.pdf, Chapter 7 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun struct dv_psc_regs { 15*4882a593Smuzhiyun unsigned int pid; /* 0x000 */ 16*4882a593Smuzhiyun unsigned char rsvd0[16]; /* 0x004 */ 17*4882a593Smuzhiyun unsigned char rsvd1[4]; /* 0x014 */ 18*4882a593Smuzhiyun unsigned int inteval; /* 0x018 */ 19*4882a593Smuzhiyun unsigned char rsvd2[36]; /* 0x01C */ 20*4882a593Smuzhiyun unsigned int merrpr0; /* 0x040 */ 21*4882a593Smuzhiyun unsigned int merrpr1; /* 0x044 */ 22*4882a593Smuzhiyun unsigned char rsvd3[8]; /* 0x048 */ 23*4882a593Smuzhiyun unsigned int merrcr0; /* 0x050 */ 24*4882a593Smuzhiyun unsigned int merrcr1; /* 0x054 */ 25*4882a593Smuzhiyun unsigned char rsvd4[8]; /* 0x058 */ 26*4882a593Smuzhiyun unsigned int perrpr; /* 0x060 */ 27*4882a593Smuzhiyun unsigned char rsvd5[4]; /* 0x064 */ 28*4882a593Smuzhiyun unsigned int perrcr; /* 0x068 */ 29*4882a593Smuzhiyun unsigned char rsvd6[4]; /* 0x06C */ 30*4882a593Smuzhiyun unsigned int epcpr; /* 0x070 */ 31*4882a593Smuzhiyun unsigned char rsvd7[4]; /* 0x074 */ 32*4882a593Smuzhiyun unsigned int epccr; /* 0x078 */ 33*4882a593Smuzhiyun unsigned char rsvd8[144]; /* 0x07C */ 34*4882a593Smuzhiyun unsigned char rsvd9[20]; /* 0x10C */ 35*4882a593Smuzhiyun unsigned int ptcmd; /* 0x120 */ 36*4882a593Smuzhiyun unsigned char rsvd10[4]; /* 0x124 */ 37*4882a593Smuzhiyun unsigned int ptstat; /* 0x128 */ 38*4882a593Smuzhiyun unsigned char rsvd11[212]; /* 0x12C */ 39*4882a593Smuzhiyun unsigned int pdstat0; /* 0x200 */ 40*4882a593Smuzhiyun unsigned int pdstat1; /* 0x204 */ 41*4882a593Smuzhiyun unsigned char rsvd12[248]; /* 0x208 */ 42*4882a593Smuzhiyun unsigned int pdctl0; /* 0x300 */ 43*4882a593Smuzhiyun unsigned int pdctl1; /* 0x304 */ 44*4882a593Smuzhiyun unsigned char rsvd13[536]; /* 0x308 */ 45*4882a593Smuzhiyun unsigned int mckout0; /* 0x520 */ 46*4882a593Smuzhiyun unsigned int mckout1; /* 0x524 */ 47*4882a593Smuzhiyun unsigned char rsvd14[728]; /* 0x528 */ 48*4882a593Smuzhiyun unsigned int mdstat[52]; /* 0x800 */ 49*4882a593Smuzhiyun unsigned char rsvd15[304]; /* 0x8D0 */ 50*4882a593Smuzhiyun unsigned int mdctl[52]; /* 0xA00 */ 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* PSC constants */ 54*4882a593Smuzhiyun #define EMURSTIE_MASK (0x00000200) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PD0 (0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PSC_ENABLE (0x3) 59*4882a593Smuzhiyun #define PSC_DISABLE (0x2) 60*4882a593Smuzhiyun #define PSC_SYNCRESET (0x1) 61*4882a593Smuzhiyun #define PSC_SWRSTDISABLE (0x0) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define PSC_GOSTAT (1 << 0) 64*4882a593Smuzhiyun #define PSC_MD_STATE_MSK (0x1f) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define PSC_CMD_GO (1 << 0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _DV_PSC_DEFS_H_ */ 71