1*4882a593Smuzhiyun0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) 2*4882a593Smuzhiyun0xf8000700 0x202 3*4882a593Smuzhiyun0xf8000704 0x202 4*4882a593Smuzhiyun0xf8000708 0x202 5*4882a593Smuzhiyun0xf800070c 0x202 6*4882a593Smuzhiyun0xf8000710 0x202 7*4882a593Smuzhiyun0xf8000714 0x202 8*4882a593Smuzhiyun0xf8000718 0x202 9*4882a593Smuzhiyun0xf800071c 0x200 10*4882a593Smuzhiyun0xf8000720 0x202 11*4882a593Smuzhiyun0xf8000724 0x202 12*4882a593Smuzhiyun0xf8000728 0x202 13*4882a593Smuzhiyun0xf800072c 0x202 14*4882a593Smuzhiyun0xf8000730 0x202 15*4882a593Smuzhiyun0xf8000734 0x202 16*4882a593Smuzhiyun0xf8000738 0x12e1 17*4882a593Smuzhiyun0xf800073c 0x12e0 18*4882a593Smuzhiyun0xf8000740 0x1200 19*4882a593Smuzhiyun0xf8000744 0x1200 20*4882a593Smuzhiyun0xf8000748 0x1200 21*4882a593Smuzhiyun0xf800074c 0x1200 22*4882a593Smuzhiyun0xf8000750 0x1200 23*4882a593Smuzhiyun0xf8000754 0x1200 24*4882a593Smuzhiyun0xf8000758 0x1200 25*4882a593Smuzhiyun0xf800075c 0x1200 26*4882a593Smuzhiyun0xf8000760 0x1200 27*4882a593Smuzhiyun0xf8000764 0x200 28*4882a593Smuzhiyun0xf8000768 0x1200 29*4882a593Smuzhiyun0xf800076c 0x200 30*4882a593Smuzhiyun0xf8000770 0x304 31*4882a593Smuzhiyun0xf8000774 0x305 32*4882a593Smuzhiyun0xf8000778 0x304 33*4882a593Smuzhiyun0xf800077c 0x305 34*4882a593Smuzhiyun0xf8000780 0x304 35*4882a593Smuzhiyun0xf8000784 0x304 36*4882a593Smuzhiyun0xf8000788 0x304 37*4882a593Smuzhiyun0xf800078c 0x304 38*4882a593Smuzhiyun0xf8000790 0x305 39*4882a593Smuzhiyun0xf8000794 0x304 40*4882a593Smuzhiyun0xf8000798 0x304 41*4882a593Smuzhiyun0xf800079c 0x304 42*4882a593Smuzhiyun0xf80007a0 0x380 43*4882a593Smuzhiyun0xf80007a4 0x380 44*4882a593Smuzhiyun0xf80007a8 0x380 45*4882a593Smuzhiyun0xf80007ac 0x380 46*4882a593Smuzhiyun0xf80007b0 0x380 47*4882a593Smuzhiyun0xf80007b4 0x380 48*4882a593Smuzhiyun0xf80007b8 0x1200 49*4882a593Smuzhiyun0xf80007bc 0x1200 50*4882a593Smuzhiyun0xf80007c0 0x1240 51*4882a593Smuzhiyun0xf80007c4 0x1240 52*4882a593Smuzhiyun0xf80007c8 0x1240 53*4882a593Smuzhiyun0xf80007cc 0x1240 54*4882a593Smuzhiyun0xf80007d0 0x1200 55*4882a593Smuzhiyun0xf80007d4 0x1200 56*4882a593Smuzhiyun0xf8000830 0x380037 57*4882a593Smuzhiyun0xf8000834 0x3a0039 58*4882a593Smuzhiyun0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) 59*4882a593Smuzhiyun0xE000D000 0x800238C1 // QSPI config - divide-by-2 60*4882a593Smuzhiyun0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay 61*4882a593Smuzhiyun0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash 62