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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddiu.txt20 reg = <0x2c000 100>;
28 reg = <0x2100 0x100>;
29 interrupts = <64 0x8>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dtango-nand.txt11 - #size-cells: <0>
20 reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
25 #size-cells = <0>;
27 nand@0 {
28 reg = <0>; /* CS0 */
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/slimbus/
H A Dslim-ngd-qcom-ctrl.txt46 Definition: Should be 0
69 reg = <0x91c0000 0x2c000>;
70 interrupts = <0 163 0>;
74 #size-cells = <0>;
81 reg = <1 0>;
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dqcom,ipa.yaml174 iommus = <&apps_smmu 0x720 0x3>;
175 reg = <0x1e40000 0x7000>,
176 <0x1e47000 0x2000>,
177 <0x1e04000 0x2c000>;
182 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
183 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
184 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
202 qcom,smem-states = <&ipa_smp2p_out 0>,
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
H A Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/soundwire/
H A Dintel_init.c23 #define SDW_SHIM_LCAP 0x0
24 #define SDW_SHIM_BASE 0x2C000
25 #define SDW_ALH_BASE 0x2C800
26 #define SDW_LINK_BASE 0x30000
27 #define SDW_LINK_SIZE 0x10000
37 u32 quirk_mask = 0; in is_link_enabled()
64 return 0; in sdw_intel_cleanup()
68 for (i = 0; i < ctx->count; i++, link++) { in sdw_intel_cleanup()
81 return 0; in sdw_intel_cleanup()
95 count = 0; in sdw_intel_scan_controller()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/lima/
H A Dlima_device.c51 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
52 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
53 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
55 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
56 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
57 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
58 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
59 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
60 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h31 #define MALI_OFFSET_GP 0x00000
32 #define MALI_OFFSET_GP_MMU 0x03000
34 #define MALI_OFFSET_PP0 0x08000
35 #define MALI_OFFSET_PP0_MMU 0x04000
36 #define MALI_OFFSET_PP1 0x0A000
37 #define MALI_OFFSET_PP1_MMU 0x05000
38 #define MALI_OFFSET_PP2 0x0C000
39 #define MALI_OFFSET_PP2_MMU 0x06000
40 #define MALI_OFFSET_PP3 0x0E000
41 #define MALI_OFFSET_PP3_MMU 0x07000
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DMPC8610HPCD.h15 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
17 #define CONFIG_SYS_TEXT_BASE 0xfff00000
23 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
29 #define CONFIG_SYS_DIAG_ADDR 0xff800000
36 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
56 #define L2_INIT 0
57 #define L2_ENABLE (L2CR_L2E |0x00100000 )
60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
66 #define CONFIG_SYS_MEMTEST_END 0x00400000
[all …]
/OK3568_Linux_fs/kernel/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
21 #define MT_HIF_BASE 0x4000
24 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_kernel_core.c47 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)
54 #define MALI_SHARED_MEMORY_DEFAULT_SIZE 0xffffffff
57 unsigned int mali_dedicated_mem_start = 0;
58 unsigned int mali_dedicated_mem_size = 0;
64 int mali_fb_start = 0;
65 int mali_fb_size = 0;
71 int mali_boot_profiling = 0;
74 int mali_max_pp_cores_group_1 = 0xFF;
75 int mali_max_pp_cores_group_2 = 0xFF;
77 int mali_inited_pp_cores_group_1 = 0;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
42 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
66 reg = <0x0 0x100>;
80 reg = <0x0 0x101>;
112 CPU_SLEEP_0: cpu-sleep-0 {
115 arm,psci-suspend-param = <0x00000004>;
[all …]
H A Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-msm8998.c39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
H A Dgcc-msm8996.c50 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
106 { P_XO, 0 },
120 { P_XO, 0 },
134 { P_XO, 0 },
152 { P_XO, 0 },
183 .offset = 0x00000,
[all …]
/OK3568_Linux_fs/kernel/tools/perf/util/
H A Dmachine.c62 for (i = 0; i < THREADS__TABLE_SIZE; i++) { in machine__threads_init()
66 threads->nr = 0; in machine__threads_init()
79 machine->pid) < 0) in machine__set_mmap_name()
82 return machine->mmap_name ? 0 : -ENOMEM; in machine__set_mmap_name()
89 memset(machine, 0, sizeof(*machine)); in machine__init()
101 machine->id_hdr_size = 0; in machine__init()
104 machine->kernel_start = 0; in machine__init()
123 thread__set_comm(thread, comm, 0); in machine__init()
128 err = 0; in machine__init()
135 return 0; in machine__init()
[all …]

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