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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drenesas,ceu.yaml78 reg = <0xe8210000 0x209c>;
88 vsync-active = <0>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dcoregv100.c28 .mthd = 0x0000,
29 .addr = 0x000000,
31 { 0x0200, 0x680200 },
32 { 0x0208, 0x680208 },
33 { 0x020c, 0x68020c },
34 { 0x0210, 0x680210 },
35 { 0x0214, 0x680214 },
36 { 0x0218, 0x680218 },
37 { 0x021c, 0x68021c },
44 .mthd = 0x0020,
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/s5p-mfc/
H A Dregs-mfc.h20 #define S5P_FIMV_START_ADDR 0x0000
21 #define S5P_FIMV_END_ADDR 0xe008
23 #define S5P_FIMV_SW_RESET 0x0000
24 #define S5P_FIMV_RISC_HOST_INT 0x0008
27 #define S5P_FIMV_HOST2RISC_CMD 0x0030
28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034
29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038
30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c
31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040
34 #define S5P_FIMV_RISC2HOST_CMD 0x0044
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dhi556.c7 * V0.0X01.0X00 init version
38 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
49 #define CHIP_ID 0x0556
50 #define HI556_REG_CHIP_ID 0x0f16
52 #define HI556_REG_CTRL_MODE 0x0A00
53 #define HI556_MODE_SW_STANDBY 0x00
54 #define HI556_MODE_STREAMING 0x01
56 #define HI556_REG_EXPOSURE_H 0x0073
57 #define HI556_REG_EXPOSURE_M 0x0074
58 #define HI556_REG_EXPOSURE_L 0x0075
[all …]
/OK3568_Linux_fs/kernel/fs/exfat/
H A Dnls.c16 #define UTBL_COUNT (0x10000)
24 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
25 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
26 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
27 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
28 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
29 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
30 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
31 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
32 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dmvpp2.c52 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 } while (0)
63 #define smp_processor_id() 0
66 for ((cpu) = 0; (cpu) < 1; (cpu)++)
81 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
82 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
83 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
84 #define MVPP2_RX_FIFO_INIT_REG 0x64
87 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
88 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/OK3568_Linux_fs/kernel/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_reg.h106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
121 * @__n: 0-based bit number
130 ((__n) < 0 || (__n) > 31))))
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
31 // base address: 0x4980
32 …SDMA0_DEC_START 0x0000
33 …ne mmSDMA0_DEC_START_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …ne mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
H A Ddcn_3_0_0_offset.h7 // base address: 0x0
8 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
9 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
10 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
11 …VGA_MEM_READ_PAGE_ADDR 0x0001
12 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
13 …VGA_RENDER_CONTROL 0x0000
15 …VGA_SEQUENCER_RESET_CONTROL 0x0001
17 …VGA_MODE_CONTROL 0x0002
19 …VGA_SURFACE_PITCH_SELECT 0x0003
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_init.c106 ql_dbg(ql_dbg_async, sp->vha, 0x507c, in qla24xx_abort_iocb_timeout()
111 ql_dbg(ql_dbg_async, sp->vha, 0x507c, in qla24xx_abort_iocb_timeout()
177 ql_dbg(ql_dbg_async, vha, 0x507c, in qla24xx_async_abort_cmd()
207 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, in qla2x00_async_iocb_timeout()
222 lio->u.logio.data[0] = MBS_COMMAND_ERROR; in qla2x00_async_iocb_timeout()
225 QLA_LOGIO_LOGIN_RETRIED : 0; in qla2x00_async_iocb_timeout()
273 ql_dbg(ql_dbg_disc, vha, 0x20dd, in qla2x00_async_login_sp_done()
279 memset(&ea, 0, sizeof(ea)); in qla2x00_async_login_sp_done()
281 ea.data[0] = lio->u.logio.data[0]; in qla2x00_async_login_sp_done()
283 ea.iop[0] = lio->u.logio.iop[0]; in qla2x00_async_login_sp_done()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h27 // base address: 0x48
28 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
29 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
33 // base address: 0x4c
34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
35 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
39 // base address: 0x0
40 …DC_PERFMON0_PERFCOUNTER_CNTL 0x0020
42 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
44 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/vendor/nunicode/src/libnu/gen/
H A D_ducet.c6 * Combined length : 0,
22 -19864, -19863, -19862, -19861, -19860, 0, -19859, -19858, -19857, -19856, -19855, -19854,
51 -19532, -19531, -19530, -19529, 0, -19528, 15, 17, 22, 16, 24, 50,
79 -19397, -19396, 0, 0, 0, -19395, 69, 71, 69, 76, 79, 90,
81 12, 9, 9, 16, 9, 16, -19389, -19388, 16, -19387, 0, 0,
89 -19318, -19317, -19316, -19315, -19314, -19313, -19312, -19311, -19310, 0, 0, 0,
90 0, -19309, 1, 1, -19308, 1, 2, 21, 5, 32, 20, 26,
91 32, 32, 32, 36, 32, -19307, 0, 0, 0, 0, -19306, -19305,
92 0, 0, -19304, -19303, -19302, -19301, -19300, -19299, -19298, -19297, -19296, -19295,
93 -19294, -19293, 0, 0, 0, -19292, 0, 0, 0, 0, 0, 0,
[all …]