1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_VOP_REG_H 8 #define _ROCKCHIP_VOP_REG_H 9 10 /* rk3288 register definition */ 11 #define RK3288_REG_CFG_DONE 0x0000 12 #define RK3288_VERSION_INFO 0x0004 13 #define RK3288_SYS_CTRL 0x0008 14 #define RK3288_SYS_CTRL1 0x000c 15 #define RK3288_DSP_CTRL0 0x0010 16 #define RK3288_DSP_CTRL1 0x0014 17 #define RK3288_DSP_BG 0x0018 18 #define RK3288_MCU_CTRL 0x001c 19 #define RK3288_INTR_CTRL0 0x0020 20 #define RK3288_INTR_CTRL1 0x0024 21 #define RK3288_WIN0_CTRL0 0x0030 22 #define RK3288_WIN0_CTRL1 0x0034 23 #define RK3288_WIN0_COLOR_KEY 0x0038 24 #define RK3288_WIN0_VIR 0x003c 25 #define RK3288_WIN0_YRGB_MST 0x0040 26 #define RK3288_WIN0_CBR_MST 0x0044 27 #define RK3288_WIN0_ACT_INFO 0x0048 28 #define RK3288_WIN0_DSP_INFO 0x004c 29 #define RK3288_WIN0_DSP_ST 0x0050 30 #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 31 #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 32 #define RK3288_WIN0_SCL_OFFSET 0x005c 33 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 34 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 35 #define RK3288_WIN0_FADING_CTRL 0x0068 36 #define RK3288_WIN0_CTRL2 0x006c 37 38 /* win1 register */ 39 #define RK3288_WIN1_CTRL0 0x0070 40 #define RK3288_WIN1_CTRL1 0x0074 41 #define RK3288_WIN1_COLOR_KEY 0x0078 42 #define RK3288_WIN1_VIR 0x007c 43 #define RK3288_WIN1_YRGB_MST 0x0080 44 #define RK3288_WIN1_CBR_MST 0x0084 45 #define RK3288_WIN1_ACT_INFO 0x0088 46 #define RK3288_WIN1_DSP_INFO 0x008c 47 #define RK3288_WIN1_DSP_ST 0x0090 48 #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 49 #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 50 #define RK3288_WIN1_SCL_OFFSET 0x009c 51 #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 52 #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 53 #define RK3288_WIN1_FADING_CTRL 0x00a8 54 /* win2 register */ 55 #define RK3288_WIN2_CTRL0 0x00b0 56 #define RK3288_WIN2_CTRL1 0x00b4 57 #define RK3288_WIN2_VIR0_1 0x00b8 58 #define RK3288_WIN2_VIR2_3 0x00bc 59 #define RK3288_WIN2_MST0 0x00c0 60 #define RK3288_WIN2_DSP_INFO0 0x00c4 61 #define RK3288_WIN2_DSP_ST0 0x00c8 62 #define RK3288_WIN2_COLOR_KEY 0x00cc 63 #define RK3288_WIN2_MST1 0x00d0 64 #define RK3288_WIN2_DSP_INFO1 0x00d4 65 #define RK3288_WIN2_DSP_ST1 0x00d8 66 #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc 67 #define RK3288_WIN2_MST2 0x00e0 68 #define RK3288_WIN2_DSP_INFO2 0x00e4 69 #define RK3288_WIN2_DSP_ST2 0x00e8 70 #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec 71 #define RK3288_WIN2_MST3 0x00f0 72 #define RK3288_WIN2_DSP_INFO3 0x00f4 73 #define RK3288_WIN2_DSP_ST3 0x00f8 74 #define RK3288_WIN2_FADING_CTRL 0x00fc 75 /* win3 register */ 76 #define RK3288_WIN3_CTRL0 0x0100 77 #define RK3288_WIN3_CTRL1 0x0104 78 #define RK3288_WIN3_VIR0_1 0x0108 79 #define RK3288_WIN3_VIR2_3 0x010c 80 #define RK3288_WIN3_MST0 0x0110 81 #define RK3288_WIN3_DSP_INFO0 0x0114 82 #define RK3288_WIN3_DSP_ST0 0x0118 83 #define RK3288_WIN3_COLOR_KEY 0x011c 84 #define RK3288_WIN3_MST1 0x0120 85 #define RK3288_WIN3_DSP_INFO1 0x0124 86 #define RK3288_WIN3_DSP_ST1 0x0128 87 #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c 88 #define RK3288_WIN3_MST2 0x0130 89 #define RK3288_WIN3_DSP_INFO2 0x0134 90 #define RK3288_WIN3_DSP_ST2 0x0138 91 #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c 92 #define RK3288_WIN3_MST3 0x0140 93 #define RK3288_WIN3_DSP_INFO3 0x0144 94 #define RK3288_WIN3_DSP_ST3 0x0148 95 #define RK3288_WIN3_FADING_CTRL 0x014c 96 /* hwc register */ 97 #define RK3288_HWC_CTRL0 0x0150 98 #define RK3288_HWC_CTRL1 0x0154 99 #define RK3288_HWC_MST 0x0158 100 #define RK3288_HWC_DSP_ST 0x015c 101 #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 102 #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 103 #define RK3288_HWC_FADING_CTRL 0x0168 104 /* post process register */ 105 #define RK3288_POST_DSP_HACT_INFO 0x0170 106 #define RK3288_POST_DSP_VACT_INFO 0x0174 107 #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 108 #define RK3288_POST_SCL_CTRL 0x0180 109 #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 110 #define RK3288_DSP_HTOTAL_HS_END 0x0188 111 #define RK3288_DSP_HACT_ST_END 0x018c 112 #define RK3288_DSP_VTOTAL_VS_END 0x0190 113 #define RK3288_DSP_VACT_ST_END 0x0194 114 #define RK3288_DSP_VS_ST_END_F1 0x0198 115 #define RK3288_DSP_VACT_ST_END_F1 0x019c 116 117 #define RK3288_BCSH_COLOR_BAR 0x01b0 118 #define RK3288_BCSH_BCS 0x01b4 119 #define RK3288_BCSH_H 0x01b8 120 #define RK3288_GRF_SOC_CON15 0x03a4 121 /* register definition end */ 122 123 /* rk3368 register definition */ 124 #define RK3368_REG_CFG_DONE 0x0000 125 #define RK3368_VERSION_INFO 0x0004 126 #define RK3368_SYS_CTRL 0x0008 127 #define RK3368_SYS_CTRL1 0x000c 128 #define RK3368_DSP_CTRL0 0x0010 129 #define RK3368_DSP_CTRL1 0x0014 130 #define RK3368_DSP_BG 0x0018 131 #define RK3368_MCU_CTRL 0x001c 132 #define RK3368_LINE_FLAG 0x0020 133 #define RK3368_INTR_EN 0x0024 134 #define RK3368_INTR_CLEAR 0x0028 135 #define RK3368_INTR_STATUS 0x002c 136 #define RK3368_WIN0_CTRL0 0x0030 137 #define RK3368_WIN0_CTRL1 0x0034 138 #define RK3368_WIN0_COLOR_KEY 0x0038 139 #define RK3368_WIN0_VIR 0x003c 140 #define RK3368_WIN0_YRGB_MST 0x0040 141 #define RK3368_WIN0_CBR_MST 0x0044 142 #define RK3368_WIN0_ACT_INFO 0x0048 143 #define RK3368_WIN0_DSP_INFO 0x004c 144 #define RK3368_WIN0_DSP_ST 0x0050 145 #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 146 #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 147 #define RK3368_WIN0_SCL_OFFSET 0x005c 148 #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 149 #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 150 #define RK3368_WIN0_FADING_CTRL 0x0068 151 #define RK3368_WIN0_CTRL2 0x006c 152 #define RK3368_WIN1_CTRL0 0x0070 153 #define RK3368_WIN1_CTRL1 0x0074 154 #define RK3368_WIN1_COLOR_KEY 0x0078 155 #define RK3368_WIN1_VIR 0x007c 156 #define RK3368_WIN1_YRGB_MST 0x0080 157 #define RK3368_WIN1_CBR_MST 0x0084 158 #define RK3368_WIN1_ACT_INFO 0x0088 159 #define RK3368_WIN1_DSP_INFO 0x008c 160 #define RK3368_WIN1_DSP_ST 0x0090 161 #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 162 #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 163 #define RK3368_WIN1_SCL_OFFSET 0x009c 164 #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 165 #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 166 #define RK3368_WIN1_FADING_CTRL 0x00a8 167 #define RK3368_WIN1_CTRL2 0x00ac 168 #define RK3368_WIN2_CTRL0 0x00b0 169 #define RK3368_WIN2_CTRL1 0x00b4 170 #define RK3368_WIN2_VIR0_1 0x00b8 171 #define RK3368_WIN2_VIR2_3 0x00bc 172 #define RK3368_WIN2_MST0 0x00c0 173 #define RK3368_WIN2_DSP_INFO0 0x00c4 174 #define RK3368_WIN2_DSP_ST0 0x00c8 175 #define RK3368_WIN2_COLOR_KEY 0x00cc 176 #define RK3368_WIN2_MST1 0x00d0 177 #define RK3368_WIN2_DSP_INFO1 0x00d4 178 #define RK3368_WIN2_DSP_ST1 0x00d8 179 #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 180 #define RK3368_WIN2_MST2 0x00e0 181 #define RK3368_WIN2_DSP_INFO2 0x00e4 182 #define RK3368_WIN2_DSP_ST2 0x00e8 183 #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 184 #define RK3368_WIN2_MST3 0x00f0 185 #define RK3368_WIN2_DSP_INFO3 0x00f4 186 #define RK3368_WIN2_DSP_ST3 0x00f8 187 #define RK3368_WIN2_FADING_CTRL 0x00fc 188 #define RK3368_WIN3_CTRL0 0x0100 189 #define RK3368_WIN3_CTRL1 0x0104 190 #define RK3368_WIN3_VIR0_1 0x0108 191 #define RK3368_WIN3_VIR2_3 0x010c 192 #define RK3368_WIN3_MST0 0x0110 193 #define RK3368_WIN3_DSP_INFO0 0x0114 194 #define RK3368_WIN3_DSP_ST0 0x0118 195 #define RK3368_WIN3_COLOR_KEY 0x011c 196 #define RK3368_WIN3_MST1 0x0120 197 #define RK3368_WIN3_DSP_INFO1 0x0124 198 #define RK3368_WIN3_DSP_ST1 0x0128 199 #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 200 #define RK3368_WIN3_MST2 0x0130 201 #define RK3368_WIN3_DSP_INFO2 0x0134 202 #define RK3368_WIN3_DSP_ST2 0x0138 203 #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 204 #define RK3368_WIN3_MST3 0x0140 205 #define RK3368_WIN3_DSP_INFO3 0x0144 206 #define RK3368_WIN3_DSP_ST3 0x0148 207 #define RK3368_WIN3_FADING_CTRL 0x014c 208 #define RK3368_HWC_CTRL0 0x0150 209 #define RK3368_HWC_CTRL1 0x0154 210 #define RK3368_HWC_MST 0x0158 211 #define RK3368_HWC_DSP_ST 0x015c 212 #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 213 #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 214 #define RK3368_HWC_FADING_CTRL 0x0168 215 #define RK3368_HWC_RESERVED1 0x016c 216 #define RK3368_POST_DSP_HACT_INFO 0x0170 217 #define RK3368_POST_DSP_VACT_INFO 0x0174 218 #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 219 #define RK3368_POST_RESERVED 0x017c 220 #define RK3368_POST_SCL_CTRL 0x0180 221 #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 222 #define RK3368_DSP_HTOTAL_HS_END 0x0188 223 #define RK3368_DSP_HACT_ST_END 0x018c 224 #define RK3368_DSP_VTOTAL_VS_END 0x0190 225 #define RK3368_DSP_VACT_ST_END 0x0194 226 #define RK3368_DSP_VS_ST_END_F1 0x0198 227 #define RK3368_DSP_VACT_ST_END_F1 0x019c 228 #define RK3368_PWM_CTRL 0x01a0 229 #define RK3368_PWM_PERIOD_HPR 0x01a4 230 #define RK3368_PWM_DUTY_LPR 0x01a8 231 #define RK3368_PWM_CNT 0x01ac 232 #define RK3368_BCSH_COLOR_BAR 0x01b0 233 #define RK3368_BCSH_BCS 0x01b4 234 #define RK3368_BCSH_H 0x01b8 235 #define RK3368_BCSH_CTRL 0x01bc 236 #define RK3368_CABC_CTRL0 0x01c0 237 #define RK3368_CABC_CTRL1 0x01c4 238 #define RK3368_CABC_CTRL2 0x01c8 239 #define RK3368_CABC_CTRL3 0x01cc 240 #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 241 #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 242 #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 243 #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 244 #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 245 #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 246 #define RK3368_FRC_LOWER01_0 0x01e8 247 #define RK3368_FRC_LOWER01_1 0x01ec 248 #define RK3368_FRC_LOWER10_0 0x01f0 249 #define RK3368_FRC_LOWER10_1 0x01f4 250 #define RK3368_FRC_LOWER11_0 0x01f8 251 #define RK3368_FRC_LOWER11_1 0x01fc 252 #define RK3368_IFBDC_CTRL 0x0200 253 #define RK3368_IFBDC_TILES_NUM 0x0204 254 #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 255 #define RK3368_IFBDC_BASE_ADDR 0x020c 256 #define RK3368_IFBDC_MB_SIZE 0x0210 257 #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 258 #define RK3368_IFBDC_VIR 0x0220 259 #define RK3368_IFBDC_DEBUG0 0x0230 260 #define RK3368_IFBDC_DEBUG1 0x0234 261 #define RK3368_LATENCY_CTRL0 0x0250 262 #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 263 #define RK3368_RD_LATENCY_THR_NUM0 0x0258 264 #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 265 #define RK3368_WIN0_DSP_BG 0x0260 266 #define RK3368_WIN1_DSP_BG 0x0264 267 #define RK3368_WIN2_DSP_BG 0x0268 268 #define RK3368_WIN3_DSP_BG 0x026c 269 #define RK3368_SCAN_LINE_NUM 0x0270 270 #define RK3368_CABC_DEBUG0 0x0274 271 #define RK3368_CABC_DEBUG1 0x0278 272 #define RK3368_CABC_DEBUG2 0x027c 273 #define RK3368_DBG_REG_000 0x0280 274 #define RK3368_DBG_REG_001 0x0284 275 #define RK3368_DBG_REG_002 0x0288 276 #define RK3368_DBG_REG_003 0x028c 277 #define RK3368_DBG_REG_004 0x0290 278 #define RK3368_DBG_REG_005 0x0294 279 #define RK3368_DBG_REG_006 0x0298 280 #define RK3368_DBG_REG_007 0x029c 281 #define RK3368_DBG_REG_008 0x02a0 282 #define RK3368_DBG_REG_016 0x02c0 283 #define RK3368_DBG_REG_017 0x02c4 284 #define RK3368_DBG_REG_018 0x02c8 285 #define RK3368_DBG_REG_019 0x02cc 286 #define RK3368_DBG_REG_020 0x02d0 287 #define RK3368_DBG_REG_021 0x02d4 288 #define RK3368_DBG_REG_022 0x02d8 289 #define RK3368_DBG_REG_023 0x02dc 290 #define RK3368_DBG_REG_028 0x02f0 291 #define RK3368_MMU_DTE_ADDR 0x0300 292 #define RK3368_MMU_STATUS 0x0304 293 #define RK3368_MMU_COMMAND 0x0308 294 #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 295 #define RK3368_MMU_ZAP_ONE_LINE 0x0310 296 #define RK3368_MMU_INT_RAWSTAT 0x0314 297 #define RK3368_MMU_INT_CLEAR 0x0318 298 #define RK3368_MMU_INT_MASK 0x031c 299 #define RK3368_MMU_INT_STATUS 0x0320 300 #define RK3368_MMU_AUTO_GATING 0x0324 301 #define RK3368_WIN2_LUT_ADDR 0x0400 302 #define RK3368_WIN3_LUT_ADDR 0x0800 303 #define RK3368_HWC_LUT_ADDR 0x0c00 304 #define RK3368_GAMMA_LUT_ADDR 0x1000 305 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 306 #define RK3368_MCU_BYPASS_WPORT 0x2200 307 #define RK3368_MCU_BYPASS_RPORT 0x2300 308 #define RK3368_GRF_SOC_CON6 0x0418 309 /* rk3368 register definition end */ 310 311 #define RK3366_REG_CFG_DONE 0x0000 312 #define RK3366_VERSION_INFO 0x0004 313 #define RK3366_SYS_CTRL 0x0008 314 #define RK3366_SYS_CTRL1 0x000c 315 #define RK3366_DSP_CTRL0 0x0010 316 #define RK3366_DSP_CTRL1 0x0014 317 #define RK3366_DSP_BG 0x0018 318 #define RK3366_MCU_CTRL 0x001c 319 #define RK3366_WB_CTRL0 0x0020 320 #define RK3366_WB_CTRL1 0x0024 321 #define RK3366_WB_YRGB_MST 0x0028 322 #define RK3366_WB_CBR_MST 0x002c 323 #define RK3366_WIN0_CTRL0 0x0030 324 #define RK3366_WIN0_CTRL1 0x0034 325 #define RK3366_WIN0_COLOR_KEY 0x0038 326 #define RK3366_WIN0_VIR 0x003c 327 #define RK3366_WIN0_YRGB_MST 0x0040 328 #define RK3366_WIN0_CBR_MST 0x0044 329 #define RK3366_WIN0_ACT_INFO 0x0048 330 #define RK3366_WIN0_DSP_INFO 0x004c 331 #define RK3366_WIN0_DSP_ST 0x0050 332 #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 333 #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 334 #define RK3366_WIN0_SCL_OFFSET 0x005c 335 #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 336 #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 337 #define RK3366_WIN0_FADING_CTRL 0x0068 338 #define RK3366_WIN0_CTRL2 0x006c 339 #define RK3366_WIN1_CTRL0 0x0070 340 #define RK3366_WIN1_CTRL1 0x0074 341 #define RK3366_WIN1_COLOR_KEY 0x0078 342 #define RK3366_WIN1_VIR 0x007c 343 #define RK3366_WIN1_YRGB_MST 0x0080 344 #define RK3366_WIN1_CBR_MST 0x0084 345 #define RK3366_WIN1_ACT_INFO 0x0088 346 #define RK3366_WIN1_DSP_INFO 0x008c 347 #define RK3366_WIN1_DSP_ST 0x0090 348 #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 349 #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 350 #define RK3366_WIN1_SCL_OFFSET 0x009c 351 #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 352 #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 353 #define RK3366_WIN1_FADING_CTRL 0x00a8 354 #define RK3366_WIN1_CTRL2 0x00ac 355 #define RK3366_WIN2_CTRL0 0x00b0 356 #define RK3366_WIN2_CTRL1 0x00b4 357 #define RK3366_WIN2_VIR0_1 0x00b8 358 #define RK3366_WIN2_VIR2_3 0x00bc 359 #define RK3366_WIN2_MST0 0x00c0 360 #define RK3366_WIN2_DSP_INFO0 0x00c4 361 #define RK3366_WIN2_DSP_ST0 0x00c8 362 #define RK3366_WIN2_COLOR_KEY 0x00cc 363 #define RK3366_WIN2_MST1 0x00d0 364 #define RK3366_WIN2_DSP_INFO1 0x00d4 365 #define RK3366_WIN2_DSP_ST1 0x00d8 366 #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 367 #define RK3366_WIN2_MST2 0x00e0 368 #define RK3366_WIN2_DSP_INFO2 0x00e4 369 #define RK3366_WIN2_DSP_ST2 0x00e8 370 #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 371 #define RK3366_WIN2_MST3 0x00f0 372 #define RK3366_WIN2_DSP_INFO3 0x00f4 373 #define RK3366_WIN2_DSP_ST3 0x00f8 374 #define RK3366_WIN2_FADING_CTRL 0x00fc 375 #define RK3366_WIN3_CTRL0 0x0100 376 #define RK3366_WIN3_CTRL1 0x0104 377 #define RK3366_WIN3_VIR0_1 0x0108 378 #define RK3366_WIN3_VIR2_3 0x010c 379 #define RK3366_WIN3_MST0 0x0110 380 #define RK3366_WIN3_DSP_INFO0 0x0114 381 #define RK3366_WIN3_DSP_ST0 0x0118 382 #define RK3366_WIN3_COLOR_KEY 0x011c 383 #define RK3366_WIN3_MST1 0x0120 384 #define RK3366_WIN3_DSP_INFO1 0x0124 385 #define RK3366_WIN3_DSP_ST1 0x0128 386 #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 387 #define RK3366_WIN3_MST2 0x0130 388 #define RK3366_WIN3_DSP_INFO2 0x0134 389 #define RK3366_WIN3_DSP_ST2 0x0138 390 #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 391 #define RK3366_WIN3_MST3 0x0140 392 #define RK3366_WIN3_DSP_INFO3 0x0144 393 #define RK3366_WIN3_DSP_ST3 0x0148 394 #define RK3366_WIN3_FADING_CTRL 0x014c 395 #define RK3366_HWC_CTRL0 0x0150 396 #define RK3366_HWC_CTRL1 0x0154 397 #define RK3366_HWC_MST 0x0158 398 #define RK3366_HWC_DSP_ST 0x015c 399 #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 400 #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 401 #define RK3366_HWC_FADING_CTRL 0x0168 402 #define RK3366_HWC_RESERVED1 0x016c 403 #define RK3366_POST_DSP_HACT_INFO 0x0170 404 #define RK3366_POST_DSP_VACT_INFO 0x0174 405 #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 406 #define RK3366_POST_RESERVED 0x017c 407 #define RK3366_POST_SCL_CTRL 0x0180 408 #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 409 #define RK3366_DSP_HTOTAL_HS_END 0x0188 410 #define RK3366_DSP_HACT_ST_END 0x018c 411 #define RK3366_DSP_VTOTAL_VS_END 0x0190 412 #define RK3366_DSP_VACT_ST_END 0x0194 413 #define RK3366_DSP_VS_ST_END_F1 0x0198 414 #define RK3366_DSP_VACT_ST_END_F1 0x019c 415 #define RK3366_PWM_CTRL 0x01a0 416 #define RK3366_PWM_PERIOD_HPR 0x01a4 417 #define RK3366_PWM_DUTY_LPR 0x01a8 418 #define RK3366_PWM_CNT 0x01ac 419 #define RK3366_BCSH_COLOR_BAR 0x01b0 420 #define RK3366_BCSH_BCS 0x01b4 421 #define RK3366_BCSH_H 0x01b8 422 #define RK3366_BCSH_CTRL 0x01bc 423 #define RK3366_CABC_CTRL0 0x01c0 424 #define RK3366_CABC_CTRL1 0x01c4 425 #define RK3366_CABC_CTRL2 0x01c8 426 #define RK3366_CABC_CTRL3 0x01cc 427 #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 428 #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 429 #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 430 #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 431 #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 432 #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 433 #define RK3366_FRC_LOWER01_0 0x01e8 434 #define RK3366_FRC_LOWER01_1 0x01ec 435 #define RK3366_FRC_LOWER10_0 0x01f0 436 #define RK3366_FRC_LOWER10_1 0x01f4 437 #define RK3366_FRC_LOWER11_0 0x01f8 438 #define RK3366_FRC_LOWER11_1 0x01fc 439 #define RK3366_INTR_EN0 0x0280 440 #define RK3366_INTR_CLEAR0 0x0284 441 #define RK3366_INTR_STATUS0 0x0288 442 #define RK3366_INTR_RAW_STATUS0 0x028c 443 #define RK3366_INTR_EN1 0x0290 444 #define RK3366_INTR_CLEAR1 0x0294 445 #define RK3366_INTR_STATUS1 0x0298 446 #define RK3366_INTR_RAW_STATUS1 0x029c 447 #define RK3366_LINE_FLAG 0x02a0 448 #define RK3366_VOP_STATUS 0x02a4 449 #define RK3366_BLANKING_VALUE 0x02a8 450 #define RK3366_WIN0_DSP_BG 0x02b0 451 #define RK3366_WIN1_DSP_BG 0x02b4 452 #define RK3366_WIN2_DSP_BG 0x02b8 453 #define RK3366_WIN3_DSP_BG 0x02bc 454 #define RK3366_WIN2_LUT_ADDR 0x0400 455 #define RK3366_WIN3_LUT_ADDR 0x0800 456 #define RK3366_HWC_LUT_ADDR 0x0c00 457 #define RK3366_GAMMA0_LUT_ADDR 0x1000 458 #define RK3366_GAMMA1_LUT_ADDR 0x1400 459 #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 460 #define RK3366_MCU_BYPASS_WPORT 0x2200 461 #define RK3366_MCU_BYPASS_RPORT 0x2300 462 #define RK3366_MMU_DTE_ADDR 0x2400 463 #define RK3366_MMU_STATUS 0x2404 464 #define RK3366_MMU_COMMAND 0x2408 465 #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 466 #define RK3366_MMU_ZAP_ONE_LINE 0x2410 467 #define RK3366_MMU_INT_RAWSTAT 0x2414 468 #define RK3366_MMU_INT_CLEAR 0x2418 469 #define RK3366_MMU_INT_MASK 0x241c 470 #define RK3366_MMU_INT_STATUS 0x2420 471 #define RK3366_MMU_AUTO_GATING 0x2424 472 473 /* rk3399 register definition */ 474 #define RK3399_REG_CFG_DONE 0x0000 475 #define RK3399_VERSION_INFO 0x0004 476 #define RK3399_SYS_CTRL 0x0008 477 #define RK3399_SYS_CTRL1 0x000c 478 #define RK3399_DSP_CTRL0 0x0010 479 #define RK3399_DSP_CTRL1 0x0014 480 #define RK3399_DSP_BG 0x0018 481 #define RK3399_MCU_CTRL 0x001c 482 #define RK3399_WB_CTRL0 0x0020 483 #define RK3399_WB_CTRL1 0x0024 484 #define RK3399_WB_YRGB_MST 0x0028 485 #define RK3399_WB_CBR_MST 0x002c 486 #define RK3399_WIN0_CTRL0 0x0030 487 #define RK3399_WIN0_CTRL1 0x0034 488 #define RK3399_WIN0_COLOR_KEY 0x0038 489 #define RK3399_WIN0_VIR 0x003c 490 #define RK3399_WIN0_YRGB_MST 0x0040 491 #define RK3399_WIN0_CBR_MST 0x0044 492 #define RK3399_WIN0_ACT_INFO 0x0048 493 #define RK3399_WIN0_DSP_INFO 0x004c 494 #define RK3399_WIN0_DSP_ST 0x0050 495 #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 496 #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 497 #define RK3399_WIN0_SCL_OFFSET 0x005c 498 #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 499 #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 500 #define RK3399_WIN0_FADING_CTRL 0x0068 501 #define RK3399_WIN0_CTRL2 0x006c 502 #define RK3399_WIN1_CTRL0 0x0070 503 #define RK3399_WIN1_CTRL1 0x0074 504 #define RK3399_WIN1_COLOR_KEY 0x0078 505 #define RK3399_WIN1_VIR 0x007c 506 #define RK3399_WIN1_YRGB_MST 0x0080 507 #define RK3399_WIN1_CBR_MST 0x0084 508 #define RK3399_WIN1_ACT_INFO 0x0088 509 #define RK3399_WIN1_DSP_INFO 0x008c 510 #define RK3399_WIN1_DSP_ST 0x0090 511 #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 512 #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 513 #define RK3399_WIN1_SCL_OFFSET 0x009c 514 #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 515 #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 516 #define RK3399_WIN1_FADING_CTRL 0x00a8 517 #define RK3399_WIN1_CTRL2 0x00ac 518 #define RK3399_WIN2_CTRL0 0x00b0 519 #define RK3399_WIN2_CTRL1 0x00b4 520 #define RK3399_WIN2_VIR0_1 0x00b8 521 #define RK3399_WIN2_VIR2_3 0x00bc 522 #define RK3399_WIN2_MST0 0x00c0 523 #define RK3399_WIN2_DSP_INFO0 0x00c4 524 #define RK3399_WIN2_DSP_ST0 0x00c8 525 #define RK3399_WIN2_COLOR_KEY 0x00cc 526 #define RK3399_WIN2_MST1 0x00d0 527 #define RK3399_WIN2_DSP_INFO1 0x00d4 528 #define RK3399_WIN2_DSP_ST1 0x00d8 529 #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 530 #define RK3399_WIN2_MST2 0x00e0 531 #define RK3399_WIN2_DSP_INFO2 0x00e4 532 #define RK3399_WIN2_DSP_ST2 0x00e8 533 #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 534 #define RK3399_WIN2_MST3 0x00f0 535 #define RK3399_WIN2_DSP_INFO3 0x00f4 536 #define RK3399_WIN2_DSP_ST3 0x00f8 537 #define RK3399_WIN2_FADING_CTRL 0x00fc 538 #define RK3399_WIN3_CTRL0 0x0100 539 #define RK3399_WIN3_CTRL1 0x0104 540 #define RK3399_WIN3_VIR0_1 0x0108 541 #define RK3399_WIN3_VIR2_3 0x010c 542 #define RK3399_WIN3_MST0 0x0110 543 #define RK3399_WIN3_DSP_INFO0 0x0114 544 #define RK3399_WIN3_DSP_ST0 0x0118 545 #define RK3399_WIN3_COLOR_KEY 0x011c 546 #define RK3399_WIN3_MST1 0x0120 547 #define RK3399_WIN3_DSP_INFO1 0x0124 548 #define RK3399_WIN3_DSP_ST1 0x0128 549 #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 550 #define RK3399_WIN3_MST2 0x0130 551 #define RK3399_WIN3_DSP_INFO2 0x0134 552 #define RK3399_WIN3_DSP_ST2 0x0138 553 #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 554 #define RK3399_WIN3_MST3 0x0140 555 #define RK3399_WIN3_DSP_INFO3 0x0144 556 #define RK3399_WIN3_DSP_ST3 0x0148 557 #define RK3399_WIN3_FADING_CTRL 0x014c 558 #define RK3399_HWC_CTRL0 0x0150 559 #define RK3399_HWC_CTRL1 0x0154 560 #define RK3399_HWC_MST 0x0158 561 #define RK3399_HWC_DSP_ST 0x015c 562 #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 563 #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 564 #define RK3399_HWC_FADING_CTRL 0x0168 565 #define RK3399_HWC_RESERVED1 0x016c 566 #define RK3399_POST_DSP_HACT_INFO 0x0170 567 #define RK3399_POST_DSP_VACT_INFO 0x0174 568 #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 569 #define RK3399_POST_RESERVED 0x017c 570 #define RK3399_POST_SCL_CTRL 0x0180 571 #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 572 #define RK3399_DSP_HTOTAL_HS_END 0x0188 573 #define RK3399_DSP_HACT_ST_END 0x018c 574 #define RK3399_DSP_VTOTAL_VS_END 0x0190 575 #define RK3399_DSP_VACT_ST_END 0x0194 576 #define RK3399_DSP_VS_ST_END_F1 0x0198 577 #define RK3399_DSP_VACT_ST_END_F1 0x019c 578 #define RK3399_PWM_CTRL 0x01a0 579 #define RK3399_PWM_PERIOD_HPR 0x01a4 580 #define RK3399_PWM_DUTY_LPR 0x01a8 581 #define RK3399_PWM_CNT 0x01ac 582 #define RK3399_BCSH_COLOR_BAR 0x01b0 583 #define RK3399_BCSH_BCS 0x01b4 584 #define RK3399_BCSH_H 0x01b8 585 #define RK3399_BCSH_CTRL 0x01bc 586 #define RK3399_CABC_CTRL0 0x01c0 587 #define RK3399_CABC_CTRL1 0x01c4 588 #define RK3399_CABC_CTRL2 0x01c8 589 #define RK3399_CABC_CTRL3 0x01cc 590 #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 591 #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 592 #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 593 #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 594 #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 595 #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 596 #define RK3399_FRC_LOWER01_0 0x01e8 597 #define RK3399_FRC_LOWER01_1 0x01ec 598 #define RK3399_FRC_LOWER10_0 0x01f0 599 #define RK3399_FRC_LOWER10_1 0x01f4 600 #define RK3399_FRC_LOWER11_0 0x01f8 601 #define RK3399_FRC_LOWER11_1 0x01fc 602 #define RK3399_AFBCD0_CTRL 0x0200 603 #define RK3399_AFBCD0_HDR_PTR 0x0204 604 #define RK3399_AFBCD0_PIC_SIZE 0x0208 605 #define RK3399_AFBCD0_STATUS 0x020c 606 #define RK3399_AFBCD1_CTRL 0x0220 607 #define RK3399_AFBCD1_HDR_PTR 0x0224 608 #define RK3399_AFBCD1_PIC_SIZE 0x0228 609 #define RK3399_AFBCD1_STATUS 0x022c 610 #define RK3399_AFBCD2_CTRL 0x0240 611 #define RK3399_AFBCD2_HDR_PTR 0x0244 612 #define RK3399_AFBCD2_PIC_SIZE 0x0248 613 #define RK3399_AFBCD2_STATUS 0x024c 614 #define RK3399_AFBCD3_CTRL 0x0260 615 #define RK3399_AFBCD3_HDR_PTR 0x0264 616 #define RK3399_AFBCD3_PIC_SIZE 0x0268 617 #define RK3399_AFBCD3_STATUS 0x026c 618 #define RK3399_INTR_EN0 0x0280 619 #define RK3399_INTR_CLEAR0 0x0284 620 #define RK3399_INTR_STATUS0 0x0288 621 #define RK3399_INTR_RAW_STATUS0 0x028c 622 #define RK3399_INTR_EN1 0x0290 623 #define RK3399_INTR_CLEAR1 0x0294 624 #define RK3399_INTR_STATUS1 0x0298 625 #define RK3399_INTR_RAW_STATUS1 0x029c 626 #define RK3399_LINE_FLAG 0x02a0 627 #define RK3399_VOP_STATUS 0x02a4 628 #define RK3399_BLANKING_VALUE 0x02a8 629 #define RK3399_MCU_BYPASS_PORT 0x02ac 630 #define RK3399_WIN0_DSP_BG 0x02b0 631 #define RK3399_WIN1_DSP_BG 0x02b4 632 #define RK3399_WIN2_DSP_BG 0x02b8 633 #define RK3399_WIN3_DSP_BG 0x02bc 634 #define RK3399_YUV2YUV_WIN 0x02c0 635 #define RK3399_YUV2YUV_POST 0x02c4 636 #define RK3399_AUTO_GATING_EN 0x02cc 637 #define RK3399_DBG_POST_REG1 0x036c 638 #define RK3399_WIN0_CSC_COE 0x03a0 639 #define RK3399_WIN1_CSC_COE 0x03c0 640 #define RK3399_WIN2_CSC_COE 0x03e0 641 #define RK3399_WIN3_CSC_COE 0x0400 642 #define RK3399_HWC_CSC_COE 0x0420 643 #define RK3399_BCSH_R2Y_CSC_COE 0x0440 644 #define RK3399_BCSH_Y2R_CSC_COE 0x0460 645 #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 646 #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 647 #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 648 #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 649 #define RK3399_WIN0_YUV2YUV_3X3 0x0500 650 #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 651 #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 652 #define RK3399_WIN1_YUV2YUV_3X3 0x0560 653 #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 654 #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 655 #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 656 #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 657 #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 658 #define RK3399_WIN3_YUV2YUV_3X3 0x0620 659 #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 660 #define RK3399_WIN2_LUT_ADDR 0x1000 661 #define RK3399_WIN3_LUT_ADDR 0x1400 662 #define RK3399_HWC_LUT_ADDR 0x1800 663 #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 664 #define RK3399_GAMMA_LUT_ADDR 0x2000 665 /* rk3399 register definition end */ 666 667 /* rk3328 register definition end */ 668 #define RK3328_REG_CFG_DONE 0x00000000 669 #define RK3328_VERSION_INFO 0x00000004 670 #define RK3328_SYS_CTRL 0x00000008 671 #define RK3328_SYS_CTRL1 0x0000000c 672 #define RK3328_DSP_CTRL0 0x00000010 673 #define RK3328_DSP_CTRL1 0x00000014 674 #define RK3328_DSP_BG 0x00000018 675 #define RK3328_AUTO_GATING_EN 0x0000003c 676 #define RK3328_LINE_FLAG 0x00000040 677 #define RK3328_VOP_STATUS 0x00000044 678 #define RK3328_BLANKING_VALUE 0x00000048 679 #define RK3328_WIN0_DSP_BG 0x00000050 680 #define RK3328_WIN1_DSP_BG 0x00000054 681 #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 682 #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 683 #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 684 #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 685 #define RK3328_INTR_EN0 0x000000e0 686 #define RK3328_INTR_CLEAR0 0x000000e4 687 #define RK3328_INTR_STATUS0 0x000000e8 688 #define RK3328_INTR_RAW_STATUS0 0x000000ec 689 #define RK3328_INTR_EN1 0x000000f0 690 #define RK3328_INTR_CLEAR1 0x000000f4 691 #define RK3328_INTR_STATUS1 0x000000f8 692 #define RK3328_INTR_RAW_STATUS1 0x000000fc 693 #define RK3328_WIN0_CTRL0 0x00000100 694 #define RK3328_WIN0_CTRL1 0x00000104 695 #define RK3328_WIN0_COLOR_KEY 0x00000108 696 #define RK3328_WIN0_VIR 0x0000010c 697 #define RK3328_WIN0_YRGB_MST 0x00000110 698 #define RK3328_WIN0_CBR_MST 0x00000114 699 #define RK3328_WIN0_ACT_INFO 0x00000118 700 #define RK3328_WIN0_DSP_INFO 0x0000011c 701 #define RK3328_WIN0_DSP_ST 0x00000120 702 #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 703 #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 704 #define RK3328_WIN0_SCL_OFFSET 0x0000012c 705 #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 706 #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 707 #define RK3328_WIN0_FADING_CTRL 0x00000138 708 #define RK3328_WIN0_CTRL2 0x0000013c 709 #define RK3328_DBG_WIN0_REG0 0x000001f0 710 #define RK3328_DBG_WIN0_REG1 0x000001f4 711 #define RK3328_DBG_WIN0_REG2 0x000001f8 712 #define RK3328_DBG_WIN0_RESERVED 0x000001fc 713 #define RK3328_WIN1_CTRL0 0x00000200 714 #define RK3328_WIN1_CTRL1 0x00000204 715 #define RK3328_WIN1_COLOR_KEY 0x00000208 716 #define RK3328_WIN1_VIR 0x0000020c 717 #define RK3328_WIN1_YRGB_MST 0x00000210 718 #define RK3328_WIN1_CBR_MST 0x00000214 719 #define RK3328_WIN1_ACT_INFO 0x00000218 720 #define RK3328_WIN1_DSP_INFO 0x0000021c 721 #define RK3328_WIN1_DSP_ST 0x00000220 722 #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 723 #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 724 #define RK3328_WIN1_SCL_OFFSET 0x0000022c 725 #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 726 #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 727 #define RK3328_WIN1_FADING_CTRL 0x00000238 728 #define RK3328_WIN1_CTRL2 0x0000023c 729 #define RK3328_DBG_WIN1_REG0 0x000002f0 730 #define RK3328_DBG_WIN1_REG1 0x000002f4 731 #define RK3328_DBG_WIN1_REG2 0x000002f8 732 #define RK3328_DBG_WIN1_RESERVED 0x000002fc 733 #define RK3328_WIN2_CTRL0 0x00000300 734 #define RK3328_WIN2_CTRL1 0x00000304 735 #define RK3328_WIN2_COLOR_KEY 0x00000308 736 #define RK3328_WIN2_VIR 0x0000030c 737 #define RK3328_WIN2_YRGB_MST 0x00000310 738 #define RK3328_WIN2_CBR_MST 0x00000314 739 #define RK3328_WIN2_ACT_INFO 0x00000318 740 #define RK3328_WIN2_DSP_INFO 0x0000031c 741 #define RK3328_WIN2_DSP_ST 0x00000320 742 #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 743 #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 744 #define RK3328_WIN2_SCL_OFFSET 0x0000032c 745 #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 746 #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 747 #define RK3328_WIN2_FADING_CTRL 0x00000338 748 #define RK3328_WIN2_CTRL2 0x0000033c 749 #define RK3328_DBG_WIN2_REG0 0x000003f0 750 #define RK3328_DBG_WIN2_REG1 0x000003f4 751 #define RK3328_DBG_WIN2_REG2 0x000003f8 752 #define RK3328_DBG_WIN2_RESERVED 0x000003fc 753 #define RK3328_WIN3_CTRL0 0x00000400 754 #define RK3328_WIN3_CTRL1 0x00000404 755 #define RK3328_WIN3_COLOR_KEY 0x00000408 756 #define RK3328_WIN3_VIR 0x0000040c 757 #define RK3328_WIN3_YRGB_MST 0x00000410 758 #define RK3328_WIN3_CBR_MST 0x00000414 759 #define RK3328_WIN3_ACT_INFO 0x00000418 760 #define RK3328_WIN3_DSP_INFO 0x0000041c 761 #define RK3328_WIN3_DSP_ST 0x00000420 762 #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 763 #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 764 #define RK3328_WIN3_SCL_OFFSET 0x0000042c 765 #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 766 #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 767 #define RK3328_WIN3_FADING_CTRL 0x00000438 768 #define RK3328_WIN3_CTRL2 0x0000043c 769 #define RK3328_DBG_WIN3_REG0 0x000004f0 770 #define RK3328_DBG_WIN3_REG1 0x000004f4 771 #define RK3328_DBG_WIN3_REG2 0x000004f8 772 #define RK3328_DBG_WIN3_RESERVED 0x000004fc 773 774 #define RK3328_HWC_CTRL0 0x00000500 775 #define RK3328_HWC_CTRL1 0x00000504 776 #define RK3328_HWC_MST 0x00000508 777 #define RK3328_HWC_DSP_ST 0x0000050c 778 #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 779 #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 780 #define RK3328_HWC_FADING_CTRL 0x00000518 781 #define RK3328_HWC_RESERVED1 0x0000051c 782 #define RK3328_POST_DSP_HACT_INFO 0x00000600 783 #define RK3328_POST_DSP_VACT_INFO 0x00000604 784 #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 785 #define RK3328_POST_RESERVED 0x0000060c 786 #define RK3328_POST_SCL_CTRL 0x00000610 787 #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 788 #define RK3328_DSP_HTOTAL_HS_END 0x00000618 789 #define RK3328_DSP_HACT_ST_END 0x0000061c 790 #define RK3328_DSP_VTOTAL_VS_END 0x00000620 791 #define RK3328_DSP_VACT_ST_END 0x00000624 792 #define RK3328_DSP_VS_ST_END_F1 0x00000628 793 #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 794 #define RK3328_BCSH_COLOR_BAR 0x00000640 795 #define RK3328_BCSH_BCS 0x00000644 796 #define RK3328_BCSH_H 0x00000648 797 #define RK3328_BCSH_CTRL 0x0000064c 798 #define RK3328_FRC_LOWER01_0 0x00000678 799 #define RK3328_FRC_LOWER01_1 0x0000067c 800 #define RK3328_FRC_LOWER10_0 0x00000680 801 #define RK3328_FRC_LOWER10_1 0x00000684 802 #define RK3328_FRC_LOWER11_0 0x00000688 803 #define RK3328_FRC_LOWER11_1 0x0000068c 804 #define RK3328_DBG_POST_REG0 0x000006e8 805 #define RK3328_DBG_POST_RESERVED 0x000006ec 806 #define RK3328_DBG_DATAO 0x000006f0 807 #define RK3328_DBG_DATAO_2 0x000006f4 808 #define RK3328_SDR2HDR_CTRL 0x00000700 809 #define RK3328_SDR2HDR_EOTF_OETF_Y0 0x00000704 810 #define RK3328_SDR2HDR_EOTF_OETF_Y1 0x00000710 811 #define RK3328_SDR2HDR_OETF_DX_DXPOW1 0x00000810 812 #define RK3328_SDR2HDR_OETF_XN1 0x00000910 813 814 #define RK3328_HDR2DR_CTRL 0x00000a10 815 #define RK3328_HDR2DR_SRC_RANGE 0x00000a14 816 #define RK3328_HDR2DR_NORMFACEETF 0x00000a18 817 #define RK3328_HDR2DR_DST_RANGE 0x00000a20 818 #define RK3328_HDR2DR_NORMFACGAMMA 0x00000a24 819 #define RK3328_HDR2SDR_EETF_OETF_Y0 0x00000a28 820 #define RK3328_HDR2DR_SAT_Y0 0x00000a2C 821 #define RK3328_HDR2SDR_EETF_OETF_Y1 0x00000a30 822 #define RK3328_HDR2DR_SAT_Y1 0x00000ab0 823 824 /* sdr to hdr */ 825 #define RK3328_SDR2HDR_CTRL 0x00000700 826 #define RK3328_EOTF_OETF_Y0 0x00000704 827 #define RK3328_RESERVED0001 0x00000708 828 #define RK3328_RESERVED0002 0x0000070c 829 #define RK3328_EOTF_OETF_Y1 0x00000710 830 #define RK3328_EOTF_OETF_Y64 0x0000080c 831 #define RK3328_OETF_DX_DXPOW1 0x00000810 832 #define RK3328_OETF_DX_DXPOW64 0x0000090c 833 #define RK3328_OETF_XN1 0x00000910 834 #define RK3328_OETF_XN63 0x00000a08 835 836 /* hdr to sdr */ 837 #define RK3328_HDR2SDR_CTRL 0x00000a10 838 #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 839 #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 840 #define RK3328_RESERVED0003 0x00000a1c 841 #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 842 #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 843 #define RK3328_EETF_OETF_Y0 0x00000a28 844 #define RK3328_SAT_Y0 0x00000a2c 845 #define RK3328_EETF_OETF_Y1 0x00000a30 846 #define RK3328_SAT_Y1 0x00000ab0 847 #define RK3328_SAT_Y8 0x00000acc 848 849 #define RK3328_HWC_LUT_ADDR 0x00000c00 850 851 /* rk3036 register definition */ 852 #define RK3036_SYS_CTRL 0x00 853 #define RK3036_DSP_CTRL0 0x04 854 #define RK3036_DSP_CTRL1 0x08 855 #define RK3036_INT_SCALER 0x0c 856 #define RK3036_INT_STATUS 0x10 857 #define RK3036_ALPHA_CTRL 0x14 858 #define RK3036_WIN0_COLOR_KEY 0x18 859 #define RK3036_WIN1_COLOR_KEY 0x1c 860 #define RK3036_WIN0_YRGB_MST 0x20 861 #define RK3036_WIN0_CBR_MST 0x24 862 #define RK3036_WIN1_VIR 0x28 863 #define RK3036_AXI_BUS_CTRL 0x2c 864 #define RK3036_WIN0_VIR 0x30 865 #define RK3036_WIN0_ACT_INFO 0x34 866 #define RK3036_WIN0_DSP_INFO 0x38 867 #define RK3036_WIN0_DSP_ST 0x3c 868 #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 869 #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 870 #define RK3036_WIN0_SCL_OFFSET 0x48 871 #define RK3036_HWC_MST 0x58 872 #define RK3036_HWC_DSP_ST 0x5c 873 #define RK3036_DSP_HTOTAL_HS_END 0x6c 874 #define RK3036_DSP_HACT_ST_END 0x70 875 #define RK3036_DSP_VTOTAL_VS_END 0x74 876 #define RK3036_DSP_VACT_ST_END 0x78 877 #define RK3036_DSP_VS_ST_END_F1 0x7c 878 #define RK3036_DSP_VACT_ST_END_F1 0x80 879 #define RK3036_GATHER_TRANSFER 0x84 880 #define RK3036_VERSION_INFO 0x94 881 #define RK3036_REG_CFG_DONE 0x90 882 #define RK3036_WIN1_MST 0xa0 883 #define RK3036_WIN1_ACT_INFO 0xb4 884 #define RK3036_WIN1_DSP_INFO 0xb8 885 #define RK3036_WIN1_DSP_ST 0xbc 886 #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 887 #define RK3036_WIN1_SCL_OFFSET 0xc8 888 #define RK3036_BCSH_CTRL 0xd0 889 #define RK3036_BCSH_COLOR_BAR 0xd4 890 #define RK3036_BCSH_BCS 0xd8 891 #define RK3036_BCSH_H 0xdc 892 #define RK3036_WIN1_LUT_ADDR 0x400 893 #define RK3036_HWC_LUT_ADDR 0x800 894 /* rk3036 register definition end */ 895 896 #define RK3066_SYS_CTRL0 0x00 897 #define RK3066_SYS_CTRL1 0x04 898 #define RK3066_DSP_CTRL0 0x08 899 #define RK3066_DSP_CTRL1 0x0c 900 #define RK3066_INT_STATUS 0x10 901 #define RK3066_MCU_CTRL 0x14 902 #define RK3066_BLEND_CTRL 0x18 903 #define RK3066_WIN0_COLOR_KEY_CTRL 0x1c 904 #define RK3066_WIN1_COLOR_KEY_CTRL 0x20 905 #define RK3066_WIN2_COLOR_KEY_CTRL 0x24 906 #define RK3066_WIN0_YRGB_MST0 0x28 907 #define RK3066_WIN0_CBR_MST0 0x2c 908 #define RK3066_WIN0_YRGB_MST1 0x30 909 #define RK3066_WIN0_CBR_MST1 0x34 910 #define RK3066_WIN0_VIR 0x38 911 #define RK3066_WIN0_ACT_INFO 0x3c 912 #define RK3066_WIN0_DSP_INFO 0x40 913 #define RK3066_WIN0_DSP_ST 0x44 914 #define RK3066_WIN0_SCL_FACTOR_YRGB 0x48 915 #define RK3066_WIN0_SCL_FACTOR_CBR 0x4c 916 #define RK3066_WIN0_SCL_OFFSET 0x50 917 #define RK3066_WIN1_YRGB_MST 0x54 918 #define RK3066_WIN1_CBR_MST 0x58 919 #define RK3066_WIN1_VIR 0x5c 920 #define RK3066_WIN1_ACT_INFO 0x60 921 #define RK3066_WIN1_DSP_INFO 0x64 922 #define RK3066_WIN1_DSP_ST 0x68 923 #define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c 924 #define RK3066_WIN1_SCL_FACTOR_CBR 0x70 925 #define RK3066_WIN1_SCL_OFFSET 0x74 926 #define RK3066_WIN2_MST 0x78 927 #define RK3066_WIN2_VIR 0x7c 928 #define RK3066_WIN2_DSP_INFO 0x80 929 #define RK3066_WIN2_DSP_ST 0x84 930 #define RK3066_HWC_MST 0x88 931 #define RK3066_HWC_DSP_ST 0x8c 932 #define RK3066_HWC_COLOR_LUT0 0x90 933 #define RK3066_HWC_COLOR_LUT1 0x94 934 #define RK3066_HWC_COLOR_LUT2 0x98 935 #define RK3066_DSP_HTOTAL_HS_END 0x9c 936 #define RK3066_DSP_HACT_ST_END 0xa0 937 #define RK3066_DSP_VTOTAL_VS_END 0xa4 938 #define RK3066_DSP_VACT_ST_END 0xa8 939 #define RK3066_DSP_VS_ST_END_F1 0xac 940 #define RK3066_DSP_VACT_ST_END_F1 0xb0 941 #define RK3066_REG_CFG_DONE 0xc0 942 #define RK3066_MCU_BYPASS_WPORT 0x100 943 #define RK3066_MCU_BYPASS_RPORT 0x200 944 #define RK3066_WIN2_LUT_ADDR 0x400 945 #define RK3066_DSP_LUT_ADDR 0x800 946 947 /* rk3366 register definition */ 948 #define RK3366_LIT_REG_CFG_DONE 0x00000 949 #define RK3366_LIT_VERSION 0x00004 950 #define RK3366_LIT_DSP_BG 0x00008 951 #define RK3366_LIT_MCU_CTRL 0x0000c 952 #define RK3366_LIT_SYS_CTRL0 0x00010 953 #define RK3366_LIT_SYS_CTRL1 0x00014 954 #define RK3366_LIT_SYS_CTRL2 0x00018 955 #define RK3366_LIT_DSP_CTRL0 0x00020 956 #define RK3366_LIT_DSP_CTRL2 0x00028 957 #define RK3366_LIT_VOP_STATUS 0x0002c 958 #define RK3366_LIT_LINE_FLAG 0x00030 959 #define RK3366_LIT_INTR_EN 0x00034 960 #define RK3366_LIT_INTR_CLEAR 0x00038 961 #define RK3366_LIT_INTR_STATUS 0x0003c 962 #define RK3366_LIT_WIN0_CTRL0 0x00050 963 #define RK3366_LIT_WIN0_CTRL1 0x00054 964 #define RK3366_LIT_WIN0_COLOR_KEY 0x00058 965 #define RK3366_LIT_WIN0_VIR 0x0005c 966 #define RK3366_LIT_WIN0_YRGB_MST0 0x00060 967 #define RK3366_LIT_WIN0_CBR_MST0 0x00064 968 #define RK3366_LIT_WIN0_ACT_INFO 0x00068 969 #define RK3366_LIT_WIN0_DSP_INFO 0x0006c 970 #define RK3366_LIT_WIN0_DSP_ST 0x00070 971 #define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 972 #define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078 973 #define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c 974 #define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080 975 #define RK3366_LIT_WIN1_CTRL0 0x00090 976 #define RK3366_LIT_WIN1_CTRL1 0x00094 977 #define RK3366_LIT_WIN1_VIR 0x00098 978 #define RK3366_LIT_WIN1_MST 0x000a0 979 #define RK3366_LIT_WIN1_DSP_INFO 0x000a4 980 #define RK3366_LIT_WIN1_DSP_ST 0x000a8 981 #define RK3366_LIT_WIN1_COLOR_KEY 0x000ac 982 #define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc 983 #define RK3366_LIT_HWC_CTRL0 0x000e0 984 #define RK3366_LIT_HWC_CTRL1 0x000e4 985 #define RK3366_LIT_HWC_MST 0x000e8 986 #define RK3366_LIT_HWC_DSP_ST 0x000ec 987 #define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0 988 #define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100 989 #define RK3366_LIT_DSP_HACT_ST_END 0x00104 990 #define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108 991 #define RK3366_LIT_DSP_VACT_ST_END 0x0010c 992 #define RK3366_LIT_DSP_VS_ST_END_F1 0x00110 993 #define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114 994 #define RK3366_LIT_BCSH_CTRL 0x00160 995 #define RK3366_LIT_BCSH_COL_BAR 0x00164 996 #define RK3366_LIT_BCSH_BCS 0x00168 997 #define RK3366_LIT_BCSH_H 0x0016c 998 #define RK3366_LIT_FRC_LOWER01_0 0x00170 999 #define RK3366_LIT_FRC_LOWER01_1 0x00174 1000 #define RK3366_LIT_FRC_LOWER10_0 0x00178 1001 #define RK3366_LIT_FRC_LOWER10_1 0x0017c 1002 #define RK3366_LIT_FRC_LOWER11_0 0x00180 1003 #define RK3366_LIT_FRC_LOWER11_1 0x00184 1004 #define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c 1005 #define RK3366_LIT_DBG_REG_000 0x00190 1006 #define RK3366_LIT_BLANKING_VALUE 0x001f4 1007 #define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8 1008 #define RK3366_LIT_FLAG_REG 0x001fc 1009 #define RK3366_LIT_HWC_LUT_ADDR 0x00600 1010 #define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00 1011 /* rk3366 register definition end */ 1012 1013 /* rk3126 register definition */ 1014 #define RK3126_WIN1_MST 0x0004c 1015 #define RK3126_WIN1_DSP_INFO 0x00050 1016 #define RK3126_WIN1_DSP_ST 0x00054 1017 /* rk3126 register definition end */ 1018 1019 /* px30 register definition */ 1020 #define PX30_CABC_CTRL0 0x00200 1021 #define PX30_CABC_CTRL1 0x00204 1022 #define PX30_CABC_CTRL2 0x00208 1023 #define PX30_CABC_CTRL3 0x0020c 1024 #define PX30_CABC_GAUSS_LINE0_0 0x00210 1025 #define PX30_CABC_GAUSS_LINE0_1 0x00214 1026 #define PX30_CABC_GAUSS_LINE1_0 0x00218 1027 #define PX30_CABC_GAUSS_LINE1_1 0x0021c 1028 #define PX30_CABC_GAUSS_LINE2_0 0x00220 1029 #define PX30_CABC_GAUSS_LINE2_1 0x00224 1030 #define PX30_AFBCD0_CTRL 0x00240 1031 #define PX30_AFBCD0_HDR_PTR 0x00244 1032 #define PX30_AFBCD0_PIC_SIZE 0x00248 1033 #define PX30_AFBCD0_PIC_OFFSET 0x0024c 1034 #define PX30_AFBCD0_AXI_CTRL 0x00250 1035 #define PX30_GRF_PD_VO_CON1 0x00438 1036 /* px30 register definition end */ 1037 1038 #define RV1106_VENC_GRF_VOP_IO_WRAPPER 0x1000c 1039 1040 #define RV1126_GRF_IOFUNC_CON3 0x1026c 1041 1042 #define RK3562_GRF_IOC_VO_IO_CON 0x10500 1043 1044 /* rk3568 vop registers definition */ 1045 1046 #define RK3568_GRF_VO_CON1 0x0364 1047 /* System registers definition */ 1048 #define RK3568_REG_CFG_DONE 0x000 1049 #define RK3568_VOP2_WB_CFG_DONE BIT(14) 1050 #define RK3568_VOP2_GLB_CFG_DONE_EN BIT(15) 1051 #define RK3568_VERSION_INFO 0x004 1052 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 1053 #define RK3568_SYS_AXI_LUT_CTRL 0x024 1054 #define RK3568_DSP_IF_EN 0x028 1055 #define RK3568_DSP_IF_CTRL 0x02c 1056 #define RK3568_DSP_IF_POL 0x030 1057 #define RK3568_SYS_PD_CTRL 0x034 1058 #define RK3588_SYS_VAR_FREQ_CTRL 0x038 1059 #define RK3568_WB_CTRL 0x40 1060 #define RK3568_WB_XSCAL_FACTOR 0x44 1061 #define RK3568_WB_YRGB_MST 0x48 1062 #define RK3568_WB_CBR_MST 0x4C 1063 #define RK3568_OTP_WIN_EN 0x50 1064 #define RK3568_LUT_PORT_SEL 0x58 1065 #define RK3568_SYS_STATUS0 0x60 1066 #define RK3568_SYS_STATUS1 0x64 1067 #define RK3568_SYS_STATUS2 0x68 1068 #define RK3568_SYS_STATUS3 0x6C 1069 #define RK3568_VP0_LINE_FLAG 0x70 1070 #define RK3568_VP1_LINE_FLAG 0x74 1071 #define RK3568_VP2_LINE_FLAG 0x78 1072 #define RK3588_VP3_LINE_FLAG 0x7C 1073 #define RK3568_SYS0_INT_EN 0x80 1074 #define RK3568_SYS0_INT_CLR 0x84 1075 #define RK3568_SYS0_INT_STATUS 0x88 1076 #define RK3568_SYS1_INT_EN 0x90 1077 #define RK3568_SYS1_INT_CLR 0x94 1078 #define RK3568_SYS1_INT_STATUS 0x98 1079 #define RK3568_VP0_INT_EN 0xA0 1080 #define RK3568_VP0_INT_CLR 0xA4 1081 #define RK3568_VP0_INT_STATUS 0xA8 1082 #define RK3568_VP0_INT_RAW_STATUS 0xAC 1083 #define RK3568_VP1_INT_EN 0xB0 1084 #define RK3568_VP1_INT_CLR 0xB4 1085 #define RK3568_VP1_INT_STATUS 0xB8 1086 #define RK3568_VP1_INT_RAW_STATUS 0xBC 1087 #define RK3568_VP2_INT_EN 0xC0 1088 #define RK3568_VP2_INT_CLR 0xC4 1089 #define RK3568_VP2_INT_STATUS 0xC8 1090 #define RK3568_VP2_INT_RAW_STATUS 0xCC 1091 #define RK3588_VP3_INT_EN 0xD0 1092 #define RK3588_VP3_INT_CLR 0xD4 1093 #define RK3588_VP3_INT_STATUS 0xD8 1094 1095 #define RK3588_DSC_8K_SYS_CTRL 0x200 1096 #define RK3588_DSC_8K_RST 0x204 1097 #define RK3588_DSC_8K_CFG_DONE 0x208 1098 #define RK3588_DSC_8K_INIT_DLY 0x20C 1099 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210 1100 #define RK3588_DSC_8K_HACT_ST_END 0x214 1101 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218 1102 #define RK3588_DSC_8K_VACT_ST_END 0x21C 1103 #define RK3588_DSC_8K_STATUS 0x220 1104 #define RK3588_DSC_4K_SYS_CTRL 0x230 1105 #define RK3588_DSC_4K_RST 0x234 1106 #define RK3588_DSC_4K_CFG_DONE 0x238 1107 #define RK3588_DSC_4K_INIT_DLY 0x23C 1108 #define RK3588_DSC_4K_HTOTAL_HS_END 0x240 1109 #define RK3588_DSC_4K_HACT_ST_END 0x244 1110 #define RK3588_DSC_4K_VTOTAL_VS_END 0x248 1111 #define RK3588_DSC_4K_VACT_ST_END 0x24C 1112 #define RK3588_DSC_4K_STATUS 0x250 1113 1114 /* Video Port registers definition */ 1115 #define RK3568_VP0_DSP_CTRL 0xC00 1116 #define RK3568_VP0_DUAL_CHANNEL_CTRL 0xC04 1117 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 1118 #define RK3568_VP0_CLK_CTRL 0xC0C 1119 #define RK3568_VP0_3D_LUT_CTRL 0xC10 1120 #define RK3568_VP0_3D_LUT_MST 0xC20 1121 #define RK3568_VP0_DSP_BG 0xC2C 1122 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 1123 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 1124 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 1125 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 1126 #define RK3568_VP0_POST_SCL_CTRL 0xC40 1127 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 1128 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 1129 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 1130 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 1131 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 1132 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 1133 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 1134 #define RK3568_VP0_BCSH_CTRL 0xC60 1135 #define RK3568_VP0_BCSH_BCS 0xC64 1136 #define RK3568_VP0_BCSH_H 0xC68 1137 #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C 1138 #define RK3562_VP0_MCU_CTRL 0xCF8 1139 #define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC 1140 1141 #define RK3528_VP0_ACM_CTRL 0xCD0 1142 #define RK3528_VP0_CSC_COE01_02 0xCD4 1143 #define RK3528_VP0_CSC_COE10_11 0xCD8 1144 #define RK3528_VP0_CSC_COE12_20 0xCDC 1145 #define RK3528_VP0_CSC_COE21_22 0xCE0 1146 #define RK3528_VP0_CSC_OFFSET0 0xCE4 1147 #define RK3528_VP0_CSC_OFFSET1 0xCE8 1148 #define RK3528_VP0_CSC_OFFSET2 0xCEC 1149 #define RK3528_VP0_MCU_CTRL 0xCF8 1150 #define RK3528_VP0_MCU_RW_BYPASS_PORT 0xCFC 1151 1152 #define RK3568_VP1_DSP_CTRL 0xD00 1153 #define RK3568_VP1_DUAL_CHANNEL_CTRL 0xD04 1154 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 1155 #define RK3568_VP1_CLK_CTRL 0xD0C 1156 #define RK3588_VP1_3D_LUT_CTRL 0xD10 1157 #define RK3588_VP1_3D_LUT_MST 0xD20 1158 #define RK3568_VP1_DSP_BG 0xD2C 1159 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 1160 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 1161 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 1162 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 1163 #define RK3568_VP1_POST_SCL_CTRL 0xD40 1164 #define RK3568_VP1_DSP_HACT_INFO 0xD34 1165 #define RK3568_VP1_DSP_VACT_INFO 0xD38 1166 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 1167 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 1168 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 1169 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 1170 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 1171 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 1172 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 1173 #define RK3568_VP1_BCSH_CTRL 0xD60 1174 #define RK3568_VP1_BCSH_BCS 0xD64 1175 #define RK3568_VP1_BCSH_H 0xD68 1176 #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C 1177 #define RK3562_VP1_MCU_CTRL 0xDF8 1178 #define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC 1179 1180 #define RK3568_VP2_DSP_CTRL 0xE00 1181 #define RK3568_VP2_DUAL_CHANNEL_CTRL 0xE04 1182 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 1183 #define RK3568_VP2_CLK_CTRL 0xE0C 1184 #define RK3588_VP2_3D_LUT_CTRL 0xE10 1185 #define RK3588_VP2_3D_LUT_MST 0xE20 1186 #define RK3568_VP2_DSP_BG 0xE2C 1187 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 1188 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 1189 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 1190 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 1191 #define RK3568_VP2_POST_SCL_CTRL 0xE40 1192 #define RK3568_VP2_DSP_HACT_INFO 0xE34 1193 #define RK3568_VP2_DSP_VACT_INFO 0xE38 1194 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 1195 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 1196 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 1197 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 1198 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 1199 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 1200 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 1201 #define RK3568_VP2_BCSH_CTRL 0xE60 1202 #define RK3568_VP2_BCSH_BCS 0xE64 1203 #define RK3568_VP2_BCSH_H 0xE68 1204 #define RK3568_VP2_BCSH_COLOR_BAR 0xE6C 1205 1206 #define RK3588_VP3_DSP_CTRL 0xF00 1207 #define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04 1208 #define RK3588_VP3_COLOR_BAR_CTRL 0xF08 1209 #define RK3568_VP3_CLK_CTRL 0xF0C 1210 #define RK3588_VP3_DSP_BG 0xF2C 1211 #define RK3588_VP3_PRE_SCAN_HTIMING 0xF30 1212 #define RK3588_VP3_POST_DSP_HACT_INFO 0xF34 1213 #define RK3588_VP3_POST_DSP_VACT_INFO 0xF38 1214 #define RK3588_VP3_POST_SCL_FACTOR_YRGB 0xF3C 1215 #define RK3588_VP3_POST_SCL_CTRL 0xF40 1216 #define RK3588_VP3_DSP_HACT_INFO 0xF34 1217 #define RK3588_VP3_DSP_VACT_INFO 0xF38 1218 #define RK3588_VP3_POST_DSP_VACT_INFO_F1 0xF44 1219 #define RK3588_VP3_DSP_HTOTAL_HS_END 0xF48 1220 #define RK3588_VP3_DSP_HACT_ST_END 0xF4C 1221 #define RK3588_VP3_DSP_VTOTAL_VS_END 0xF50 1222 #define RK3588_VP3_DSP_VACT_ST_END 0xF54 1223 #define RK3588_VP3_DSP_VS_ST_END_F1 0xF58 1224 #define RK3588_VP3_DSP_VACT_ST_END_F1 0xF5C 1225 #define RK3588_VP3_BCSH_CTRL 0xF60 1226 #define RK3588_VP3_BCSH_BCS 0xF64 1227 #define RK3588_VP3_BCSH_H 0xF68 1228 #define RK3588_VP3_BCSH_COLOR_BAR 0xF6C 1229 #define RK3528_OVL_SYS 0x500 1230 #define RK3528_OVL_SYS_PORT_SEL_IMD 0x504 1231 #define RK3528_OVL_SYS_GATING_EN_IMD 0x508 1232 #define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510 1233 #define RK3528_OVL_SYS_ESMART0_CTRL 0x520 1234 #define RK3528_OVL_SYS_ESMART1_CTRL 0x524 1235 #define RK3528_OVL_SYS_ESMART2_CTRL 0x528 1236 #define RK3528_OVL_SYS_ESMART3_CTRL 0x52C 1237 #define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530 1238 #define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534 1239 #define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538 1240 #define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c 1241 #define RK3528_OVL_PORT0_CTRL 0x600 1242 #define RK3528_OVL_PORT0_LAYER_SEL 0x604 1243 #define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620 1244 #define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624 1245 #define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628 1246 #define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C 1247 #define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630 1248 #define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634 1249 #define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638 1250 #define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C 1251 #define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640 1252 #define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644 1253 #define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648 1254 #define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C 1255 #define RK3528_HDR_SRC_COLOR_CTRL 0x660 1256 #define RK3528_HDR_DST_COLOR_CTRL 0x664 1257 #define RK3528_HDR_SRC_ALPHA_CTRL 0x668 1258 #define RK3528_HDR_DST_ALPHA_CTRL 0x66C 1259 #define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670 1260 #define RK3528_OVL_PORT1_CTRL 0x700 1261 #define RK3528_OVL_PORT1_LAYER_SEL 0x704 1262 #define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720 1263 #define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724 1264 #define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728 1265 #define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C 1266 #define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730 1267 #define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734 1268 #define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738 1269 #define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C 1270 #define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740 1271 #define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744 1272 #define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748 1273 #define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C 1274 #define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770 1275 1276 /* Overlay registers definition */ 1277 #define RK3568_OVL_CTRL 0x600 1278 #define RK3568_OVL_LAYER_SEL 0x604 1279 #define RK3568_OVL_PORT_SEL 0x608 1280 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 1281 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 1282 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 1283 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 1284 #define RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL 0x620 1285 #define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL 0x624 1286 #define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x628 1287 #define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL 0x62C 1288 #define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL 0x630 1289 #define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL 0x634 1290 #define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL 0x638 1291 #define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL 0x63C 1292 #define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL 0x640 1293 #define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL 0x644 1294 #define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL 0x648 1295 #define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL 0x64C 1296 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 1297 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 1298 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 1299 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 1300 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 1301 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 1302 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 1303 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 1304 #define RK3568_HDR1_SRC_COLOR_CTRL 0x6D0 1305 #define RK3568_HDR1_DST_COLOR_CTRL 0x6D4 1306 #define RK3568_HDR1_SRC_ALPHA_CTRL 0x6D8 1307 #define RK3568_HDR1_DST_ALPHA_CTRL 0x6DC 1308 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 1309 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 1310 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 1311 #define RK3588_VP3_BG_MIX_CTRL 0x6EC 1312 #define RK3568_CLUSTER_DLY_NUM 0x6F0 1313 #define RK3568_CLUSTER_DLY_NUM1 0x6F4 1314 #define RK3568_SMART_DLY_NUM 0x6F8 1315 1316 /* Cluster0 register definition */ 1317 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 1318 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 1319 #define RK3528_CLUSTER0_WIN0_CTRL1 0x1004 1320 #define RK3528_CLUSTER0_WIN0_CTRL2 0x1008 1321 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 1322 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 1323 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 1324 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 1325 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 1326 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 1327 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 1328 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 1329 #define RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET 0x103C 1330 #define RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL 0x1050 1331 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 1332 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 1333 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 1334 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 1335 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 1336 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 1337 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 1338 1339 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 1340 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 1341 #define RK3528_CLUSTER0_WIN1_CTRL1 0x1084 1342 #define RK3528_CLUSTER0_WIN1_CTRL2 0x1088 1343 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 1344 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 1345 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 1346 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 1347 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 1348 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 1349 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 1350 #define RK3568_CLUSTER0_WIN1_AFBCD_OUTPUT_CTRL 0x10D0 1351 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 1352 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 1353 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 1354 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 1355 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 1356 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 1357 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 1358 1359 #define RK3568_CLUSTER0_CTRL 0x1100 1360 1361 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 1362 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 1363 #define RK3568_CLUSTER1_WIN0_CTRL2 0x1208 1364 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 1365 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 1366 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 1367 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 1368 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 1369 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 1370 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 1371 #define RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET 0x123C 1372 #define RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL 0x1250 1373 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 1374 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 1375 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 1376 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 1377 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 1378 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 1379 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 1380 1381 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 1382 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 1383 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 1384 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 1385 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 1386 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 1387 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 1388 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 1389 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 1390 #define RK3568_CLUSTER1_WIN1_AFBCD_OUTPUT_CTRL 0x12D0 1391 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 1392 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 1393 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 1394 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 1395 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 1396 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 1397 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 1398 1399 #define RK3568_CLUSTER1_CTRL 0x1300 1400 1401 #define RK3588_CLUSTER2_WIN0_CTRL0 0x1400 1402 #define RK3588_CLUSTER2_WIN0_CTRL1 0x1404 1403 #define RK3588_CLUSTER2_WIN0_CTRL2 0x1408 1404 #define RK3588_CLUSTER2_WIN0_YRGB_MST 0x1410 1405 #define RK3588_CLUSTER2_WIN0_CBR_MST 0x1414 1406 #define RK3588_CLUSTER2_WIN0_VIR 0x1418 1407 #define RK3588_CLUSTER2_WIN0_ACT_INFO 0x1420 1408 #define RK3588_CLUSTER2_WIN0_DSP_INFO 0x1424 1409 #define RK3588_CLUSTER2_WIN0_DSP_ST 0x1428 1410 #define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB 0x1430 1411 #define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET 0x143C 1412 #define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL 0x1450 1413 #define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE 0x1454 1414 #define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR 0x1458 1415 #define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH 0x145C 1416 #define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE 0x1460 1417 #define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET 0x1464 1418 #define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET 0x1468 1419 #define RK3588_CLUSTER2_WIN0_AFBCD_CTRL 0x146C 1420 1421 #define RK3588_CLUSTER2_WIN1_CTRL0 0x1480 1422 #define RK3588_CLUSTER2_WIN1_CTRL1 0x1484 1423 #define RK3588_CLUSTER2_WIN1_YRGB_MST 0x1490 1424 #define RK3588_CLUSTER2_WIN1_CBR_MST 0x1494 1425 #define RK3588_CLUSTER2_WIN1_VIR 0x1498 1426 #define RK3588_CLUSTER2_WIN1_ACT_INFO 0x14A0 1427 #define RK3588_CLUSTER2_WIN1_DSP_INFO 0x14A4 1428 #define RK3588_CLUSTER2_WIN1_DSP_ST 0x14A8 1429 #define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB 0x14B0 1430 #define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL 0x14D0 1431 #define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE 0x14D4 1432 #define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR 0x14D8 1433 #define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH 0x14DC 1434 #define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE 0x14E0 1435 #define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET 0x14E4 1436 #define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET 0x14E8 1437 #define RK3588_CLUSTER2_WIN1_AFBCD_CTRL 0x14EC 1438 1439 #define RK3588_CLUSTER2_CTRL 0x1500 1440 1441 #define RK3588_CLUSTER3_WIN0_CTRL0 0x1600 1442 #define RK3588_CLUSTER3_WIN0_CTRL1 0x1604 1443 #define RK3588_CLUSTER3_WIN0_CTRL2 0x1608 1444 #define RK3588_CLUSTER3_WIN0_YRGB_MST 0x1610 1445 #define RK3588_CLUSTER3_WIN0_CBR_MST 0x1614 1446 #define RK3588_CLUSTER3_WIN0_VIR 0x1618 1447 #define RK3588_CLUSTER3_WIN0_ACT_INFO 0x1620 1448 #define RK3588_CLUSTER3_WIN0_DSP_INFO 0x1624 1449 #define RK3588_CLUSTER3_WIN0_DSP_ST 0x1628 1450 #define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB 0x1630 1451 #define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET 0x163C 1452 #define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL 0x1650 1453 #define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE 0x1654 1454 #define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR 0x1658 1455 #define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH 0x165C 1456 #define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE 0x1660 1457 #define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET 0x1664 1458 #define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET 0x1668 1459 #define RK3588_CLUSTER3_WIN0_AFBCD_CTRL 0x166C 1460 1461 #define RK3588_CLUSTER3_WIN1_CTRL0 0x1680 1462 #define RK3588_CLUSTER3_WIN1_CTRL1 0x1684 1463 #define RK3588_CLUSTER3_WIN1_YRGB_MST 0x1690 1464 #define RK3588_CLUSTER3_WIN1_CBR_MST 0x1694 1465 #define RK3588_CLUSTER3_WIN1_VIR 0x1698 1466 #define RK3588_CLUSTER3_WIN1_ACT_INFO 0x16A0 1467 #define RK3588_CLUSTER3_WIN1_DSP_INFO 0x16A4 1468 #define RK3588_CLUSTER3_WIN1_DSP_ST 0x16A8 1469 #define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB 0x16B0 1470 #define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL 0x16D0 1471 #define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE 0x16D4 1472 #define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR 0x16D8 1473 #define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH 0x16DC 1474 #define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE 0x16E0 1475 #define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET 0x16E4 1476 #define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET 0x16E8 1477 #define RK3588_CLUSTER3_WIN1_AFBCD_CTRL 0x16EC 1478 1479 #define RK3588_CLUSTER3_CTRL 0x1700 1480 1481 /* Esmart register definition */ 1482 #define RK3568_ESMART0_CTRL0 0x1800 1483 #define RK3568_ESMART0_CTRL1 0x1804 1484 #define RK3568_ESMART0_AXI_CTRL 0x1808 1485 #define RK3568_ESMART0_REGION0_CTRL 0x1810 1486 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 1487 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 1488 #define RK3568_ESMART0_REGION0_VIR 0x181C 1489 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 1490 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 1491 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 1492 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 1493 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 1494 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 1495 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 1496 #define RK3568_ESMART0_REGION1_CTRL 0x1840 1497 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 1498 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 1499 #define RK3568_ESMART0_REGION1_VIR 0x184C 1500 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 1501 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 1502 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 1503 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 1504 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 1505 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 1506 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 1507 #define RK3568_ESMART0_REGION2_CTRL 0x1870 1508 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 1509 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 1510 #define RK3568_ESMART0_REGION2_VIR 0x187C 1511 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 1512 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 1513 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 1514 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 1515 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 1516 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 1517 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 1518 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 1519 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 1520 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 1521 #define RK3568_ESMART0_REGION3_VIR 0x18AC 1522 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 1523 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 1524 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 1525 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 1526 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 1527 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 1528 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 1529 #define RK3568_ESMART0_COLOR_KEY_CTRL 0x18D0 1530 1531 #define RK3568_ESMART1_CTRL0 0x1A00 1532 #define RK3568_ESMART1_CTRL1 0x1A04 1533 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 1534 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 1535 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 1536 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 1537 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 1538 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 1539 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 1540 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 1541 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 1542 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 1543 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 1544 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 1545 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 1546 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 1547 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 1548 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 1549 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 1550 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 1551 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 1552 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 1553 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 1554 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 1555 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 1556 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 1557 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 1558 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 1559 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 1560 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 1561 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 1562 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 1563 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 1564 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 1565 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 1566 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 1567 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 1568 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 1569 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 1570 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 1571 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 1572 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 1573 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 1574 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 1575 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 1576 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 1577 1578 #define RK3568_SMART0_CTRL0 0x1C00 1579 #define RK3568_SMART0_CTRL1 0x1C04 1580 #define RK3568_SMART0_REGION0_CTRL 0x1C10 1581 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 1582 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 1583 #define RK3568_SMART0_REGION0_VIR 0x1C1C 1584 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 1585 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 1586 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 1587 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 1588 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 1589 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 1590 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 1591 #define RK3568_SMART0_REGION1_CTRL 0x1C40 1592 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 1593 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 1594 #define RK3568_SMART0_REGION1_VIR 0x1C4C 1595 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 1596 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 1597 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 1598 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 1599 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 1600 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 1601 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 1602 #define RK3568_SMART0_REGION2_CTRL 0x1C70 1603 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 1604 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 1605 #define RK3568_SMART0_REGION2_VIR 0x1C7C 1606 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 1607 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 1608 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 1609 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 1610 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 1611 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 1612 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 1613 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 1614 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 1615 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 1616 #define RK3568_SMART0_REGION3_VIR 0x1CAC 1617 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 1618 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 1619 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 1620 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 1621 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 1622 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 1623 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 1624 1625 #define RK3568_SMART1_CTRL0 0x1E00 1626 #define RK3568_SMART1_CTRL1 0x1E04 1627 #define RK3568_SMART1_REGION0_CTRL 0x1E10 1628 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 1629 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 1630 #define RK3568_SMART1_REGION0_VIR 0x1E1C 1631 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 1632 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 1633 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 1634 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 1635 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 1636 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 1637 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 1638 #define RK3568_SMART1_REGION1_CTRL 0x1E40 1639 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 1640 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 1641 #define RK3568_SMART1_REGION1_VIR 0x1E4C 1642 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 1643 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 1644 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 1645 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 1646 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 1647 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 1648 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 1649 #define RK3568_SMART1_REGION2_CTRL 0x1E70 1650 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 1651 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 1652 #define RK3568_SMART1_REGION2_VIR 0x1E7C 1653 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 1654 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 1655 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 1656 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 1657 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 1658 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 1659 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 1660 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 1661 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 1662 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 1663 #define RK3568_SMART1_REGION3_VIR 0x1EAC 1664 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 1665 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 1666 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 1667 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 1668 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 1669 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 1670 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 1671 1672 /* HDR register definition */ 1673 #define RK3568_HDR_LUT_CTRL 0x2000 1674 #define RK3568_HDR_LUT_MST 0x2004 1675 #define RK3568_SDR2HDR_CTRL 0x2010 1676 /* for HDR10 controller1 */ 1677 #define RK3568_SDR2HDR_CTRL1 0x2018 1678 #define RK3568_HDR2SDR_CTRL1 0x201C 1679 #define RK3568_HDR2SDR_CTRL 0x2020 1680 #define RK3568_HDR2SDR_SRC_RANGE 0x2024 1681 #define RK3568_HDR2SDR_NORMFACEETF 0x2028 1682 #define RK3568_HDR2SDR_DST_RANGE 0x202C 1683 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 1684 #define RK3568_HDR_EETF_OETF_Y0 0x203C 1685 #define RK3568_HDR_SAT_Y0 0x20C0 1686 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 1687 #define RK3568_HDR_OETF_DX_POW1 0x2200 1688 #define RK3568_HDR_OETF_XN1 0x2300 1689 1690 /* DSC register definition */ 1691 #define RK3588_DSC_8K_PPS0_3 0x4000 1692 #define RK3588_DSC_8K_CTRL0 0x40A0 1693 #define RK3588_DSC_8K_CTRL1 0x40A4 1694 #define RK3588_DSC_8K_STS0 0x40A8 1695 #define RK3588_DSC_8K_ERS 0x40C4 1696 1697 #define RK3588_DSC_4K_PPS0_3 0x4100 1698 #define RK3588_DSC_4K_CTRL0 0x41A0 1699 #define RK3588_DSC_4K_CTRL1 0x41A4 1700 #define RK3588_DSC_4K_STS0 0x41A8 1701 #define RK3588_DSC_4K_ERS 0x41C4 1702 1703 #define RK3588_GRF_SOC_CON1 0x0304 1704 #define RK3588_GRF_VOP_CON2 0x08 1705 #define RK3588_GRF_VO1_CON0 0x00 1706 1707 1708 #define RK3588_PMU_PWR_GATE_CON1 0x150 1709 #define RK3588_PMU_SUBMEM_PWR_GATE_CON1 0x1B4 1710 #define RK3588_PMU_SUBMEM_PWR_GATE_CON2 0x1B8 1711 #define RK3588_PMU_SUBMEM_PWR_GATE_STATUS 0x1BC 1712 #define RK3588_PMU_BISR_CON3 0x20C 1713 #define RK3588_PMU_BISR_STATUS5 0x294 1714 1715 /* RK3528 HDR register definition */ 1716 #define RK3528_HDR_LUT_CTRL 0x2000 1717 #define RK3528_HDR_LUT_MST 0x2004 1718 #define RK3528_HDR_LUT_STATUS 0x2008 1719 #define RK3528_SDR2HDR_CTRL 0x2010 1720 #define RK3528_SDR_CFG_COE0 0x2014 1721 #define RK3528_SDR_CFG_COE1 0x2018 1722 #define RK3528_SDR_CSC_COE00_01 0x201C 1723 #define RK3528_SDR_CSC_COE02_10 0x2020 1724 #define RK3528_SDR_CSC_COE11_12 0x2024 1725 #define RK3528_SDR_CSC_COE20_21 0x2028 1726 #define RK3528_SDR_CSC_COE22 0x202C 1727 #define RK3528_HDRVIVID_CTRL 0x2040 1728 #define RK3528_HDR_PQ_GAMMA 0x2044 1729 #define RK3528_HLG_RFIX_SCALEFAC 0x2048 1730 #define RK3528_HLG_MAXLUMA 0x204C 1731 #define RK3528_HLG_R_TM_LIN2NON 0x2050 1732 #define RK3528_HDR_CSC_COE00_01 0x2054 1733 #define RK3528_HDR_CSC_COE02_10 0x2058 1734 #define RK3528_HDR_CSC_COE11_12 0x205C 1735 #define RK3528_HDR_CSC_COE20_21 0x2060 1736 #define RK3528_HDR_CSC_COE22 0x2064 1737 #define RK3528_INK_CFG 0x2080 1738 #define RK3528_INK_POINT0_CFG 0x2084 1739 #define RK3528_INK_POINT1_CFG 0x2088 1740 #define RK3528_INK_POINT0_R0 0x208C 1741 #define RK3528_INK_POINT0_G0 0x2090 1742 #define RK3528_INK_POINT0_B0 0x2094 1743 #define RK3528_INK_POINT0_R1 0x2098 1744 #define RK3528_INK_POINT0_G1 0x209C 1745 #define RK3528_INK_POINT0_B1 0x20A0 1746 #define RK3528_INK_POINT1_R0 0x20A4 1747 #define RK3528_INK_POINT1_G0 0x20A8 1748 #define RK3528_INK_POINT1_B0 0x20AC 1749 #define RK3528_INK_POINT1_R1 0x20B0 1750 #define RK3528_INK_POINT1_G1 0x20B4 1751 #define RK3528_INK_POINT1_B1 0x20B8 1752 #define RK3528_HDR_TONE_SCA 0x213C 1753 #define RK3528_HDRGAMMA_CURVE 0x2540 1754 #define RK3528_HDRGAMMA_MDFVALUE 0x2690 1755 #define RK3528_SDRINVGAMMA_CURVE 0x2700 1756 #define RK3528_SDRINVGAMMA_STARTIDX 0x2820 1757 #define RK3528_SDRINVGAMMA_CHANGEIDX 0x2840 1758 #define RK3528_SDR_SMGAIN 0x2900 1759 1760 /* RK3588 ACM register definition */ 1761 #define RK3528_ACM_CTRL 0x0000 1762 #define RK3528_ACM_ENABLE BIT(0) 1763 #define RK3528_ACM_BYPASS BIT(1) 1764 #define RK3528_ACM_DELTA_RANGE 0x0004 1765 #define RK3528_ACM_FETCH_START 0x0008 1766 #define RK3528_ACM_DEBUG_POINT0 0x0010 1767 #define RK3528_ACM_DEBUG_POINT1 0x0014 1768 #define RK3528_ACM_DEBUG_POINT2 0x0018 1769 #define RK3528_ACM_DEBUG_POINT3 0x001c 1770 #define RK3528_ACM_FETCH_DONE 0x0020 1771 #define RK3528_ACM_DEBUG0_DATA0 0x0030 1772 #define RK3528_ACM_DEBUG0_DATA1 0x0034 1773 #define RK3528_ACM_DEBUG0_DATA2 0x0038 1774 #define RK3528_ACM_DEBUG0_DATA3 0x003c 1775 #define RK3528_ACM_DEBUG1_DATA0 0x0040 1776 #define RK3528_ACM_DEBUG1_DATA1 0x0044 1777 #define RK3528_ACM_DEBUG1_DATA2 0x0048 1778 #define RK3528_ACM_DEBUG1_DATA3 0x004c 1779 #define RK3528_ACM_DEBUG2_DATA0 0x0050 1780 #define RK3528_ACM_DEBUG2_DATA1 0x0054 1781 #define RK3528_ACM_DEBUG2_DATA2 0x0058 1782 #define RK3528_ACM_DEBUG2_DATA3 0x005c 1783 #define RK3528_ACM_DEBUG3_DATA0 0x0060 1784 #define RK3528_ACM_DEBUG3_DATA1 0x0064 1785 #define RK3528_ACM_DEBUG3_DATA2 0x0068 1786 #define RK3528_ACM_DEBUG3_DATA3 0x006c 1787 #define RK3528_ACM_YHS_DEL_HY_SEG0 0x0100 1788 #define RK3528_ACM_YHS_DEL_HY_SEG152 0x0360 1789 #define RK3528_ACM_YHS_DEL_HS_SEG0 0x0364 1790 #define RK3528_ACM_YHS_DEL_HS_SEG220 0x06d4 1791 #define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x06d8 1792 #define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x07d8 1793 #endif /* _ROCKCHIP_VOP_REG_H */ 1794