xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/hi556.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * hi556 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * V0.0X01.0X00 init version
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/pm_runtime.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_graph.h>
19*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
20*4882a593Smuzhiyun #include <linux/sysfs.h>
21*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
22*4882a593Smuzhiyun #include <linux/version.h>
23*4882a593Smuzhiyun #include <media/v4l2-async.h>
24*4882a593Smuzhiyun #include <media/media-entity.h>
25*4882a593Smuzhiyun #include <media/v4l2-common.h>
26*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
27*4882a593Smuzhiyun #include <media/v4l2-device.h>
28*4882a593Smuzhiyun #include <media/v4l2-event.h>
29*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
30*4882a593Smuzhiyun #include <media/v4l2-image-sizes.h>
31*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
32*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
33*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* verify default register values */
36*4882a593Smuzhiyun //#define CHECK_REG_VALUE
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x00)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
41*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
45*4882a593Smuzhiyun #define MIPI_FREQ	440000000U
46*4882a593Smuzhiyun #define HI556_PIXEL_RATE		(440000000LL * 2LL * 2LL / 10)
47*4882a593Smuzhiyun #define HI556_XVCLK_FREQ		24000000
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define CHIP_ID				0x0556
50*4882a593Smuzhiyun #define HI556_REG_CHIP_ID		0x0f16
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define HI556_REG_CTRL_MODE		0x0A00
53*4882a593Smuzhiyun #define HI556_MODE_SW_STANDBY		0x00
54*4882a593Smuzhiyun #define HI556_MODE_STREAMING		0x01
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define HI556_REG_EXPOSURE_H		0x0073
57*4882a593Smuzhiyun #define HI556_REG_EXPOSURE_M		0x0074
58*4882a593Smuzhiyun #define HI556_REG_EXPOSURE_L		0x0075
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define HI556_FETCH_HIGH_BYTE_EXP(VAL)	(((VAL) >> 16) & 0xF)	/* 4 Bits */
61*4882a593Smuzhiyun #define HI556_FETCH_MIDDLE_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF)	/* 8 Bits */
62*4882a593Smuzhiyun #define HI556_FETCH_LOW_BYTE_EXP(VAL)	((VAL) & 0xFF)	/* 8 Bits */
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define	HI556_EXPOSURE_MIN		4
65*4882a593Smuzhiyun #define	HI556_EXPOSURE_STEP		1
66*4882a593Smuzhiyun #define HI556_VTS_MAX			0x7fff
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define HI556_REG_GAIN			0x0077
69*4882a593Smuzhiyun #define HI556_GAIN_MASK			0xff
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define	ANALOG_GAIN_MIN			0x00
72*4882a593Smuzhiyun #define	ANALOG_GAIN_MAX			0xF0
73*4882a593Smuzhiyun #define	ANALOG_GAIN_STEP		1
74*4882a593Smuzhiyun #define	ANALOG_GAIN_DEFAULT		0x10
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define HI556_REG_GROUP	0x0046
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define HI556_REG_TEST_PATTERN		0x0A05
79*4882a593Smuzhiyun #define	HI556_TEST_PATTERN_ENABLE	0x01
80*4882a593Smuzhiyun #define	HI556_TEST_PATTERN_DISABLE	0x0
81*4882a593Smuzhiyun #define HI556_REG_TEST_PATTERN_SELECT	0x0201
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define HI556_REG_VTS			0x0006
84*4882a593Smuzhiyun #define HI556_FLIP_MIRROR_REG	0x000e
85*4882a593Smuzhiyun #define HI556_FETCH_MIRROR(VAL, ENABLE)	(ENABLE ? VAL | 0x01 : VAL & 0xfe)
86*4882a593Smuzhiyun #define HI556_FETCH_FLIP(VAL, ENABLE)	(ENABLE ? VAL | 0x02 : VAL & 0xfd)
87*4882a593Smuzhiyun #define REG_NULL			0xFFFF
88*4882a593Smuzhiyun #define DELAY_MS			0xEEEE	/* Array delay token */
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define HI556_REG_VALUE_08BIT		1
91*4882a593Smuzhiyun #define HI556_REG_VALUE_16BIT		2
92*4882a593Smuzhiyun #define HI556_REG_VALUE_24BIT		3
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define HI556_LANES			2
95*4882a593Smuzhiyun #define HI556_BITS_PER_SAMPLE		10
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT	"rockchip,camera_default"
98*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP	"rockchip,camera_sleep"
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define HI556_NAME			"hi556"
101*4882a593Smuzhiyun #define HI556_MEDIA_BUS_FMT		MEDIA_BUS_FMT_SGBRG10_1X10
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun struct hi556_otp_info {
104*4882a593Smuzhiyun 	int flag; // bit[7]: info, bit[6]:wb
105*4882a593Smuzhiyun 	int module_id;
106*4882a593Smuzhiyun 	int lens_id;
107*4882a593Smuzhiyun 	int year;
108*4882a593Smuzhiyun 	int month;
109*4882a593Smuzhiyun 	int day;
110*4882a593Smuzhiyun 	int rg_ratio;
111*4882a593Smuzhiyun 	int bg_ratio;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const char * const hi556_supply_names[] = {
115*4882a593Smuzhiyun 	"avdd",		/* Analog power */
116*4882a593Smuzhiyun 	"dovdd",	/* Digital I/O power */
117*4882a593Smuzhiyun 	"dvdd",		/* Digital core power */
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define HI556_NUM_SUPPLIES ARRAY_SIZE(hi556_supply_names)
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct regval {
123*4882a593Smuzhiyun 	u16 addr;
124*4882a593Smuzhiyun 	u16 val;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun struct hi556_mode {
128*4882a593Smuzhiyun 	u32 width;
129*4882a593Smuzhiyun 	u32 height;
130*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
131*4882a593Smuzhiyun 	u32 hts_def;
132*4882a593Smuzhiyun 	u32 vts_def;
133*4882a593Smuzhiyun 	u32 exp_def;
134*4882a593Smuzhiyun 	const struct regval *reg_list;
135*4882a593Smuzhiyun 	u32 hdr_mode;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun struct hi556 {
139*4882a593Smuzhiyun 	struct i2c_client	*client;
140*4882a593Smuzhiyun 	struct clk		*xvclk;
141*4882a593Smuzhiyun 	struct gpio_desc	*power_gpio;
142*4882a593Smuzhiyun 	struct gpio_desc	*reset_gpio;
143*4882a593Smuzhiyun 	struct gpio_desc	*pwdn_gpio;
144*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[HI556_NUM_SUPPLIES];
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	struct pinctrl		*pinctrl;
147*4882a593Smuzhiyun 	struct pinctrl_state	*pins_default;
148*4882a593Smuzhiyun 	struct pinctrl_state	*pins_sleep;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	struct v4l2_subdev	subdev;
151*4882a593Smuzhiyun 	struct media_pad	pad;
152*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
153*4882a593Smuzhiyun 	struct v4l2_ctrl	*exposure;
154*4882a593Smuzhiyun 	struct v4l2_ctrl	*anal_gain;
155*4882a593Smuzhiyun 	struct v4l2_ctrl	*digi_gain;
156*4882a593Smuzhiyun 	struct v4l2_ctrl	*hblank;
157*4882a593Smuzhiyun 	struct v4l2_ctrl	*vblank;
158*4882a593Smuzhiyun 	struct v4l2_ctrl	*test_pattern;
159*4882a593Smuzhiyun 	struct mutex		mutex;
160*4882a593Smuzhiyun 	bool			streaming;
161*4882a593Smuzhiyun 	bool			power_on;
162*4882a593Smuzhiyun 	const struct hi556_mode *cur_mode;
163*4882a593Smuzhiyun 	unsigned int lane_num;
164*4882a593Smuzhiyun 	unsigned int cfg_num;
165*4882a593Smuzhiyun 	unsigned int pixel_rate;
166*4882a593Smuzhiyun 	u32			module_index;
167*4882a593Smuzhiyun 	struct hi556_otp_info *otp;
168*4882a593Smuzhiyun 	const char		*module_facing;
169*4882a593Smuzhiyun 	const char		*module_name;
170*4882a593Smuzhiyun 	const char		*len_name;
171*4882a593Smuzhiyun 	struct rkmodule_awb_cfg	awb_cfg;
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define to_hi556(sd) container_of(sd, struct hi556, subdev)
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun  * Xclk 24Mhz
178*4882a593Smuzhiyun  * Pclk 176Mhz
179*4882a593Smuzhiyun  * linelength 2816(0xb00)
180*4882a593Smuzhiyun  * framelength 1988(0x7c0)
181*4882a593Smuzhiyun  * grabwindow_width 2592
182*4882a593Smuzhiyun  * grabwindow_height 1944
183*4882a593Smuzhiyun  * max_framerate 30fps
184*4882a593Smuzhiyun  * MIPI speed(Mbps) : 840Mbps x 2Lane
185*4882a593Smuzhiyun  */
186*4882a593Smuzhiyun static const struct regval hi556_global_regs[] = {
187*4882a593Smuzhiyun 	{0x0a00, 0x0000},
188*4882a593Smuzhiyun 	{0x0e00, 0x0102},
189*4882a593Smuzhiyun 	{0x0e02, 0x0102},
190*4882a593Smuzhiyun 	{0x0e0c, 0x0100},
191*4882a593Smuzhiyun 	{0x2000, 0x7400},
192*4882a593Smuzhiyun 	{0x2002, 0x001c},
193*4882a593Smuzhiyun 	{0x2004, 0x0242},
194*4882a593Smuzhiyun 	{0x2006, 0x0942},
195*4882a593Smuzhiyun 	{0x2008, 0x7007},
196*4882a593Smuzhiyun 	{0x200a, 0x0fd9},
197*4882a593Smuzhiyun 	{0x200c, 0x0259},
198*4882a593Smuzhiyun 	{0x200e, 0x7008},
199*4882a593Smuzhiyun 	{0x2010, 0x160e},
200*4882a593Smuzhiyun 	{0x2012, 0x0047},
201*4882a593Smuzhiyun 	{0x2014, 0x2118},
202*4882a593Smuzhiyun 	{0x2016, 0x0041},
203*4882a593Smuzhiyun 	{0x2018, 0x00d8},
204*4882a593Smuzhiyun 	{0x201a, 0x0145},
205*4882a593Smuzhiyun 	{0x201c, 0x0006},
206*4882a593Smuzhiyun 	{0x201e, 0x0181},
207*4882a593Smuzhiyun 	{0x2020, 0x13cc},
208*4882a593Smuzhiyun 	{0x2022, 0x2057},
209*4882a593Smuzhiyun 	{0x2024, 0x7001},
210*4882a593Smuzhiyun 	{0x2026, 0x0fca},
211*4882a593Smuzhiyun 	{0x2028, 0x00cb},
212*4882a593Smuzhiyun 	{0x202a, 0x009f},
213*4882a593Smuzhiyun 	{0x202c, 0x7002},
214*4882a593Smuzhiyun 	{0x202e, 0x13cc},
215*4882a593Smuzhiyun 	{0x2030, 0x019b},
216*4882a593Smuzhiyun 	{0x2032, 0x014d},
217*4882a593Smuzhiyun 	{0x2034, 0x2987},
218*4882a593Smuzhiyun 	{0x2036, 0x2766},
219*4882a593Smuzhiyun 	{0x2038, 0x0020},
220*4882a593Smuzhiyun 	{0x203a, 0x2060},
221*4882a593Smuzhiyun 	{0x203c, 0x0e5d},
222*4882a593Smuzhiyun 	{0x203e, 0x181d},
223*4882a593Smuzhiyun 	{0x2040, 0x2066},
224*4882a593Smuzhiyun 	{0x2042, 0x20c4},
225*4882a593Smuzhiyun 	{0x2044, 0x5000},
226*4882a593Smuzhiyun 	{0x2046, 0x0005},
227*4882a593Smuzhiyun 	{0x2048, 0x0000},
228*4882a593Smuzhiyun 	{0x204a, 0x01db},
229*4882a593Smuzhiyun 	{0x204c, 0x025a},
230*4882a593Smuzhiyun 	{0x204e, 0x00c0},
231*4882a593Smuzhiyun 	{0x2050, 0x0005},
232*4882a593Smuzhiyun 	{0x2052, 0x0006},
233*4882a593Smuzhiyun 	{0x2054, 0x0ad9},
234*4882a593Smuzhiyun 	{0x2056, 0x0259},
235*4882a593Smuzhiyun 	{0x2058, 0x0618},
236*4882a593Smuzhiyun 	{0x205a, 0x0258},
237*4882a593Smuzhiyun 	{0x205c, 0x2266},
238*4882a593Smuzhiyun 	{0x205e, 0x20c8},
239*4882a593Smuzhiyun 	{0x2060, 0x2060},
240*4882a593Smuzhiyun 	{0x2062, 0x707b},
241*4882a593Smuzhiyun 	{0x2064, 0x0fdd},
242*4882a593Smuzhiyun 	{0x2066, 0x81b8},
243*4882a593Smuzhiyun 	{0x2068, 0x5040},
244*4882a593Smuzhiyun 	{0x206a, 0x0020},
245*4882a593Smuzhiyun 	{0x206c, 0x5060},
246*4882a593Smuzhiyun 	{0x206e, 0x3143},
247*4882a593Smuzhiyun 	{0x2070, 0x5081},
248*4882a593Smuzhiyun 	{0x2072, 0x025c},
249*4882a593Smuzhiyun 	{0x2074, 0x7800},
250*4882a593Smuzhiyun 	{0x2076, 0x7400},
251*4882a593Smuzhiyun 	{0x2078, 0x001c},
252*4882a593Smuzhiyun 	{0x207a, 0x0242},
253*4882a593Smuzhiyun 	{0x207c, 0x0942},
254*4882a593Smuzhiyun 	{0x207e, 0x0bd9},
255*4882a593Smuzhiyun 	{0x2080, 0x0259},
256*4882a593Smuzhiyun 	{0x2082, 0x7008},
257*4882a593Smuzhiyun 	{0x2084, 0x160e},
258*4882a593Smuzhiyun 	{0x2086, 0x0047},
259*4882a593Smuzhiyun 	{0x2088, 0x2118},
260*4882a593Smuzhiyun 	{0x208a, 0x0041},
261*4882a593Smuzhiyun 	{0x208c, 0x00d8},
262*4882a593Smuzhiyun 	{0x208e, 0x0145},
263*4882a593Smuzhiyun 	{0x2090, 0x0006},
264*4882a593Smuzhiyun 	{0x2092, 0x0181},
265*4882a593Smuzhiyun 	{0x2094, 0x13cc},
266*4882a593Smuzhiyun 	{0x2096, 0x2057},
267*4882a593Smuzhiyun 	{0x2098, 0x7001},
268*4882a593Smuzhiyun 	{0x209a, 0x0fca},
269*4882a593Smuzhiyun 	{0x209c, 0x00cb},
270*4882a593Smuzhiyun 	{0x209e, 0x009f},
271*4882a593Smuzhiyun 	{0x20a0, 0x7002},
272*4882a593Smuzhiyun 	{0x20a2, 0x13cc},
273*4882a593Smuzhiyun 	{0x20a4, 0x019b},
274*4882a593Smuzhiyun 	{0x20a6, 0x014d},
275*4882a593Smuzhiyun 	{0x20a8, 0x2987},
276*4882a593Smuzhiyun 	{0x20aa, 0x2766},
277*4882a593Smuzhiyun 	{0x20ac, 0x0020},
278*4882a593Smuzhiyun 	{0x20ae, 0x2060},
279*4882a593Smuzhiyun 	{0x20b0, 0x0e5d},
280*4882a593Smuzhiyun 	{0x20b2, 0x181d},
281*4882a593Smuzhiyun 	{0x20b4, 0x2066},
282*4882a593Smuzhiyun 	{0x20b6, 0x20c4},
283*4882a593Smuzhiyun 	{0x20b8, 0x50a0},
284*4882a593Smuzhiyun 	{0x20ba, 0x0005},
285*4882a593Smuzhiyun 	{0x20bc, 0x0000},
286*4882a593Smuzhiyun 	{0x20be, 0x01db},
287*4882a593Smuzhiyun 	{0x20c0, 0x025a},
288*4882a593Smuzhiyun 	{0x20c2, 0x00c0},
289*4882a593Smuzhiyun 	{0x20c4, 0x0005},
290*4882a593Smuzhiyun 	{0x20c6, 0x0006},
291*4882a593Smuzhiyun 	{0x20c8, 0x0ad9},
292*4882a593Smuzhiyun 	{0x20ca, 0x0259},
293*4882a593Smuzhiyun 	{0x20cc, 0x0618},
294*4882a593Smuzhiyun 	{0x20ce, 0x0258},
295*4882a593Smuzhiyun 	{0x20d0, 0x2266},
296*4882a593Smuzhiyun 	{0x20d2, 0x20c8},
297*4882a593Smuzhiyun 	{0x20d4, 0x2060},
298*4882a593Smuzhiyun 	{0x20d6, 0x707b},
299*4882a593Smuzhiyun 	{0x20d8, 0x0fdd},
300*4882a593Smuzhiyun 	{0x20da, 0x86b8},
301*4882a593Smuzhiyun 	{0x20dc, 0x50e0},
302*4882a593Smuzhiyun 	{0x20de, 0x0020},
303*4882a593Smuzhiyun 	{0x20e0, 0x5100},
304*4882a593Smuzhiyun 	{0x20e2, 0x3143},
305*4882a593Smuzhiyun 	{0x20e4, 0x5121},
306*4882a593Smuzhiyun 	{0x20e6, 0x7800},
307*4882a593Smuzhiyun 	{0x20e8, 0x3140},
308*4882a593Smuzhiyun 	{0x20ea, 0x01c4},
309*4882a593Smuzhiyun 	{0x20ec, 0x01c1},
310*4882a593Smuzhiyun 	{0x20ee, 0x01c0},
311*4882a593Smuzhiyun 	{0x20f0, 0x01c4},
312*4882a593Smuzhiyun 	{0x20f2, 0x2700},
313*4882a593Smuzhiyun 	{0x20f4, 0x3d40},
314*4882a593Smuzhiyun 	{0x20f6, 0x7800},
315*4882a593Smuzhiyun 	{0x20f8, 0xffff},
316*4882a593Smuzhiyun 	{0x27fe, 0xe000},
317*4882a593Smuzhiyun 	{0x3000, 0x60f8},
318*4882a593Smuzhiyun 	{0x3002, 0x187f},
319*4882a593Smuzhiyun 	{0x3004, 0x7060},
320*4882a593Smuzhiyun 	{0x3006, 0x0114},
321*4882a593Smuzhiyun 	{0x3008, 0x60b0},
322*4882a593Smuzhiyun 	{0x300a, 0x1473},
323*4882a593Smuzhiyun 	{0x300c, 0x0013},
324*4882a593Smuzhiyun 	{0x300e, 0x140f},
325*4882a593Smuzhiyun 	{0x3010, 0x0040},
326*4882a593Smuzhiyun 	{0x3012, 0x100f},
327*4882a593Smuzhiyun 	{0x3014, 0x60f8},
328*4882a593Smuzhiyun 	{0x3016, 0x187f},
329*4882a593Smuzhiyun 	{0x3018, 0x7060},
330*4882a593Smuzhiyun 	{0x301a, 0x0114},
331*4882a593Smuzhiyun 	{0x301c, 0x60b0},
332*4882a593Smuzhiyun 	{0x301e, 0x1473},
333*4882a593Smuzhiyun 	{0x3020, 0x0013},
334*4882a593Smuzhiyun 	{0x3022, 0x140f},
335*4882a593Smuzhiyun 	{0x3024, 0x0040},
336*4882a593Smuzhiyun 	{0x3026, 0x000f},
337*4882a593Smuzhiyun 	{0x0b00, 0x0000},
338*4882a593Smuzhiyun 	{0x0b02, 0x0045},
339*4882a593Smuzhiyun 	{0x0b04, 0xb405},
340*4882a593Smuzhiyun 	{0x0b06, 0xc403},
341*4882a593Smuzhiyun 	{0x0b08, 0x0081},
342*4882a593Smuzhiyun 	{0x0b0a, 0x8252},
343*4882a593Smuzhiyun 	{0x0b0c, 0xf814},
344*4882a593Smuzhiyun 	{0x0b0e, 0xc618},
345*4882a593Smuzhiyun 	{0x0b10, 0xa828},
346*4882a593Smuzhiyun 	{0x0b12, 0x004c},
347*4882a593Smuzhiyun 	{0x0b14, 0x4068},
348*4882a593Smuzhiyun 	{0x0b16, 0x0000},
349*4882a593Smuzhiyun 	{0x0f30, 0x6e25},
350*4882a593Smuzhiyun 	{0x0f32, 0x7067},
351*4882a593Smuzhiyun 	{0x0954, 0x0009},
352*4882a593Smuzhiyun 	{0x0956, 0x1100},
353*4882a593Smuzhiyun 	{0x0958, 0xcc80},
354*4882a593Smuzhiyun 	{0x095a, 0x0000},
355*4882a593Smuzhiyun 	{0x0c00, 0x1110},
356*4882a593Smuzhiyun 	{0x0c02, 0x0011},
357*4882a593Smuzhiyun 	{0x0c04, 0x0000},
358*4882a593Smuzhiyun 	{0x0c06, 0x0200},
359*4882a593Smuzhiyun 	{0x0c10, 0x0040},
360*4882a593Smuzhiyun 	{0x0c12, 0x0040},
361*4882a593Smuzhiyun 	{0x0c14, 0x0040},
362*4882a593Smuzhiyun 	{0x0c16, 0x0040},
363*4882a593Smuzhiyun 	{0x0a10, 0x4000},
364*4882a593Smuzhiyun 	{0x3068, 0xf800},
365*4882a593Smuzhiyun 	{0x306a, 0xf876},
366*4882a593Smuzhiyun 	{0x006c, 0x0000},
367*4882a593Smuzhiyun 	{0x005e, 0x0200},
368*4882a593Smuzhiyun 	{0x000e, 0x0100},
369*4882a593Smuzhiyun 	{0x0e0a, 0x0001},
370*4882a593Smuzhiyun 	{0x004a, 0x0100},
371*4882a593Smuzhiyun 	{0x004c, 0x0000},
372*4882a593Smuzhiyun 	{0x004e, 0x0100},
373*4882a593Smuzhiyun 	{0x000c, 0x0022},
374*4882a593Smuzhiyun 	{0x0008, 0x0b00},
375*4882a593Smuzhiyun 	{0x005a, 0x0202},
376*4882a593Smuzhiyun 	{0x0012, 0x000e},
377*4882a593Smuzhiyun 	{0x0018, 0x0a31},
378*4882a593Smuzhiyun 	{0x0022, 0x0008},
379*4882a593Smuzhiyun 	{0x0028, 0x0017},
380*4882a593Smuzhiyun 	{0x0024, 0x0028},
381*4882a593Smuzhiyun 	{0x002a, 0x002d},
382*4882a593Smuzhiyun 	{0x0026, 0x0030},
383*4882a593Smuzhiyun 	{0x002c, 0x07c7},
384*4882a593Smuzhiyun 	{0x002e, 0x1111},
385*4882a593Smuzhiyun 	{0x0030, 0x1111},
386*4882a593Smuzhiyun 	{0x0032, 0x1111},
387*4882a593Smuzhiyun 	{0x0006, 0x0823},
388*4882a593Smuzhiyun 	{0x0a22, 0x0000},
389*4882a593Smuzhiyun 	{0x0a12, 0x0a20},
390*4882a593Smuzhiyun 	{0x0a14, 0x0798},
391*4882a593Smuzhiyun 	{0x003e, 0x0000},
392*4882a593Smuzhiyun 	{0x0074, 0x0821},
393*4882a593Smuzhiyun 	{0x0070, 0x0411},
394*4882a593Smuzhiyun 	{0x0002, 0x0000},
395*4882a593Smuzhiyun 	{0x0a02, 0x0100},
396*4882a593Smuzhiyun 	{0x0a24, 0x0100},
397*4882a593Smuzhiyun 	{0x0076, 0x0000},
398*4882a593Smuzhiyun 	{0x0060, 0x0000},
399*4882a593Smuzhiyun 	{0x0062, 0x0530},
400*4882a593Smuzhiyun 	{0x0064, 0x0500},
401*4882a593Smuzhiyun 	{0x0066, 0x0530},
402*4882a593Smuzhiyun 	{0x0068, 0x0500},
403*4882a593Smuzhiyun 	{0x0122, 0x0300},
404*4882a593Smuzhiyun 	{0x015a, 0xff08},
405*4882a593Smuzhiyun 	{0x0804, 0x0200},
406*4882a593Smuzhiyun 	{0x005c, 0x0102},
407*4882a593Smuzhiyun 	{0x0a1a, 0x0800},
408*4882a593Smuzhiyun 	{0x003c, 0x0101}, //fix framerate
409*4882a593Smuzhiyun 	{REG_NULL, 0x00},
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun /*
413*4882a593Smuzhiyun  * Xclk 24Mhz
414*4882a593Smuzhiyun  * Pclk 210Mhz
415*4882a593Smuzhiyun  * linelength 2816
416*4882a593Smuzhiyun  * framelength 2083
417*4882a593Smuzhiyun  * grabwindow_width 2592
418*4882a593Smuzhiyun  * grabwindow_height 1944
419*4882a593Smuzhiyun  * max_framerate 30fps
420*4882a593Smuzhiyun  * MIPI speed(Mbps): 880Mbps x 2lane
421*4882a593Smuzhiyun  */
422*4882a593Smuzhiyun static const struct regval hi556_2592x1944_regs_2lane[] = {
423*4882a593Smuzhiyun 	{0x0a00, 0x0000},
424*4882a593Smuzhiyun 	{0x0b0a, 0x8252},
425*4882a593Smuzhiyun 	{0x0f30, 0x6e25},
426*4882a593Smuzhiyun 	{0x0f32, 0x7067},
427*4882a593Smuzhiyun 	{0x004a, 0x0100},
428*4882a593Smuzhiyun 	{0x004c, 0x0000},
429*4882a593Smuzhiyun 	{0x004e, 0x0000},
430*4882a593Smuzhiyun 	{0x000c, 0x0022},
431*4882a593Smuzhiyun 	{0x0008, 0x0b00},
432*4882a593Smuzhiyun 	{0x005a, 0x0202},
433*4882a593Smuzhiyun 	{0x0012, 0x000e},
434*4882a593Smuzhiyun 	{0x0018, 0x0a31},
435*4882a593Smuzhiyun 	{0x0022, 0x0008},
436*4882a593Smuzhiyun 	{0x0028, 0x0017},
437*4882a593Smuzhiyun 	{0x0024, 0x0028},
438*4882a593Smuzhiyun 	{0x002a, 0x002d},
439*4882a593Smuzhiyun 	{0x0026, 0x0030},
440*4882a593Smuzhiyun 	{0x002c, 0x07c7},
441*4882a593Smuzhiyun 	{0x002e, 0x1111},
442*4882a593Smuzhiyun 	{0x0030, 0x1111},
443*4882a593Smuzhiyun 	{0x0032, 0x1111},
444*4882a593Smuzhiyun 	{0x0006, 0x0823},
445*4882a593Smuzhiyun 	{0x0a22, 0x0000},
446*4882a593Smuzhiyun 	{0x0a12, 0x0a20},
447*4882a593Smuzhiyun 	{0x0a14, 0x0798},
448*4882a593Smuzhiyun 	{0x003e, 0x0000},
449*4882a593Smuzhiyun 	{0x0804, 0x0200},
450*4882a593Smuzhiyun 	{0x0a04, 0x014a},
451*4882a593Smuzhiyun 	{0x090c, 0x0fdc},
452*4882a593Smuzhiyun 	{0x090e, 0x002d},
453*4882a593Smuzhiyun 	{0x0902, 0x4319},
454*4882a593Smuzhiyun 	{0x0914, 0xc10a},
455*4882a593Smuzhiyun 	{0x0916, 0x071f},
456*4882a593Smuzhiyun 	{0x0918, 0x0408},
457*4882a593Smuzhiyun 	{0x091a, 0x0c0d},
458*4882a593Smuzhiyun 	{0x091c, 0x0f09},
459*4882a593Smuzhiyun 	{0x091e, 0x0a00},
460*4882a593Smuzhiyun 	//{0x0a00, 0x0100},
461*4882a593Smuzhiyun 	{REG_NULL, 0x00},
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun static const struct hi556_mode supported_modes_2lane[] = {
465*4882a593Smuzhiyun 	{
466*4882a593Smuzhiyun 		.width = 2592,
467*4882a593Smuzhiyun 		.height = 1944,
468*4882a593Smuzhiyun 		.max_fps = {
469*4882a593Smuzhiyun 			.numerator = 10000,
470*4882a593Smuzhiyun 			.denominator = 300000,
471*4882a593Smuzhiyun 		},
472*4882a593Smuzhiyun 		.exp_def = 0x0810,
473*4882a593Smuzhiyun 		.hts_def = 0x0B00,
474*4882a593Smuzhiyun 		.vts_def = 0x0823,
475*4882a593Smuzhiyun 		.reg_list = hi556_2592x1944_regs_2lane,
476*4882a593Smuzhiyun 		.hdr_mode = NO_HDR,
477*4882a593Smuzhiyun 	}
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun static const struct hi556_mode *supported_modes;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
483*4882a593Smuzhiyun 	MIPI_FREQ
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static const char * const hi556_test_pattern_menu[] = {
487*4882a593Smuzhiyun 	"Disabled",
488*4882a593Smuzhiyun 	"Solid color bar",
489*4882a593Smuzhiyun 	"100% color bars",
490*4882a593Smuzhiyun 	"Fade to gray color bars",
491*4882a593Smuzhiyun 	"PN9",
492*4882a593Smuzhiyun 	"Horizental/Vertical gradient",
493*4882a593Smuzhiyun 	"Check board",
494*4882a593Smuzhiyun 	"Slant",
495*4882a593Smuzhiyun 	"Resolution",
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun /* Write registers up to 4 at a time */
hi556_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)499*4882a593Smuzhiyun static int hi556_write_reg(struct i2c_client *client, u16 reg,
500*4882a593Smuzhiyun 			    u32 len, u32 val)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	u32 buf_i, val_i;
503*4882a593Smuzhiyun 	u8 buf[6];
504*4882a593Smuzhiyun 	u8 *val_p;
505*4882a593Smuzhiyun 	__be32 val_be;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	dev_dbg(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
508*4882a593Smuzhiyun 	dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	if (len > 4)
511*4882a593Smuzhiyun 		return -EINVAL;
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	buf[0] = reg >> 8;
514*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	val_be = cpu_to_be32(val);
517*4882a593Smuzhiyun 	val_p = (u8 *)&val_be;
518*4882a593Smuzhiyun 	buf_i = 2;
519*4882a593Smuzhiyun 	val_i = 4 - len;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	while (val_i < 4)
522*4882a593Smuzhiyun 		buf[buf_i++] = val_p[val_i++];
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2) {
525*4882a593Smuzhiyun 		dev_err(&client->dev,
526*4882a593Smuzhiyun 			   "write reg(0x%x val:0x%x)failed !\n", reg, val);
527*4882a593Smuzhiyun 		return -EIO;
528*4882a593Smuzhiyun 	}
529*4882a593Smuzhiyun 	return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
hi556_write_array(struct i2c_client * client,const struct regval * regs)532*4882a593Smuzhiyun static int hi556_write_array(struct i2c_client *client,
533*4882a593Smuzhiyun 			      const struct regval *regs)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun 	int i, delay_ms, ret = 0;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
538*4882a593Smuzhiyun 		if (regs[i].addr == DELAY_MS) {
539*4882a593Smuzhiyun 			delay_ms = regs[i].val;
540*4882a593Smuzhiyun 			dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
541*4882a593Smuzhiyun 			usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
542*4882a593Smuzhiyun 			continue;
543*4882a593Smuzhiyun 		}
544*4882a593Smuzhiyun 		ret = hi556_write_reg(client, regs[i].addr,
545*4882a593Smuzhiyun 				       HI556_REG_VALUE_16BIT, regs[i].val);
546*4882a593Smuzhiyun 		if (ret)
547*4882a593Smuzhiyun 			dev_err(&client->dev, "%s failed !\n", __func__);
548*4882a593Smuzhiyun 	}
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	return ret;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun /* Read registers up to 4 at a time */
hi556_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)554*4882a593Smuzhiyun static int hi556_read_reg(struct i2c_client *client, u16 reg,
555*4882a593Smuzhiyun 					unsigned int len, u32 *val)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
558*4882a593Smuzhiyun 	u8 *data_be_p;
559*4882a593Smuzhiyun 	__be32 data_be = 0;
560*4882a593Smuzhiyun 	__be16 reg_addr_be = cpu_to_be16(reg);
561*4882a593Smuzhiyun 	int ret;
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	if (len > 4 || !len)
564*4882a593Smuzhiyun 		return -EINVAL;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	data_be_p = (u8 *)&data_be;
567*4882a593Smuzhiyun 	/* Write register address */
568*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
569*4882a593Smuzhiyun 	msgs[0].flags = 0;
570*4882a593Smuzhiyun 	msgs[0].len = 2;
571*4882a593Smuzhiyun 	msgs[0].buf = (u8 *)&reg_addr_be;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	/* Read data from register */
574*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
575*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
576*4882a593Smuzhiyun 	msgs[1].len = len;
577*4882a593Smuzhiyun 	msgs[1].buf = &data_be_p[4 - len];
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
580*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
581*4882a593Smuzhiyun 		return -EIO;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	*val = be32_to_cpu(data_be);
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	return 0;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun /* Check Register value */
589*4882a593Smuzhiyun #ifdef CHECK_REG_VALUE
hi556_reg_verify(struct i2c_client * client,const struct regval * regs)590*4882a593Smuzhiyun static int hi556_reg_verify(struct i2c_client *client,
591*4882a593Smuzhiyun 				const struct regval *regs)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun 	u32 i;
594*4882a593Smuzhiyun 	int ret = 0;
595*4882a593Smuzhiyun 	u32 value;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
598*4882a593Smuzhiyun 		ret = hi556_read_reg(client, regs[i].addr,
599*4882a593Smuzhiyun 			  HI556_REG_VALUE_16BIT, &value);
600*4882a593Smuzhiyun 		if (value != regs[i].val) {
601*4882a593Smuzhiyun 			dev_info(&client->dev, "%s: 0x%04x is 0x%x instead of 0x%x\n",
602*4882a593Smuzhiyun 				  __func__, regs[i].addr, value, regs[i].val);
603*4882a593Smuzhiyun 		}
604*4882a593Smuzhiyun 	}
605*4882a593Smuzhiyun 	return ret;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun #endif
608*4882a593Smuzhiyun 
hi556_get_reso_dist(const struct hi556_mode * mode,struct v4l2_mbus_framefmt * framefmt)609*4882a593Smuzhiyun static int hi556_get_reso_dist(const struct hi556_mode *mode,
610*4882a593Smuzhiyun 				struct v4l2_mbus_framefmt *framefmt)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun 	return abs(mode->width - framefmt->width) +
613*4882a593Smuzhiyun 	       abs(mode->height - framefmt->height);
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun static const struct hi556_mode *
hi556_find_best_fit(struct hi556 * hi556,struct v4l2_subdev_format * fmt)617*4882a593Smuzhiyun hi556_find_best_fit(struct hi556 *hi556,
618*4882a593Smuzhiyun 			struct v4l2_subdev_format *fmt)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
621*4882a593Smuzhiyun 	int dist;
622*4882a593Smuzhiyun 	int cur_best_fit = 0;
623*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
624*4882a593Smuzhiyun 	unsigned int i;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	for (i = 0; i < hi556->cfg_num; i++) {
627*4882a593Smuzhiyun 		dist = hi556_get_reso_dist(&supported_modes[i], framefmt);
628*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
629*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
630*4882a593Smuzhiyun 			cur_best_fit = i;
631*4882a593Smuzhiyun 		}
632*4882a593Smuzhiyun 	}
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	return &supported_modes[cur_best_fit];
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun 
hi556_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)637*4882a593Smuzhiyun static int hi556_set_fmt(struct v4l2_subdev *sd,
638*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
639*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
642*4882a593Smuzhiyun 	const struct hi556_mode *mode;
643*4882a593Smuzhiyun 	s64 h_blank, vblank_def;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	mode = hi556_find_best_fit(hi556, fmt);
648*4882a593Smuzhiyun 	fmt->format.code = HI556_MEDIA_BUS_FMT;
649*4882a593Smuzhiyun 	fmt->format.width = mode->width;
650*4882a593Smuzhiyun 	fmt->format.height = mode->height;
651*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
652*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
653*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
654*4882a593Smuzhiyun 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
655*4882a593Smuzhiyun #else
656*4882a593Smuzhiyun 		mutex_unlock(&hi556->mutex);
657*4882a593Smuzhiyun 		return -ENOTTY;
658*4882a593Smuzhiyun #endif
659*4882a593Smuzhiyun 	} else {
660*4882a593Smuzhiyun 		hi556->cur_mode = mode;
661*4882a593Smuzhiyun 		h_blank = mode->hts_def - mode->width;
662*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(hi556->hblank, h_blank,
663*4882a593Smuzhiyun 					 h_blank, 1, h_blank);
664*4882a593Smuzhiyun 		vblank_def = mode->vts_def - mode->height;
665*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(hi556->vblank, vblank_def,
666*4882a593Smuzhiyun 					 HI556_VTS_MAX - mode->height,
667*4882a593Smuzhiyun 					 1, vblank_def);
668*4882a593Smuzhiyun 	}
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	return 0;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun 
hi556_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)675*4882a593Smuzhiyun static int hi556_get_fmt(struct v4l2_subdev *sd,
676*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
677*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
680*4882a593Smuzhiyun 	const struct hi556_mode *mode = hi556->cur_mode;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
683*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
684*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
685*4882a593Smuzhiyun 		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
686*4882a593Smuzhiyun #else
687*4882a593Smuzhiyun 		mutex_unlock(&hi556->mutex);
688*4882a593Smuzhiyun 		return -ENOTTY;
689*4882a593Smuzhiyun #endif
690*4882a593Smuzhiyun 	} else {
691*4882a593Smuzhiyun 		fmt->format.width = mode->width;
692*4882a593Smuzhiyun 		fmt->format.height = mode->height;
693*4882a593Smuzhiyun 		fmt->format.code = HI556_MEDIA_BUS_FMT;
694*4882a593Smuzhiyun 		fmt->format.field = V4L2_FIELD_NONE;
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun 	return 0;
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun 
hi556_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)701*4882a593Smuzhiyun static int hi556_enum_mbus_code(struct v4l2_subdev *sd,
702*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
703*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	if (code->index != 0)
706*4882a593Smuzhiyun 		return -EINVAL;
707*4882a593Smuzhiyun 	code->code = HI556_MEDIA_BUS_FMT;
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 	return 0;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun 
hi556_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)712*4882a593Smuzhiyun static int hi556_enum_frame_sizes(struct v4l2_subdev *sd,
713*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
714*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	if (fse->index >= hi556->cfg_num)
719*4882a593Smuzhiyun 		return -EINVAL;
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	if (fse->code != HI556_MEDIA_BUS_FMT)
722*4882a593Smuzhiyun 		return -EINVAL;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	fse->min_width  = supported_modes[fse->index].width;
725*4882a593Smuzhiyun 	fse->max_width  = supported_modes[fse->index].width;
726*4882a593Smuzhiyun 	fse->max_height = supported_modes[fse->index].height;
727*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	return 0;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun 
hi556_enable_test_pattern(struct hi556 * hi556,u32 pattern)732*4882a593Smuzhiyun static int hi556_enable_test_pattern(struct hi556 *hi556, u32 pattern)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	if (pattern) {
736*4882a593Smuzhiyun 		hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN,
737*4882a593Smuzhiyun 						HI556_REG_VALUE_08BIT, HI556_TEST_PATTERN_ENABLE);
738*4882a593Smuzhiyun 		hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN_SELECT,
739*4882a593Smuzhiyun 						HI556_REG_VALUE_08BIT, 0x01 << (pattern - 1));
740*4882a593Smuzhiyun 	} else {
741*4882a593Smuzhiyun 		hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN,
742*4882a593Smuzhiyun 						HI556_REG_VALUE_08BIT, HI556_TEST_PATTERN_DISABLE);
743*4882a593Smuzhiyun 	}
744*4882a593Smuzhiyun 	return 0;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun 
hi556_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)747*4882a593Smuzhiyun static int hi556_g_frame_interval(struct v4l2_subdev *sd,
748*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
751*4882a593Smuzhiyun 	const struct hi556_mode *mode = hi556->cur_mode;
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	return 0;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun 
hi556_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)758*4882a593Smuzhiyun static int hi556_g_mbus_config(struct v4l2_subdev *sd,
759*4882a593Smuzhiyun 				unsigned int pad_id,
760*4882a593Smuzhiyun 				struct v4l2_mbus_config *config)
761*4882a593Smuzhiyun {
762*4882a593Smuzhiyun 	u32 val = 1 << (HI556_LANES - 1) |
763*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CHANNEL_0 |
764*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	config->type = V4L2_MBUS_CSI2_DPHY;
767*4882a593Smuzhiyun 	config->flags = val;
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	return 0;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun 
hi556_get_module_inf(struct hi556 * hi556,struct rkmodule_inf * inf)772*4882a593Smuzhiyun static void hi556_get_module_inf(struct hi556 *hi556,
773*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
776*4882a593Smuzhiyun 	strscpy(inf->base.sensor, HI556_NAME, sizeof(inf->base.sensor));
777*4882a593Smuzhiyun 	strscpy(inf->base.module, hi556->module_name,
778*4882a593Smuzhiyun 		sizeof(inf->base.module));
779*4882a593Smuzhiyun 	strscpy(inf->base.lens, hi556->len_name, sizeof(inf->base.lens));
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun 
hi556_set_awb_cfg(struct hi556 * hi556,struct rkmodule_awb_cfg * cfg)783*4882a593Smuzhiyun static void hi556_set_awb_cfg(struct hi556 *hi556,
784*4882a593Smuzhiyun 				 struct rkmodule_awb_cfg *cfg)
785*4882a593Smuzhiyun {
786*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
787*4882a593Smuzhiyun 	memcpy(&hi556->awb_cfg, cfg, sizeof(*cfg));
788*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
789*4882a593Smuzhiyun }
790*4882a593Smuzhiyun 
hi556_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)791*4882a593Smuzhiyun static long hi556_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
792*4882a593Smuzhiyun {
793*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
794*4882a593Smuzhiyun 	long ret = 0;
795*4882a593Smuzhiyun 	u32 stream = 0;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 	switch (cmd) {
798*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
799*4882a593Smuzhiyun 		hi556_get_module_inf(hi556, (struct rkmodule_inf *)arg);
800*4882a593Smuzhiyun 		break;
801*4882a593Smuzhiyun 	case RKMODULE_AWB_CFG:
802*4882a593Smuzhiyun 		hi556_set_awb_cfg(hi556, (struct rkmodule_awb_cfg *)arg);
803*4882a593Smuzhiyun 		break;
804*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 		stream = *((u32 *)arg);
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 		if (stream)
809*4882a593Smuzhiyun 			ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
810*4882a593Smuzhiyun 				HI556_REG_VALUE_08BIT, HI556_MODE_STREAMING);
811*4882a593Smuzhiyun 		else
812*4882a593Smuzhiyun 			ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
813*4882a593Smuzhiyun 				HI556_REG_VALUE_08BIT, HI556_MODE_SW_STANDBY);
814*4882a593Smuzhiyun 		break;
815*4882a593Smuzhiyun 	default:
816*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
817*4882a593Smuzhiyun 		break;
818*4882a593Smuzhiyun 	}
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	return ret;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
hi556_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)824*4882a593Smuzhiyun static long hi556_compat_ioctl32(struct v4l2_subdev *sd,
825*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
828*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
829*4882a593Smuzhiyun 	struct rkmodule_awb_cfg *awb_cfg;
830*4882a593Smuzhiyun 	long ret;
831*4882a593Smuzhiyun 	u32 stream = 0;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	switch (cmd) {
834*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
835*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
836*4882a593Smuzhiyun 		if (!inf) {
837*4882a593Smuzhiyun 			ret = -ENOMEM;
838*4882a593Smuzhiyun 			return ret;
839*4882a593Smuzhiyun 		}
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 		ret = hi556_ioctl(sd, cmd, inf);
842*4882a593Smuzhiyun 		if (!ret) {
843*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
844*4882a593Smuzhiyun 			if (ret)
845*4882a593Smuzhiyun 				ret = -EFAULT;
846*4882a593Smuzhiyun 		}
847*4882a593Smuzhiyun 		kfree(inf);
848*4882a593Smuzhiyun 		break;
849*4882a593Smuzhiyun 	case RKMODULE_AWB_CFG:
850*4882a593Smuzhiyun 		awb_cfg = kzalloc(sizeof(*awb_cfg), GFP_KERNEL);
851*4882a593Smuzhiyun 		if (!awb_cfg) {
852*4882a593Smuzhiyun 			ret = -ENOMEM;
853*4882a593Smuzhiyun 			return ret;
854*4882a593Smuzhiyun 		}
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 		if (copy_from_user(awb_cfg, up, sizeof(*awb_cfg))) {
857*4882a593Smuzhiyun 			kfree(awb_cfg);
858*4882a593Smuzhiyun 			return -EFAULT;
859*4882a593Smuzhiyun 		}
860*4882a593Smuzhiyun 		ret = hi556_ioctl(sd, cmd, awb_cfg);
861*4882a593Smuzhiyun 		kfree(awb_cfg);
862*4882a593Smuzhiyun 		break;
863*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
864*4882a593Smuzhiyun 		if (copy_from_user(&stream, up, sizeof(u32)))
865*4882a593Smuzhiyun 			return -EFAULT;
866*4882a593Smuzhiyun 		ret = hi556_ioctl(sd, cmd, &stream);
867*4882a593Smuzhiyun 		break;
868*4882a593Smuzhiyun 	default:
869*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
870*4882a593Smuzhiyun 		break;
871*4882a593Smuzhiyun 	}
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	return ret;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun #endif
876*4882a593Smuzhiyun 
__hi556_start_stream(struct hi556 * hi556)877*4882a593Smuzhiyun static int __hi556_start_stream(struct hi556 *hi556)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun 	int ret;
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	ret = hi556_write_array(hi556->client, hi556->cur_mode->reg_list);
882*4882a593Smuzhiyun 	if (ret)
883*4882a593Smuzhiyun 		return ret;
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun #ifdef CHECK_REG_VALUE
886*4882a593Smuzhiyun 	usleep_range(10000, 20000);
887*4882a593Smuzhiyun 	/*  verify default values to make sure everything has */
888*4882a593Smuzhiyun 	/*  been written correctly as expected */
889*4882a593Smuzhiyun 	dev_info(&hi556->client->dev, "%s:Check register value!\n",
890*4882a593Smuzhiyun 				__func__);
891*4882a593Smuzhiyun 	ret = hi556_reg_verify(hi556->client, hi556_global_regs);
892*4882a593Smuzhiyun 	if (ret)
893*4882a593Smuzhiyun 		return ret;
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun 	ret = hi556_reg_verify(hi556->client, hi556->cur_mode->reg_list);
896*4882a593Smuzhiyun 	if (ret)
897*4882a593Smuzhiyun 		return ret;
898*4882a593Smuzhiyun #endif
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	/* In case these controls are set before streaming */
901*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
902*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&hi556->ctrl_handler);
903*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
904*4882a593Smuzhiyun 	if (ret)
905*4882a593Smuzhiyun 		return ret;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	if (ret)
908*4882a593Smuzhiyun 		dev_info(&hi556->client->dev, "APPly otp failed!\n");
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
911*4882a593Smuzhiyun 				HI556_REG_VALUE_08BIT, HI556_MODE_STREAMING);
912*4882a593Smuzhiyun 	return ret;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun 
__hi556_stop_stream(struct hi556 * hi556)915*4882a593Smuzhiyun static int __hi556_stop_stream(struct hi556 *hi556)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun 	return hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
918*4882a593Smuzhiyun 				HI556_REG_VALUE_08BIT, HI556_MODE_SW_STANDBY);
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun 
hi556_s_stream(struct v4l2_subdev * sd,int on)921*4882a593Smuzhiyun static int hi556_s_stream(struct v4l2_subdev *sd, int on)
922*4882a593Smuzhiyun {
923*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
924*4882a593Smuzhiyun 	struct i2c_client *client = hi556->client;
925*4882a593Smuzhiyun 	int ret = 0;
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun 	dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
928*4882a593Smuzhiyun 				hi556->cur_mode->width,
929*4882a593Smuzhiyun 				hi556->cur_mode->height,
930*4882a593Smuzhiyun 		DIV_ROUND_CLOSEST(hi556->cur_mode->max_fps.denominator,
931*4882a593Smuzhiyun 		hi556->cur_mode->max_fps.numerator));
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
934*4882a593Smuzhiyun 	on = !!on;
935*4882a593Smuzhiyun 	if (on == hi556->streaming)
936*4882a593Smuzhiyun 		goto unlock_and_return;
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 	if (on) {
939*4882a593Smuzhiyun 		dev_info(&client->dev, "stream on!!!\n");
940*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
941*4882a593Smuzhiyun 		if (ret < 0) {
942*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
943*4882a593Smuzhiyun 			goto unlock_and_return;
944*4882a593Smuzhiyun 		}
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 		ret = __hi556_start_stream(hi556);
947*4882a593Smuzhiyun 		if (ret) {
948*4882a593Smuzhiyun 			v4l2_err(sd, "start stream failed while write regs\n");
949*4882a593Smuzhiyun 			pm_runtime_put(&client->dev);
950*4882a593Smuzhiyun 			goto unlock_and_return;
951*4882a593Smuzhiyun 		}
952*4882a593Smuzhiyun 	} else {
953*4882a593Smuzhiyun 		dev_info(&client->dev, "stream off!!!\n");
954*4882a593Smuzhiyun 		__hi556_stop_stream(hi556);
955*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
956*4882a593Smuzhiyun 	}
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	hi556->streaming = on;
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun unlock_and_return:
961*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	return ret;
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun 
hi556_s_power(struct v4l2_subdev * sd,int on)966*4882a593Smuzhiyun static int hi556_s_power(struct v4l2_subdev *sd, int on)
967*4882a593Smuzhiyun {
968*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
969*4882a593Smuzhiyun 	struct i2c_client *client = hi556->client;
970*4882a593Smuzhiyun 	int ret = 0;
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun 	dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
973*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	/* If the power state is not modified - no work to do. */
976*4882a593Smuzhiyun 	if (hi556->power_on == !!on)
977*4882a593Smuzhiyun 		goto unlock_and_return;
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 	if (on) {
980*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
981*4882a593Smuzhiyun 		if (ret < 0) {
982*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
983*4882a593Smuzhiyun 			goto unlock_and_return;
984*4882a593Smuzhiyun 		}
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun 		ret = hi556_write_array(hi556->client, hi556_global_regs);
987*4882a593Smuzhiyun 		if (ret) {
988*4882a593Smuzhiyun 			v4l2_err(sd, "could not set init registers\n");
989*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
990*4882a593Smuzhiyun 			goto unlock_and_return;
991*4882a593Smuzhiyun 		}
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 		hi556->power_on = true;
994*4882a593Smuzhiyun 	} else {
995*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
996*4882a593Smuzhiyun 		hi556->power_on = false;
997*4882a593Smuzhiyun 	}
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun unlock_and_return:
1000*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	return ret;
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
hi556_cal_delay(u32 cycles)1006*4882a593Smuzhiyun static inline u32 hi556_cal_delay(u32 cycles)
1007*4882a593Smuzhiyun {
1008*4882a593Smuzhiyun 	return DIV_ROUND_UP(cycles, HI556_XVCLK_FREQ / 1000 / 1000);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun 
__hi556_power_on(struct hi556 * hi556)1011*4882a593Smuzhiyun static int __hi556_power_on(struct hi556 *hi556)
1012*4882a593Smuzhiyun {
1013*4882a593Smuzhiyun 	int ret;
1014*4882a593Smuzhiyun 	u32 delay_us;
1015*4882a593Smuzhiyun 	struct device *dev = &hi556->client->dev;
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	if (!IS_ERR(hi556->power_gpio))
1018*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->power_gpio, 1);
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 	usleep_range(1000, 2000);
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun 	if (!IS_ERR_OR_NULL(hi556->pins_default)) {
1023*4882a593Smuzhiyun 		ret = pinctrl_select_state(hi556->pinctrl,
1024*4882a593Smuzhiyun 					   hi556->pins_default);
1025*4882a593Smuzhiyun 		if (ret < 0)
1026*4882a593Smuzhiyun 			dev_err(dev, "could not set pins\n");
1027*4882a593Smuzhiyun 	}
1028*4882a593Smuzhiyun 	ret = clk_set_rate(hi556->xvclk, HI556_XVCLK_FREQ);
1029*4882a593Smuzhiyun 	if (ret < 0)
1030*4882a593Smuzhiyun 		dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1031*4882a593Smuzhiyun 	if (clk_get_rate(hi556->xvclk) != HI556_XVCLK_FREQ)
1032*4882a593Smuzhiyun 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun 	ret = clk_prepare_enable(hi556->xvclk);
1035*4882a593Smuzhiyun 	if (ret < 0) {
1036*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable xvclk\n");
1037*4882a593Smuzhiyun 		return ret;
1038*4882a593Smuzhiyun 	}
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	ret = regulator_bulk_enable(HI556_NUM_SUPPLIES, hi556->supplies);
1041*4882a593Smuzhiyun 	if (ret < 0) {
1042*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable regulators\n");
1043*4882a593Smuzhiyun 		goto disable_clk;
1044*4882a593Smuzhiyun 	}
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	if (!IS_ERR(hi556->reset_gpio))
1047*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->reset_gpio, 1);
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun 	if (!IS_ERR(hi556->pwdn_gpio))
1050*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->pwdn_gpio, 1);
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	/* 8192 cycles prior to first SCCB transaction */
1053*4882a593Smuzhiyun 	delay_us = hi556_cal_delay(8192);
1054*4882a593Smuzhiyun 	usleep_range(delay_us, delay_us * 2);
1055*4882a593Smuzhiyun 	usleep_range(10000, 20000);
1056*4882a593Smuzhiyun 	return 0;
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun disable_clk:
1059*4882a593Smuzhiyun 	clk_disable_unprepare(hi556->xvclk);
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	return ret;
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun 
__hi556_power_off(struct hi556 * hi556)1064*4882a593Smuzhiyun static void __hi556_power_off(struct hi556 *hi556)
1065*4882a593Smuzhiyun {
1066*4882a593Smuzhiyun 	int ret;
1067*4882a593Smuzhiyun 	struct device *dev = &hi556->client->dev;
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	if (!IS_ERR(hi556->pwdn_gpio))
1070*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->pwdn_gpio, 0);
1071*4882a593Smuzhiyun 	clk_disable_unprepare(hi556->xvclk);
1072*4882a593Smuzhiyun 	if (!IS_ERR(hi556->reset_gpio))
1073*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->reset_gpio, 0);
1074*4882a593Smuzhiyun 	if (!IS_ERR_OR_NULL(hi556->pins_sleep)) {
1075*4882a593Smuzhiyun 		ret = pinctrl_select_state(hi556->pinctrl,
1076*4882a593Smuzhiyun 					   hi556->pins_sleep);
1077*4882a593Smuzhiyun 		if (ret < 0)
1078*4882a593Smuzhiyun 			dev_dbg(dev, "could not set pins\n");
1079*4882a593Smuzhiyun 	}
1080*4882a593Smuzhiyun 	if (!IS_ERR(hi556->power_gpio))
1081*4882a593Smuzhiyun 		gpiod_set_value_cansleep(hi556->power_gpio, 0);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	regulator_bulk_disable(HI556_NUM_SUPPLIES, hi556->supplies);
1084*4882a593Smuzhiyun }
1085*4882a593Smuzhiyun 
hi556_runtime_resume(struct device * dev)1086*4882a593Smuzhiyun static int hi556_runtime_resume(struct device *dev)
1087*4882a593Smuzhiyun {
1088*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1089*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1090*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	return __hi556_power_on(hi556);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun 
hi556_runtime_suspend(struct device * dev)1095*4882a593Smuzhiyun static int hi556_runtime_suspend(struct device *dev)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1098*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1099*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	__hi556_power_off(hi556);
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	return 0;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
hi556_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1107*4882a593Smuzhiyun static int hi556_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
1110*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1111*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1112*4882a593Smuzhiyun 	const struct hi556_mode *def_mode = &supported_modes[0];
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	mutex_lock(&hi556->mutex);
1115*4882a593Smuzhiyun 	/* Initialize try_fmt */
1116*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1117*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1118*4882a593Smuzhiyun 	try_fmt->code = HI556_MEDIA_BUS_FMT;
1119*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	mutex_unlock(&hi556->mutex);
1122*4882a593Smuzhiyun 	/* No crop or compose */
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	return 0;
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun #endif
1127*4882a593Smuzhiyun 
hi556_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1128*4882a593Smuzhiyun static int hi556_enum_frame_interval(struct v4l2_subdev *sd,
1129*4882a593Smuzhiyun 				       struct v4l2_subdev_pad_config *cfg,
1130*4882a593Smuzhiyun 				       struct v4l2_subdev_frame_interval_enum *fie)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	if (fie->index >= hi556->cfg_num)
1135*4882a593Smuzhiyun 		return -EINVAL;
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	if (fie->code != HI556_MEDIA_BUS_FMT)
1138*4882a593Smuzhiyun 		return -EINVAL;
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	fie->width = supported_modes[fie->index].width;
1141*4882a593Smuzhiyun 	fie->height = supported_modes[fie->index].height;
1142*4882a593Smuzhiyun 	fie->interval = supported_modes[fie->index].max_fps;
1143*4882a593Smuzhiyun 	fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 	return 0;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun static const struct dev_pm_ops hi556_pm_ops = {
1149*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(hi556_runtime_suspend,
1150*4882a593Smuzhiyun 			   hi556_runtime_resume, NULL)
1151*4882a593Smuzhiyun };
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1154*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops hi556_internal_ops = {
1155*4882a593Smuzhiyun 	.open = hi556_open,
1156*4882a593Smuzhiyun };
1157*4882a593Smuzhiyun #endif
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops hi556_core_ops = {
1160*4882a593Smuzhiyun 	.s_power = hi556_s_power,
1161*4882a593Smuzhiyun 	.ioctl = hi556_ioctl,
1162*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1163*4882a593Smuzhiyun 	.compat_ioctl32 = hi556_compat_ioctl32,
1164*4882a593Smuzhiyun #endif
1165*4882a593Smuzhiyun };
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops hi556_video_ops = {
1168*4882a593Smuzhiyun 	.s_stream = hi556_s_stream,
1169*4882a593Smuzhiyun 	.g_frame_interval = hi556_g_frame_interval,
1170*4882a593Smuzhiyun };
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops hi556_pad_ops = {
1173*4882a593Smuzhiyun 	.enum_mbus_code = hi556_enum_mbus_code,
1174*4882a593Smuzhiyun 	.enum_frame_size = hi556_enum_frame_sizes,
1175*4882a593Smuzhiyun 	.enum_frame_interval = hi556_enum_frame_interval,
1176*4882a593Smuzhiyun 	.get_fmt = hi556_get_fmt,
1177*4882a593Smuzhiyun 	.set_fmt = hi556_set_fmt,
1178*4882a593Smuzhiyun 	.get_mbus_config = hi556_g_mbus_config,
1179*4882a593Smuzhiyun };
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun static const struct v4l2_subdev_ops hi556_subdev_ops = {
1182*4882a593Smuzhiyun 	.core	= &hi556_core_ops,
1183*4882a593Smuzhiyun 	.video	= &hi556_video_ops,
1184*4882a593Smuzhiyun 	.pad	= &hi556_pad_ops,
1185*4882a593Smuzhiyun };
1186*4882a593Smuzhiyun 
hi556_set_exposure_reg(struct hi556 * hi556,u32 exposure)1187*4882a593Smuzhiyun static int hi556_set_exposure_reg(struct hi556 *hi556, u32 exposure)
1188*4882a593Smuzhiyun {
1189*4882a593Smuzhiyun 	int ret = 0;
1190*4882a593Smuzhiyun 	u32 cal_shutter = 0;
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 	cal_shutter = exposure >> 1;
1193*4882a593Smuzhiyun 	cal_shutter = cal_shutter << 1;
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 	ret = hi556_write_reg(hi556->client, HI556_REG_GROUP,
1196*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT, 0x01);
1197*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client,
1198*4882a593Smuzhiyun 				   HI556_REG_EXPOSURE_H,
1199*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT,
1200*4882a593Smuzhiyun 				   HI556_FETCH_HIGH_BYTE_EXP(cal_shutter));
1201*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client,
1202*4882a593Smuzhiyun 				   HI556_REG_EXPOSURE_M,
1203*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT,
1204*4882a593Smuzhiyun 				   HI556_FETCH_MIDDLE_BYTE_EXP(cal_shutter));
1205*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client,
1206*4882a593Smuzhiyun 				   HI556_REG_EXPOSURE_L,
1207*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT,
1208*4882a593Smuzhiyun 				   HI556_FETCH_LOW_BYTE_EXP(cal_shutter));
1209*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client, HI556_REG_GROUP,
1210*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT, 0x00);
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun 	return ret;
1213*4882a593Smuzhiyun }
1214*4882a593Smuzhiyun 
hi556_set_gain_reg(struct hi556 * hi556,u32 a_gain)1215*4882a593Smuzhiyun static int hi556_set_gain_reg(struct hi556 *hi556, u32 a_gain)
1216*4882a593Smuzhiyun {
1217*4882a593Smuzhiyun 	int ret = 0;
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun 	ret = hi556_write_reg(hi556->client, HI556_REG_GROUP,
1220*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT, 0x01);
1221*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client, HI556_REG_GAIN,
1222*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT, a_gain);
1223*4882a593Smuzhiyun 	ret |= hi556_write_reg(hi556->client, HI556_REG_GROUP,
1224*4882a593Smuzhiyun 				   HI556_REG_VALUE_08BIT, 0x00);
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	return ret;
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun 
hi556_set_ctrl(struct v4l2_ctrl * ctrl)1229*4882a593Smuzhiyun static int hi556_set_ctrl(struct v4l2_ctrl *ctrl)
1230*4882a593Smuzhiyun {
1231*4882a593Smuzhiyun 	struct hi556 *hi556 = container_of(ctrl->handler,
1232*4882a593Smuzhiyun 					     struct hi556, ctrl_handler);
1233*4882a593Smuzhiyun 	struct i2c_client *client = hi556->client;
1234*4882a593Smuzhiyun 	s64 max;
1235*4882a593Smuzhiyun 	u32 val = 0;
1236*4882a593Smuzhiyun 	int ret = 0;
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun 	/* Propagate change of current control to all related controls */
1239*4882a593Smuzhiyun 	switch (ctrl->id) {
1240*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1241*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
1242*4882a593Smuzhiyun 		max = hi556->cur_mode->height + ctrl->val - 4;
1243*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(hi556->exposure,
1244*4882a593Smuzhiyun 					 hi556->exposure->minimum, max,
1245*4882a593Smuzhiyun 					 hi556->exposure->step,
1246*4882a593Smuzhiyun 					 hi556->exposure->default_value);
1247*4882a593Smuzhiyun 		break;
1248*4882a593Smuzhiyun 	}
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
1251*4882a593Smuzhiyun 		return 0;
1252*4882a593Smuzhiyun 
1253*4882a593Smuzhiyun 	switch (ctrl->id) {
1254*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
1255*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
1256*4882a593Smuzhiyun 		/* 4 least significant bits of expsoure are fractional part */
1257*4882a593Smuzhiyun 		ret = hi556_set_exposure_reg(hi556, ctrl->val);
1258*4882a593Smuzhiyun 		break;
1259*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
1260*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
1261*4882a593Smuzhiyun 		ret = hi556_set_gain_reg(hi556, ctrl->val);
1262*4882a593Smuzhiyun 		break;
1263*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1264*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val);
1265*4882a593Smuzhiyun 		ret = hi556_write_reg(hi556->client, HI556_REG_VTS,
1266*4882a593Smuzhiyun 				       HI556_REG_VALUE_16BIT,
1267*4882a593Smuzhiyun 				       ctrl->val + hi556->cur_mode->height);
1268*4882a593Smuzhiyun 		break;
1269*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
1270*4882a593Smuzhiyun 		ret = hi556_enable_test_pattern(hi556, ctrl->val);
1271*4882a593Smuzhiyun 		break;
1272*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
1273*4882a593Smuzhiyun 		ret = hi556_read_reg(hi556->client, HI556_FLIP_MIRROR_REG,
1274*4882a593Smuzhiyun 				       HI556_REG_VALUE_08BIT, &val);
1275*4882a593Smuzhiyun 		ret |= hi556_write_reg(hi556->client, HI556_FLIP_MIRROR_REG,
1276*4882a593Smuzhiyun 					 HI556_REG_VALUE_08BIT,
1277*4882a593Smuzhiyun 					 HI556_FETCH_MIRROR(val, ctrl->val));
1278*4882a593Smuzhiyun 		break;
1279*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
1280*4882a593Smuzhiyun 		ret = hi556_read_reg(hi556->client, HI556_FLIP_MIRROR_REG,
1281*4882a593Smuzhiyun 				       HI556_REG_VALUE_08BIT, &val);
1282*4882a593Smuzhiyun 		ret |= hi556_write_reg(hi556->client, HI556_FLIP_MIRROR_REG,
1283*4882a593Smuzhiyun 					 HI556_REG_VALUE_08BIT,
1284*4882a593Smuzhiyun 					 HI556_FETCH_FLIP(val, ctrl->val));
1285*4882a593Smuzhiyun 		break;
1286*4882a593Smuzhiyun 	default:
1287*4882a593Smuzhiyun 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1288*4882a593Smuzhiyun 			 __func__, ctrl->id, ctrl->val);
1289*4882a593Smuzhiyun 		break;
1290*4882a593Smuzhiyun 	}
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
1293*4882a593Smuzhiyun 
1294*4882a593Smuzhiyun 	return ret;
1295*4882a593Smuzhiyun }
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun static const struct v4l2_ctrl_ops hi556_ctrl_ops = {
1298*4882a593Smuzhiyun 	.s_ctrl = hi556_set_ctrl,
1299*4882a593Smuzhiyun };
1300*4882a593Smuzhiyun 
hi556_initialize_controls(struct hi556 * hi556)1301*4882a593Smuzhiyun static int hi556_initialize_controls(struct hi556 *hi556)
1302*4882a593Smuzhiyun {
1303*4882a593Smuzhiyun 	const struct hi556_mode *mode;
1304*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler;
1305*4882a593Smuzhiyun 	struct v4l2_ctrl *ctrl;
1306*4882a593Smuzhiyun 	s64 exposure_max, vblank_def;
1307*4882a593Smuzhiyun 	u32 h_blank;
1308*4882a593Smuzhiyun 	int ret;
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	handler = &hi556->ctrl_handler;
1311*4882a593Smuzhiyun 	mode = hi556->cur_mode;
1312*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(handler, 9);
1313*4882a593Smuzhiyun 	if (ret)
1314*4882a593Smuzhiyun 		return ret;
1315*4882a593Smuzhiyun 	handler->lock = &hi556->mutex;
1316*4882a593Smuzhiyun 
1317*4882a593Smuzhiyun 	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1318*4882a593Smuzhiyun 				      0, 0, link_freq_menu_items);
1319*4882a593Smuzhiyun 	if (ctrl)
1320*4882a593Smuzhiyun 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1323*4882a593Smuzhiyun 			  0, hi556->pixel_rate, 1, hi556->pixel_rate);
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 	h_blank = mode->hts_def - mode->width;
1326*4882a593Smuzhiyun 	hi556->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1327*4882a593Smuzhiyun 				h_blank, h_blank, 1, h_blank);
1328*4882a593Smuzhiyun 	if (hi556->hblank)
1329*4882a593Smuzhiyun 		hi556->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1330*4882a593Smuzhiyun 
1331*4882a593Smuzhiyun 	vblank_def = mode->vts_def - mode->height;
1332*4882a593Smuzhiyun 	hi556->vblank = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
1333*4882a593Smuzhiyun 				V4L2_CID_VBLANK, vblank_def,
1334*4882a593Smuzhiyun 				HI556_VTS_MAX - mode->height,
1335*4882a593Smuzhiyun 				1, vblank_def);
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	exposure_max = mode->vts_def - 4;
1338*4882a593Smuzhiyun 	hi556->exposure = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
1339*4882a593Smuzhiyun 				V4L2_CID_EXPOSURE, HI556_EXPOSURE_MIN,
1340*4882a593Smuzhiyun 				exposure_max, HI556_EXPOSURE_STEP,
1341*4882a593Smuzhiyun 				mode->exp_def);
1342*4882a593Smuzhiyun 
1343*4882a593Smuzhiyun 	hi556->anal_gain = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
1344*4882a593Smuzhiyun 				V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1345*4882a593Smuzhiyun 				ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1346*4882a593Smuzhiyun 				ANALOG_GAIN_DEFAULT);
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun 	hi556->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1349*4882a593Smuzhiyun 				&hi556_ctrl_ops, V4L2_CID_TEST_PATTERN,
1350*4882a593Smuzhiyun 				ARRAY_SIZE(hi556_test_pattern_menu) - 1,
1351*4882a593Smuzhiyun 				0, 0, hi556_test_pattern_menu);
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
1354*4882a593Smuzhiyun 				V4L2_CID_HFLIP, 0, 1, 1, 0);
1355*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
1356*4882a593Smuzhiyun 				V4L2_CID_VFLIP, 0, 1, 1, 0);
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	if (handler->error) {
1359*4882a593Smuzhiyun 		ret = handler->error;
1360*4882a593Smuzhiyun 		dev_err(&hi556->client->dev,
1361*4882a593Smuzhiyun 			"Failed to init controls(%d)\n", ret);
1362*4882a593Smuzhiyun 		goto err_free_handler;
1363*4882a593Smuzhiyun 	}
1364*4882a593Smuzhiyun 
1365*4882a593Smuzhiyun 	hi556->subdev.ctrl_handler = handler;
1366*4882a593Smuzhiyun 
1367*4882a593Smuzhiyun 	return 0;
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun err_free_handler:
1370*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(handler);
1371*4882a593Smuzhiyun 
1372*4882a593Smuzhiyun 	return ret;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun 
hi556_check_sensor_id(struct hi556 * hi556,struct i2c_client * client)1375*4882a593Smuzhiyun static int hi556_check_sensor_id(struct hi556 *hi556,
1376*4882a593Smuzhiyun 				  struct i2c_client *client)
1377*4882a593Smuzhiyun {
1378*4882a593Smuzhiyun 	struct device *dev = &hi556->client->dev;
1379*4882a593Smuzhiyun 	u32 id = 0;
1380*4882a593Smuzhiyun 	int ret;
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun 	ret = hi556_read_reg(client, HI556_REG_CHIP_ID,
1383*4882a593Smuzhiyun 			      HI556_REG_VALUE_16BIT, &id);
1384*4882a593Smuzhiyun 	if (id != CHIP_ID) {
1385*4882a593Smuzhiyun 		dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1386*4882a593Smuzhiyun 		return -ENODEV;
1387*4882a593Smuzhiyun 	}
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	dev_info(dev, "Detected Hi%04x sensor\n", CHIP_ID);
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	return 0;
1392*4882a593Smuzhiyun }
1393*4882a593Smuzhiyun 
hi556_configure_regulators(struct hi556 * hi556)1394*4882a593Smuzhiyun static int hi556_configure_regulators(struct hi556 *hi556)
1395*4882a593Smuzhiyun {
1396*4882a593Smuzhiyun 	unsigned int i;
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	for (i = 0; i < HI556_NUM_SUPPLIES; i++)
1399*4882a593Smuzhiyun 		hi556->supplies[i].supply = hi556_supply_names[i];
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&hi556->client->dev,
1402*4882a593Smuzhiyun 				       HI556_NUM_SUPPLIES,
1403*4882a593Smuzhiyun 				       hi556->supplies);
1404*4882a593Smuzhiyun }
1405*4882a593Smuzhiyun 
hi556_parse_of(struct hi556 * hi556)1406*4882a593Smuzhiyun static int hi556_parse_of(struct hi556 *hi556)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun 	struct device *dev = &hi556->client->dev;
1409*4882a593Smuzhiyun 	struct device_node *endpoint;
1410*4882a593Smuzhiyun 	struct fwnode_handle *fwnode;
1411*4882a593Smuzhiyun 	int rval;
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1414*4882a593Smuzhiyun 	if (!endpoint) {
1415*4882a593Smuzhiyun 		dev_err(dev, "Failed to get endpoint\n");
1416*4882a593Smuzhiyun 		return -EINVAL;
1417*4882a593Smuzhiyun 	}
1418*4882a593Smuzhiyun 	fwnode = of_fwnode_handle(endpoint);
1419*4882a593Smuzhiyun 	rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1420*4882a593Smuzhiyun 	if (rval <= 0) {
1421*4882a593Smuzhiyun 		dev_warn(dev, " Get mipi lane num failed!\n");
1422*4882a593Smuzhiyun 		return -1;
1423*4882a593Smuzhiyun 	}
1424*4882a593Smuzhiyun 
1425*4882a593Smuzhiyun 	hi556->lane_num = rval;
1426*4882a593Smuzhiyun 	if (hi556->lane_num == 2) {
1427*4882a593Smuzhiyun 		hi556->cur_mode = &supported_modes_2lane[0];
1428*4882a593Smuzhiyun 		supported_modes = supported_modes_2lane;
1429*4882a593Smuzhiyun 		hi556->cfg_num = ARRAY_SIZE(supported_modes_2lane);
1430*4882a593Smuzhiyun 
1431*4882a593Smuzhiyun 		/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1432*4882a593Smuzhiyun 		hi556->pixel_rate = MIPI_FREQ * 2U * hi556->lane_num / 8U;
1433*4882a593Smuzhiyun 		dev_info(dev, "lane_num(%d)  pixel_rate(%u)\n",
1434*4882a593Smuzhiyun 				 hi556->lane_num, hi556->pixel_rate);
1435*4882a593Smuzhiyun 	} else {
1436*4882a593Smuzhiyun 		dev_err(dev, "unsupported lane_num(%d)\n", hi556->lane_num);
1437*4882a593Smuzhiyun 		return -1;
1438*4882a593Smuzhiyun 	}
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	return 0;
1441*4882a593Smuzhiyun }
1442*4882a593Smuzhiyun 
hi556_probe(struct i2c_client * client,const struct i2c_device_id * id)1443*4882a593Smuzhiyun static int hi556_probe(struct i2c_client *client,
1444*4882a593Smuzhiyun 			const struct i2c_device_id *id)
1445*4882a593Smuzhiyun {
1446*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1447*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1448*4882a593Smuzhiyun 	struct hi556 *hi556;
1449*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1450*4882a593Smuzhiyun 	char facing[2] = "b";
1451*4882a593Smuzhiyun 	int ret;
1452*4882a593Smuzhiyun 
1453*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1454*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
1455*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
1456*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
1457*4882a593Smuzhiyun 
1458*4882a593Smuzhiyun 	hi556 = devm_kzalloc(dev, sizeof(*hi556), GFP_KERNEL);
1459*4882a593Smuzhiyun 	if (!hi556)
1460*4882a593Smuzhiyun 		return -ENOMEM;
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1463*4882a593Smuzhiyun 				   &hi556->module_index);
1464*4882a593Smuzhiyun 	if (ret) {
1465*4882a593Smuzhiyun 		dev_warn(dev, "could not get module index!\n");
1466*4882a593Smuzhiyun 		hi556->module_index = 0;
1467*4882a593Smuzhiyun 	}
1468*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1469*4882a593Smuzhiyun 				       &hi556->module_facing);
1470*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1471*4882a593Smuzhiyun 				       &hi556->module_name);
1472*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1473*4882a593Smuzhiyun 				       &hi556->len_name);
1474*4882a593Smuzhiyun 	if (ret) {
1475*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1476*4882a593Smuzhiyun 		return -EINVAL;
1477*4882a593Smuzhiyun 	}
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	hi556->client = client;
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	hi556->xvclk = devm_clk_get(dev, "xvclk");
1482*4882a593Smuzhiyun 	if (IS_ERR(hi556->xvclk)) {
1483*4882a593Smuzhiyun 		dev_err(dev, "Failed to get xvclk\n");
1484*4882a593Smuzhiyun 		return -EINVAL;
1485*4882a593Smuzhiyun 	}
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 	hi556->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1488*4882a593Smuzhiyun 	if (IS_ERR(hi556->power_gpio))
1489*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun 	hi556->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1492*4882a593Smuzhiyun 	if (IS_ERR(hi556->reset_gpio))
1493*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get reset-gpios, maybe no use\n");
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	hi556->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1496*4882a593Smuzhiyun 	if (IS_ERR(hi556->pwdn_gpio))
1497*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get pwdn-gpios\n");
1498*4882a593Smuzhiyun 
1499*4882a593Smuzhiyun 	ret = hi556_configure_regulators(hi556);
1500*4882a593Smuzhiyun 	if (ret) {
1501*4882a593Smuzhiyun 		dev_err(dev, "Failed to get power regulators\n");
1502*4882a593Smuzhiyun 		return ret;
1503*4882a593Smuzhiyun 	}
1504*4882a593Smuzhiyun 	ret = hi556_parse_of(hi556);
1505*4882a593Smuzhiyun 	if (ret != 0)
1506*4882a593Smuzhiyun 		return -EINVAL;
1507*4882a593Smuzhiyun 
1508*4882a593Smuzhiyun 	hi556->pinctrl = devm_pinctrl_get(dev);
1509*4882a593Smuzhiyun 	if (!IS_ERR(hi556->pinctrl)) {
1510*4882a593Smuzhiyun 		hi556->pins_default =
1511*4882a593Smuzhiyun 			pinctrl_lookup_state(hi556->pinctrl,
1512*4882a593Smuzhiyun 					     OF_CAMERA_PINCTRL_STATE_DEFAULT);
1513*4882a593Smuzhiyun 		if (IS_ERR(hi556->pins_default))
1514*4882a593Smuzhiyun 			dev_err(dev, "could not get default pinstate\n");
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 		hi556->pins_sleep =
1517*4882a593Smuzhiyun 			pinctrl_lookup_state(hi556->pinctrl,
1518*4882a593Smuzhiyun 					     OF_CAMERA_PINCTRL_STATE_SLEEP);
1519*4882a593Smuzhiyun 		if (IS_ERR(hi556->pins_sleep))
1520*4882a593Smuzhiyun 			dev_err(dev, "could not get sleep pinstate\n");
1521*4882a593Smuzhiyun 	}
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	mutex_init(&hi556->mutex);
1524*4882a593Smuzhiyun 
1525*4882a593Smuzhiyun 	sd = &hi556->subdev;
1526*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &hi556_subdev_ops);
1527*4882a593Smuzhiyun 	ret = hi556_initialize_controls(hi556);
1528*4882a593Smuzhiyun 	if (ret)
1529*4882a593Smuzhiyun 		goto err_destroy_mutex;
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 	ret = __hi556_power_on(hi556);
1532*4882a593Smuzhiyun 	if (ret)
1533*4882a593Smuzhiyun 		goto err_free_handler;
1534*4882a593Smuzhiyun 
1535*4882a593Smuzhiyun 	ret = hi556_check_sensor_id(hi556, client);
1536*4882a593Smuzhiyun 	if (ret < 0) {
1537*4882a593Smuzhiyun 		dev_info(&client->dev, "%s(%d) Check id  failed\n"
1538*4882a593Smuzhiyun 				  "check following information:\n"
1539*4882a593Smuzhiyun 				  "Power/PowerDown/Reset/Mclk/I2cBus !!\n",
1540*4882a593Smuzhiyun 				  __func__, __LINE__);
1541*4882a593Smuzhiyun 		goto err_power_off;
1542*4882a593Smuzhiyun 	}
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1545*4882a593Smuzhiyun 	sd->internal_ops = &hi556_internal_ops;
1546*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1547*4882a593Smuzhiyun 		     V4L2_SUBDEV_FL_HAS_EVENTS;
1548*4882a593Smuzhiyun #endif
1549*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1550*4882a593Smuzhiyun 	hi556->pad.flags = MEDIA_PAD_FL_SOURCE;
1551*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1552*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &hi556->pad);
1553*4882a593Smuzhiyun 	if (ret < 0)
1554*4882a593Smuzhiyun 		goto err_power_off;
1555*4882a593Smuzhiyun #endif
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1558*4882a593Smuzhiyun 	if (strcmp(hi556->module_facing, "back") == 0)
1559*4882a593Smuzhiyun 		facing[0] = 'b';
1560*4882a593Smuzhiyun 	else
1561*4882a593Smuzhiyun 		facing[0] = 'f';
1562*4882a593Smuzhiyun 
1563*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1564*4882a593Smuzhiyun 		 hi556->module_index, facing,
1565*4882a593Smuzhiyun 		 HI556_NAME, dev_name(sd->dev));
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(sd);
1568*4882a593Smuzhiyun 	if (ret) {
1569*4882a593Smuzhiyun 		dev_err(dev, "v4l2 async register subdev failed\n");
1570*4882a593Smuzhiyun 		goto err_clean_entity;
1571*4882a593Smuzhiyun 	}
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
1574*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1575*4882a593Smuzhiyun 	pm_runtime_idle(dev);
1576*4882a593Smuzhiyun 
1577*4882a593Smuzhiyun 	return 0;
1578*4882a593Smuzhiyun 
1579*4882a593Smuzhiyun err_clean_entity:
1580*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1581*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1582*4882a593Smuzhiyun #endif
1583*4882a593Smuzhiyun err_power_off:
1584*4882a593Smuzhiyun 	__hi556_power_off(hi556);
1585*4882a593Smuzhiyun err_free_handler:
1586*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&hi556->ctrl_handler);
1587*4882a593Smuzhiyun err_destroy_mutex:
1588*4882a593Smuzhiyun 	mutex_destroy(&hi556->mutex);
1589*4882a593Smuzhiyun 
1590*4882a593Smuzhiyun 	return ret;
1591*4882a593Smuzhiyun }
1592*4882a593Smuzhiyun 
hi556_remove(struct i2c_client * client)1593*4882a593Smuzhiyun static int hi556_remove(struct i2c_client *client)
1594*4882a593Smuzhiyun {
1595*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1596*4882a593Smuzhiyun 	struct hi556 *hi556 = to_hi556(sd);
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1599*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1600*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1601*4882a593Smuzhiyun #endif
1602*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&hi556->ctrl_handler);
1603*4882a593Smuzhiyun 	mutex_destroy(&hi556->mutex);
1604*4882a593Smuzhiyun 
1605*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1606*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&client->dev))
1607*4882a593Smuzhiyun 		__hi556_power_off(hi556);
1608*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	return 0;
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun 
1613*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1614*4882a593Smuzhiyun static const struct of_device_id hi556_of_match[] = {
1615*4882a593Smuzhiyun 	{ .compatible = "hynix,hi556" },
1616*4882a593Smuzhiyun 	{},
1617*4882a593Smuzhiyun };
1618*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hi556_of_match);
1619*4882a593Smuzhiyun #endif
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun static const struct i2c_device_id hi556_match_id[] = {
1622*4882a593Smuzhiyun 	{ "hynix,hi556", 0 },
1623*4882a593Smuzhiyun 	{ },
1624*4882a593Smuzhiyun };
1625*4882a593Smuzhiyun 
1626*4882a593Smuzhiyun static struct i2c_driver hi556_i2c_driver = {
1627*4882a593Smuzhiyun 	.driver = {
1628*4882a593Smuzhiyun 		.name = HI556_NAME,
1629*4882a593Smuzhiyun 		.pm = &hi556_pm_ops,
1630*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(hi556_of_match),
1631*4882a593Smuzhiyun 	},
1632*4882a593Smuzhiyun 	.probe		= &hi556_probe,
1633*4882a593Smuzhiyun 	.remove		= &hi556_remove,
1634*4882a593Smuzhiyun 	.id_table	= hi556_match_id,
1635*4882a593Smuzhiyun };
1636*4882a593Smuzhiyun 
sensor_mod_init(void)1637*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1638*4882a593Smuzhiyun {
1639*4882a593Smuzhiyun 	return i2c_add_driver(&hi556_i2c_driver);
1640*4882a593Smuzhiyun }
1641*4882a593Smuzhiyun 
sensor_mod_exit(void)1642*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1643*4882a593Smuzhiyun {
1644*4882a593Smuzhiyun 	i2c_del_driver(&hi556_i2c_driver);
1645*4882a593Smuzhiyun }
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1648*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun MODULE_DESCRIPTION("Hynix hi556 sensor driver");
1651*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1652*4882a593Smuzhiyun 
1653