xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <mark.yao@rock-chips.com>
 */

#ifndef _ROCKCHIP_VOP_REG_H
#define _ROCKCHIP_VOP_REG_H

/* rk3288 register definition */
#define RK3288_REG_CFG_DONE			0x0000
#define RK3288_VERSION_INFO			0x0004
#define RK3288_SYS_CTRL				0x0008
#define RK3288_SYS_CTRL1			0x000c
#define RK3288_DSP_CTRL0			0x0010
#define RK3288_DSP_CTRL1			0x0014
#define RK3288_DSP_BG				0x0018
#define RK3288_MCU_CTRL				0x001c
#define RK3288_INTR_CTRL0			0x0020
#define RK3288_INTR_CTRL1			0x0024
#define RK3288_WIN0_CTRL0			0x0030
#define RK3288_WIN0_CTRL1			0x0034
#define RK3288_WIN0_COLOR_KEY			0x0038
#define RK3288_WIN0_VIR				0x003c
#define RK3288_WIN0_YRGB_MST			0x0040
#define RK3288_WIN0_CBR_MST			0x0044
#define RK3288_WIN0_ACT_INFO			0x0048
#define RK3288_WIN0_DSP_INFO			0x004c
#define RK3288_WIN0_DSP_ST			0x0050
#define RK3288_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3288_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3288_WIN0_SCL_OFFSET			0x005c
#define RK3288_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3288_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3288_WIN0_FADING_CTRL			0x0068
#define RK3288_WIN0_CTRL2			0x006c

/* win1 register */
#define RK3288_WIN1_CTRL0			0x0070
#define RK3288_WIN1_CTRL1			0x0074
#define RK3288_WIN1_COLOR_KEY			0x0078
#define RK3288_WIN1_VIR				0x007c
#define RK3288_WIN1_YRGB_MST			0x0080
#define RK3288_WIN1_CBR_MST			0x0084
#define RK3288_WIN1_ACT_INFO			0x0088
#define RK3288_WIN1_DSP_INFO			0x008c
#define RK3288_WIN1_DSP_ST			0x0090
#define RK3288_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3288_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3288_WIN1_SCL_OFFSET			0x009c
#define RK3288_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3288_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3288_WIN1_FADING_CTRL			0x00a8
/* win2 register */
#define RK3288_WIN2_CTRL0			0x00b0
#define RK3288_WIN2_CTRL1			0x00b4
#define RK3288_WIN2_VIR0_1			0x00b8
#define RK3288_WIN2_VIR2_3			0x00bc
#define RK3288_WIN2_MST0			0x00c0
#define RK3288_WIN2_DSP_INFO0			0x00c4
#define RK3288_WIN2_DSP_ST0			0x00c8
#define RK3288_WIN2_COLOR_KEY			0x00cc
#define RK3288_WIN2_MST1			0x00d0
#define RK3288_WIN2_DSP_INFO1			0x00d4
#define RK3288_WIN2_DSP_ST1			0x00d8
#define RK3288_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3288_WIN2_MST2			0x00e0
#define RK3288_WIN2_DSP_INFO2			0x00e4
#define RK3288_WIN2_DSP_ST2			0x00e8
#define RK3288_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3288_WIN2_MST3			0x00f0
#define RK3288_WIN2_DSP_INFO3			0x00f4
#define RK3288_WIN2_DSP_ST3			0x00f8
#define RK3288_WIN2_FADING_CTRL			0x00fc
/* win3 register */
#define RK3288_WIN3_CTRL0			0x0100
#define RK3288_WIN3_CTRL1			0x0104
#define RK3288_WIN3_VIR0_1			0x0108
#define RK3288_WIN3_VIR2_3			0x010c
#define RK3288_WIN3_MST0			0x0110
#define RK3288_WIN3_DSP_INFO0			0x0114
#define RK3288_WIN3_DSP_ST0			0x0118
#define RK3288_WIN3_COLOR_KEY			0x011c
#define RK3288_WIN3_MST1			0x0120
#define RK3288_WIN3_DSP_INFO1			0x0124
#define RK3288_WIN3_DSP_ST1			0x0128
#define RK3288_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3288_WIN3_MST2			0x0130
#define RK3288_WIN3_DSP_INFO2			0x0134
#define RK3288_WIN3_DSP_ST2			0x0138
#define RK3288_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3288_WIN3_MST3			0x0140
#define RK3288_WIN3_DSP_INFO3			0x0144
#define RK3288_WIN3_DSP_ST3			0x0148
#define RK3288_WIN3_FADING_CTRL			0x014c
/* hwc register */
#define RK3288_HWC_CTRL0			0x0150
#define RK3288_HWC_CTRL1			0x0154
#define RK3288_HWC_MST				0x0158
#define RK3288_HWC_DSP_ST			0x015c
#define RK3288_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3288_HWC_DST_ALPHA_CTRL		0x0164
#define RK3288_HWC_FADING_CTRL			0x0168
/* post process register */
#define RK3288_POST_DSP_HACT_INFO		0x0170
#define RK3288_POST_DSP_VACT_INFO		0x0174
#define RK3288_POST_SCL_FACTOR_YRGB		0x0178
#define RK3288_POST_SCL_CTRL			0x0180
#define RK3288_POST_DSP_VACT_INFO_F1		0x0184
#define RK3288_DSP_HTOTAL_HS_END		0x0188
#define RK3288_DSP_HACT_ST_END			0x018c
#define RK3288_DSP_VTOTAL_VS_END		0x0190
#define RK3288_DSP_VACT_ST_END			0x0194
#define RK3288_DSP_VS_ST_END_F1			0x0198
#define RK3288_DSP_VACT_ST_END_F1		0x019c

#define RK3288_BCSH_COLOR_BAR			0x01b0
#define RK3288_BCSH_BCS				0x01b4
#define RK3288_BCSH_H				0x01b8
#define RK3288_GRF_SOC_CON15			0x03a4
/* register definition end */

/* rk3368 register definition */
#define RK3368_REG_CFG_DONE			0x0000
#define RK3368_VERSION_INFO			0x0004
#define RK3368_SYS_CTRL				0x0008
#define RK3368_SYS_CTRL1			0x000c
#define RK3368_DSP_CTRL0			0x0010
#define RK3368_DSP_CTRL1			0x0014
#define RK3368_DSP_BG				0x0018
#define RK3368_MCU_CTRL				0x001c
#define RK3368_LINE_FLAG			0x0020
#define RK3368_INTR_EN				0x0024
#define RK3368_INTR_CLEAR			0x0028
#define RK3368_INTR_STATUS			0x002c
#define RK3368_WIN0_CTRL0			0x0030
#define RK3368_WIN0_CTRL1			0x0034
#define RK3368_WIN0_COLOR_KEY			0x0038
#define RK3368_WIN0_VIR				0x003c
#define RK3368_WIN0_YRGB_MST			0x0040
#define RK3368_WIN0_CBR_MST			0x0044
#define RK3368_WIN0_ACT_INFO			0x0048
#define RK3368_WIN0_DSP_INFO			0x004c
#define RK3368_WIN0_DSP_ST			0x0050
#define RK3368_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3368_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3368_WIN0_SCL_OFFSET			0x005c
#define RK3368_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3368_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3368_WIN0_FADING_CTRL			0x0068
#define RK3368_WIN0_CTRL2			0x006c
#define RK3368_WIN1_CTRL0			0x0070
#define RK3368_WIN1_CTRL1			0x0074
#define RK3368_WIN1_COLOR_KEY			0x0078
#define RK3368_WIN1_VIR				0x007c
#define RK3368_WIN1_YRGB_MST			0x0080
#define RK3368_WIN1_CBR_MST			0x0084
#define RK3368_WIN1_ACT_INFO			0x0088
#define RK3368_WIN1_DSP_INFO			0x008c
#define RK3368_WIN1_DSP_ST			0x0090
#define RK3368_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3368_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3368_WIN1_SCL_OFFSET			0x009c
#define RK3368_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3368_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3368_WIN1_FADING_CTRL			0x00a8
#define RK3368_WIN1_CTRL2			0x00ac
#define RK3368_WIN2_CTRL0			0x00b0
#define RK3368_WIN2_CTRL1			0x00b4
#define RK3368_WIN2_VIR0_1			0x00b8
#define RK3368_WIN2_VIR2_3			0x00bc
#define RK3368_WIN2_MST0			0x00c0
#define RK3368_WIN2_DSP_INFO0			0x00c4
#define RK3368_WIN2_DSP_ST0			0x00c8
#define RK3368_WIN2_COLOR_KEY			0x00cc
#define RK3368_WIN2_MST1			0x00d0
#define RK3368_WIN2_DSP_INFO1			0x00d4
#define RK3368_WIN2_DSP_ST1			0x00d8
#define RK3368_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3368_WIN2_MST2			0x00e0
#define RK3368_WIN2_DSP_INFO2			0x00e4
#define RK3368_WIN2_DSP_ST2			0x00e8
#define RK3368_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3368_WIN2_MST3			0x00f0
#define RK3368_WIN2_DSP_INFO3			0x00f4
#define RK3368_WIN2_DSP_ST3			0x00f8
#define RK3368_WIN2_FADING_CTRL			0x00fc
#define RK3368_WIN3_CTRL0			0x0100
#define RK3368_WIN3_CTRL1			0x0104
#define RK3368_WIN3_VIR0_1			0x0108
#define RK3368_WIN3_VIR2_3			0x010c
#define RK3368_WIN3_MST0			0x0110
#define RK3368_WIN3_DSP_INFO0			0x0114
#define RK3368_WIN3_DSP_ST0			0x0118
#define RK3368_WIN3_COLOR_KEY			0x011c
#define RK3368_WIN3_MST1			0x0120
#define RK3368_WIN3_DSP_INFO1			0x0124
#define RK3368_WIN3_DSP_ST1			0x0128
#define RK3368_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3368_WIN3_MST2			0x0130
#define RK3368_WIN3_DSP_INFO2			0x0134
#define RK3368_WIN3_DSP_ST2			0x0138
#define RK3368_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3368_WIN3_MST3			0x0140
#define RK3368_WIN3_DSP_INFO3			0x0144
#define RK3368_WIN3_DSP_ST3			0x0148
#define RK3368_WIN3_FADING_CTRL			0x014c
#define RK3368_HWC_CTRL0			0x0150
#define RK3368_HWC_CTRL1			0x0154
#define RK3368_HWC_MST				0x0158
#define RK3368_HWC_DSP_ST			0x015c
#define RK3368_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3368_HWC_DST_ALPHA_CTRL		0x0164
#define RK3368_HWC_FADING_CTRL			0x0168
#define RK3368_HWC_RESERVED1			0x016c
#define RK3368_POST_DSP_HACT_INFO		0x0170
#define RK3368_POST_DSP_VACT_INFO		0x0174
#define RK3368_POST_SCL_FACTOR_YRGB		0x0178
#define RK3368_POST_RESERVED			0x017c
#define RK3368_POST_SCL_CTRL			0x0180
#define RK3368_POST_DSP_VACT_INFO_F1		0x0184
#define RK3368_DSP_HTOTAL_HS_END		0x0188
#define RK3368_DSP_HACT_ST_END			0x018c
#define RK3368_DSP_VTOTAL_VS_END		0x0190
#define RK3368_DSP_VACT_ST_END			0x0194
#define RK3368_DSP_VS_ST_END_F1			0x0198
#define RK3368_DSP_VACT_ST_END_F1		0x019c
#define RK3368_PWM_CTRL				0x01a0
#define RK3368_PWM_PERIOD_HPR			0x01a4
#define RK3368_PWM_DUTY_LPR			0x01a8
#define RK3368_PWM_CNT				0x01ac
#define RK3368_BCSH_COLOR_BAR			0x01b0
#define RK3368_BCSH_BCS				0x01b4
#define RK3368_BCSH_H				0x01b8
#define RK3368_BCSH_CTRL			0x01bc
#define RK3368_CABC_CTRL0			0x01c0
#define RK3368_CABC_CTRL1			0x01c4
#define RK3368_CABC_CTRL2			0x01c8
#define RK3368_CABC_CTRL3			0x01cc
#define RK3368_CABC_GAUSS_LINE0_0		0x01d0
#define RK3368_CABC_GAUSS_LINE0_1		0x01d4
#define RK3368_CABC_GAUSS_LINE1_0		0x01d8
#define RK3368_CABC_GAUSS_LINE1_1		0x01dc
#define RK3368_CABC_GAUSS_LINE2_0		0x01e0
#define RK3368_CABC_GAUSS_LINE2_1		0x01e4
#define RK3368_FRC_LOWER01_0			0x01e8
#define RK3368_FRC_LOWER01_1			0x01ec
#define RK3368_FRC_LOWER10_0			0x01f0
#define RK3368_FRC_LOWER10_1			0x01f4
#define RK3368_FRC_LOWER11_0			0x01f8
#define RK3368_FRC_LOWER11_1			0x01fc
#define RK3368_IFBDC_CTRL			0x0200
#define RK3368_IFBDC_TILES_NUM			0x0204
#define RK3368_IFBDC_FRAME_RST_CYCLE		0x0208
#define RK3368_IFBDC_BASE_ADDR			0x020c
#define RK3368_IFBDC_MB_SIZE			0x0210
#define RK3368_IFBDC_CMP_INDEX_INIT		0x0214
#define RK3368_IFBDC_VIR			0x0220
#define RK3368_IFBDC_DEBUG0			0x0230
#define RK3368_IFBDC_DEBUG1			0x0234
#define RK3368_LATENCY_CTRL0			0x0250
#define RK3368_RD_MAX_LATENCY_NUM0		0x0254
#define RK3368_RD_LATENCY_THR_NUM0		0x0258
#define RK3368_RD_LATENCY_SAMP_NUM0		0x025c
#define RK3368_WIN0_DSP_BG			0x0260
#define RK3368_WIN1_DSP_BG			0x0264
#define RK3368_WIN2_DSP_BG			0x0268
#define RK3368_WIN3_DSP_BG			0x026c
#define RK3368_SCAN_LINE_NUM			0x0270
#define RK3368_CABC_DEBUG0			0x0274
#define RK3368_CABC_DEBUG1			0x0278
#define RK3368_CABC_DEBUG2			0x027c
#define RK3368_DBG_REG_000			0x0280
#define RK3368_DBG_REG_001			0x0284
#define RK3368_DBG_REG_002			0x0288
#define RK3368_DBG_REG_003			0x028c
#define RK3368_DBG_REG_004			0x0290
#define RK3368_DBG_REG_005			0x0294
#define RK3368_DBG_REG_006			0x0298
#define RK3368_DBG_REG_007			0x029c
#define RK3368_DBG_REG_008			0x02a0
#define RK3368_DBG_REG_016			0x02c0
#define RK3368_DBG_REG_017			0x02c4
#define RK3368_DBG_REG_018			0x02c8
#define RK3368_DBG_REG_019			0x02cc
#define RK3368_DBG_REG_020			0x02d0
#define RK3368_DBG_REG_021			0x02d4
#define RK3368_DBG_REG_022			0x02d8
#define RK3368_DBG_REG_023			0x02dc
#define RK3368_DBG_REG_028			0x02f0
#define RK3368_MMU_DTE_ADDR			0x0300
#define RK3368_MMU_STATUS			0x0304
#define RK3368_MMU_COMMAND			0x0308
#define RK3368_MMU_PAGE_FAULT_ADDR		0x030c
#define RK3368_MMU_ZAP_ONE_LINE			0x0310
#define RK3368_MMU_INT_RAWSTAT			0x0314
#define RK3368_MMU_INT_CLEAR			0x0318
#define RK3368_MMU_INT_MASK			0x031c
#define RK3368_MMU_INT_STATUS			0x0320
#define RK3368_MMU_AUTO_GATING			0x0324
#define RK3368_WIN2_LUT_ADDR			0x0400
#define RK3368_WIN3_LUT_ADDR			0x0800
#define RK3368_HWC_LUT_ADDR			0x0c00
#define RK3368_GAMMA_LUT_ADDR			0x1000
#define RK3368_CABC_GAMMA_LUT_ADDR		0x1800
#define RK3368_MCU_BYPASS_WPORT			0x2200
#define RK3368_MCU_BYPASS_RPORT			0x2300
#define RK3368_GRF_SOC_CON6			0x0418
/* rk3368 register definition end */

#define RK3366_REG_CFG_DONE			0x0000
#define RK3366_VERSION_INFO			0x0004
#define RK3366_SYS_CTRL				0x0008
#define RK3366_SYS_CTRL1			0x000c
#define RK3366_DSP_CTRL0			0x0010
#define RK3366_DSP_CTRL1			0x0014
#define RK3366_DSP_BG				0x0018
#define RK3366_MCU_CTRL				0x001c
#define RK3366_WB_CTRL0				0x0020
#define RK3366_WB_CTRL1				0x0024
#define RK3366_WB_YRGB_MST			0x0028
#define RK3366_WB_CBR_MST			0x002c
#define RK3366_WIN0_CTRL0			0x0030
#define RK3366_WIN0_CTRL1			0x0034
#define RK3366_WIN0_COLOR_KEY			0x0038
#define RK3366_WIN0_VIR				0x003c
#define RK3366_WIN0_YRGB_MST			0x0040
#define RK3366_WIN0_CBR_MST			0x0044
#define RK3366_WIN0_ACT_INFO			0x0048
#define RK3366_WIN0_DSP_INFO			0x004c
#define RK3366_WIN0_DSP_ST			0x0050
#define RK3366_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3366_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3366_WIN0_SCL_OFFSET			0x005c
#define RK3366_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3366_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3366_WIN0_FADING_CTRL			0x0068
#define RK3366_WIN0_CTRL2			0x006c
#define RK3366_WIN1_CTRL0			0x0070
#define RK3366_WIN1_CTRL1			0x0074
#define RK3366_WIN1_COLOR_KEY			0x0078
#define RK3366_WIN1_VIR				0x007c
#define RK3366_WIN1_YRGB_MST			0x0080
#define RK3366_WIN1_CBR_MST			0x0084
#define RK3366_WIN1_ACT_INFO			0x0088
#define RK3366_WIN1_DSP_INFO			0x008c
#define RK3366_WIN1_DSP_ST			0x0090
#define RK3366_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3366_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3366_WIN1_SCL_OFFSET			0x009c
#define RK3366_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3366_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3366_WIN1_FADING_CTRL			0x00a8
#define RK3366_WIN1_CTRL2			0x00ac
#define RK3366_WIN2_CTRL0			0x00b0
#define RK3366_WIN2_CTRL1			0x00b4
#define RK3366_WIN2_VIR0_1			0x00b8
#define RK3366_WIN2_VIR2_3			0x00bc
#define RK3366_WIN2_MST0			0x00c0
#define RK3366_WIN2_DSP_INFO0			0x00c4
#define RK3366_WIN2_DSP_ST0			0x00c8
#define RK3366_WIN2_COLOR_KEY			0x00cc
#define RK3366_WIN2_MST1			0x00d0
#define RK3366_WIN2_DSP_INFO1			0x00d4
#define RK3366_WIN2_DSP_ST1			0x00d8
#define RK3366_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3366_WIN2_MST2			0x00e0
#define RK3366_WIN2_DSP_INFO2			0x00e4
#define RK3366_WIN2_DSP_ST2			0x00e8
#define RK3366_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3366_WIN2_MST3			0x00f0
#define RK3366_WIN2_DSP_INFO3			0x00f4
#define RK3366_WIN2_DSP_ST3			0x00f8
#define RK3366_WIN2_FADING_CTRL			0x00fc
#define RK3366_WIN3_CTRL0			0x0100
#define RK3366_WIN3_CTRL1			0x0104
#define RK3366_WIN3_VIR0_1			0x0108
#define RK3366_WIN3_VIR2_3			0x010c
#define RK3366_WIN3_MST0			0x0110
#define RK3366_WIN3_DSP_INFO0			0x0114
#define RK3366_WIN3_DSP_ST0			0x0118
#define RK3366_WIN3_COLOR_KEY			0x011c
#define RK3366_WIN3_MST1			0x0120
#define RK3366_WIN3_DSP_INFO1			0x0124
#define RK3366_WIN3_DSP_ST1			0x0128
#define RK3366_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3366_WIN3_MST2			0x0130
#define RK3366_WIN3_DSP_INFO2			0x0134
#define RK3366_WIN3_DSP_ST2			0x0138
#define RK3366_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3366_WIN3_MST3			0x0140
#define RK3366_WIN3_DSP_INFO3			0x0144
#define RK3366_WIN3_DSP_ST3			0x0148
#define RK3366_WIN3_FADING_CTRL			0x014c
#define RK3366_HWC_CTRL0			0x0150
#define RK3366_HWC_CTRL1			0x0154
#define RK3366_HWC_MST				0x0158
#define RK3366_HWC_DSP_ST			0x015c
#define RK3366_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3366_HWC_DST_ALPHA_CTRL		0x0164
#define RK3366_HWC_FADING_CTRL			0x0168
#define RK3366_HWC_RESERVED1			0x016c
#define RK3366_POST_DSP_HACT_INFO		0x0170
#define RK3366_POST_DSP_VACT_INFO		0x0174
#define RK3366_POST_SCL_FACTOR_YRGB		0x0178
#define RK3366_POST_RESERVED			0x017c
#define RK3366_POST_SCL_CTRL			0x0180
#define RK3366_POST_DSP_VACT_INFO_F1		0x0184
#define RK3366_DSP_HTOTAL_HS_END		0x0188
#define RK3366_DSP_HACT_ST_END			0x018c
#define RK3366_DSP_VTOTAL_VS_END		0x0190
#define RK3366_DSP_VACT_ST_END			0x0194
#define RK3366_DSP_VS_ST_END_F1			0x0198
#define RK3366_DSP_VACT_ST_END_F1		0x019c
#define RK3366_PWM_CTRL				0x01a0
#define RK3366_PWM_PERIOD_HPR			0x01a4
#define RK3366_PWM_DUTY_LPR			0x01a8
#define RK3366_PWM_CNT				0x01ac
#define RK3366_BCSH_COLOR_BAR			0x01b0
#define RK3366_BCSH_BCS				0x01b4
#define RK3366_BCSH_H				0x01b8
#define RK3366_BCSH_CTRL			0x01bc
#define RK3366_CABC_CTRL0			0x01c0
#define RK3366_CABC_CTRL1			0x01c4
#define RK3366_CABC_CTRL2			0x01c8
#define RK3366_CABC_CTRL3			0x01cc
#define RK3366_CABC_GAUSS_LINE0_0		0x01d0
#define RK3366_CABC_GAUSS_LINE0_1		0x01d4
#define RK3366_CABC_GAUSS_LINE1_0		0x01d8
#define RK3366_CABC_GAUSS_LINE1_1		0x01dc
#define RK3366_CABC_GAUSS_LINE2_0		0x01e0
#define RK3366_CABC_GAUSS_LINE2_1		0x01e4
#define RK3366_FRC_LOWER01_0			0x01e8
#define RK3366_FRC_LOWER01_1			0x01ec
#define RK3366_FRC_LOWER10_0			0x01f0
#define RK3366_FRC_LOWER10_1			0x01f4
#define RK3366_FRC_LOWER11_0			0x01f8
#define RK3366_FRC_LOWER11_1			0x01fc
#define RK3366_INTR_EN0				0x0280
#define RK3366_INTR_CLEAR0			0x0284
#define RK3366_INTR_STATUS0			0x0288
#define RK3366_INTR_RAW_STATUS0			0x028c
#define RK3366_INTR_EN1				0x0290
#define RK3366_INTR_CLEAR1			0x0294
#define RK3366_INTR_STATUS1			0x0298
#define RK3366_INTR_RAW_STATUS1			0x029c
#define RK3366_LINE_FLAG			0x02a0
#define RK3366_VOP_STATUS			0x02a4
#define RK3366_BLANKING_VALUE			0x02a8
#define RK3366_WIN0_DSP_BG			0x02b0
#define RK3366_WIN1_DSP_BG			0x02b4
#define RK3366_WIN2_DSP_BG			0x02b8
#define RK3366_WIN3_DSP_BG			0x02bc
#define RK3366_WIN2_LUT_ADDR			0x0400
#define RK3366_WIN3_LUT_ADDR			0x0800
#define RK3366_HWC_LUT_ADDR			0x0c00
#define RK3366_GAMMA0_LUT_ADDR			0x1000
#define RK3366_GAMMA1_LUT_ADDR			0x1400
#define RK3366_CABC_GAMMA_LUT_ADDR		0x1800
#define RK3366_MCU_BYPASS_WPORT			0x2200
#define RK3366_MCU_BYPASS_RPORT			0x2300
#define RK3366_MMU_DTE_ADDR			0x2400
#define RK3366_MMU_STATUS			0x2404
#define RK3366_MMU_COMMAND			0x2408
#define RK3366_MMU_PAGE_FAULT_ADDR		0x240c
#define RK3366_MMU_ZAP_ONE_LINE			0x2410
#define RK3366_MMU_INT_RAWSTAT			0x2414
#define RK3366_MMU_INT_CLEAR			0x2418
#define RK3366_MMU_INT_MASK			0x241c
#define RK3366_MMU_INT_STATUS			0x2420
#define RK3366_MMU_AUTO_GATING			0x2424

/* rk3399 register definition */
#define RK3399_REG_CFG_DONE			0x0000
#define RK3399_VERSION_INFO			0x0004
#define RK3399_SYS_CTRL				0x0008
#define RK3399_SYS_CTRL1			0x000c
#define RK3399_DSP_CTRL0			0x0010
#define RK3399_DSP_CTRL1			0x0014
#define RK3399_DSP_BG				0x0018
#define RK3399_MCU_CTRL				0x001c
#define RK3399_WB_CTRL0				0x0020
#define RK3399_WB_CTRL1				0x0024
#define RK3399_WB_YRGB_MST			0x0028
#define RK3399_WB_CBR_MST			0x002c
#define RK3399_WIN0_CTRL0			0x0030
#define RK3399_WIN0_CTRL1			0x0034
#define RK3399_WIN0_COLOR_KEY			0x0038
#define RK3399_WIN0_VIR				0x003c
#define RK3399_WIN0_YRGB_MST			0x0040
#define RK3399_WIN0_CBR_MST			0x0044
#define RK3399_WIN0_ACT_INFO			0x0048
#define RK3399_WIN0_DSP_INFO			0x004c
#define RK3399_WIN0_DSP_ST			0x0050
#define RK3399_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3399_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3399_WIN0_SCL_OFFSET			0x005c
#define RK3399_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3399_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3399_WIN0_FADING_CTRL			0x0068
#define RK3399_WIN0_CTRL2			0x006c
#define RK3399_WIN1_CTRL0			0x0070
#define RK3399_WIN1_CTRL1			0x0074
#define RK3399_WIN1_COLOR_KEY			0x0078
#define RK3399_WIN1_VIR				0x007c
#define RK3399_WIN1_YRGB_MST			0x0080
#define RK3399_WIN1_CBR_MST			0x0084
#define RK3399_WIN1_ACT_INFO			0x0088
#define RK3399_WIN1_DSP_INFO			0x008c
#define RK3399_WIN1_DSP_ST			0x0090
#define RK3399_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3399_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3399_WIN1_SCL_OFFSET			0x009c
#define RK3399_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3399_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3399_WIN1_FADING_CTRL			0x00a8
#define RK3399_WIN1_CTRL2			0x00ac
#define RK3399_WIN2_CTRL0			0x00b0
#define RK3399_WIN2_CTRL1			0x00b4
#define RK3399_WIN2_VIR0_1			0x00b8
#define RK3399_WIN2_VIR2_3			0x00bc
#define RK3399_WIN2_MST0			0x00c0
#define RK3399_WIN2_DSP_INFO0			0x00c4
#define RK3399_WIN2_DSP_ST0			0x00c8
#define RK3399_WIN2_COLOR_KEY			0x00cc
#define RK3399_WIN2_MST1			0x00d0
#define RK3399_WIN2_DSP_INFO1			0x00d4
#define RK3399_WIN2_DSP_ST1			0x00d8
#define RK3399_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3399_WIN2_MST2			0x00e0
#define RK3399_WIN2_DSP_INFO2			0x00e4
#define RK3399_WIN2_DSP_ST2			0x00e8
#define RK3399_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3399_WIN2_MST3			0x00f0
#define RK3399_WIN2_DSP_INFO3			0x00f4
#define RK3399_WIN2_DSP_ST3			0x00f8
#define RK3399_WIN2_FADING_CTRL			0x00fc
#define RK3399_WIN3_CTRL0			0x0100
#define RK3399_WIN3_CTRL1			0x0104
#define RK3399_WIN3_VIR0_1			0x0108
#define RK3399_WIN3_VIR2_3			0x010c
#define RK3399_WIN3_MST0			0x0110
#define RK3399_WIN3_DSP_INFO0			0x0114
#define RK3399_WIN3_DSP_ST0			0x0118
#define RK3399_WIN3_COLOR_KEY			0x011c
#define RK3399_WIN3_MST1			0x0120
#define RK3399_WIN3_DSP_INFO1			0x0124
#define RK3399_WIN3_DSP_ST1			0x0128
#define RK3399_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3399_WIN3_MST2			0x0130
#define RK3399_WIN3_DSP_INFO2			0x0134
#define RK3399_WIN3_DSP_ST2			0x0138
#define RK3399_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3399_WIN3_MST3			0x0140
#define RK3399_WIN3_DSP_INFO3			0x0144
#define RK3399_WIN3_DSP_ST3			0x0148
#define RK3399_WIN3_FADING_CTRL			0x014c
#define RK3399_HWC_CTRL0			0x0150
#define RK3399_HWC_CTRL1			0x0154
#define RK3399_HWC_MST				0x0158
#define RK3399_HWC_DSP_ST			0x015c
#define RK3399_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3399_HWC_DST_ALPHA_CTRL		0x0164
#define RK3399_HWC_FADING_CTRL			0x0168
#define RK3399_HWC_RESERVED1			0x016c
#define RK3399_POST_DSP_HACT_INFO		0x0170
#define RK3399_POST_DSP_VACT_INFO		0x0174
#define RK3399_POST_SCL_FACTOR_YRGB		0x0178
#define RK3399_POST_RESERVED			0x017c
#define RK3399_POST_SCL_CTRL			0x0180
#define RK3399_POST_DSP_VACT_INFO_F1		0x0184
#define RK3399_DSP_HTOTAL_HS_END		0x0188
#define RK3399_DSP_HACT_ST_END			0x018c
#define RK3399_DSP_VTOTAL_VS_END		0x0190
#define RK3399_DSP_VACT_ST_END			0x0194
#define RK3399_DSP_VS_ST_END_F1			0x0198
#define RK3399_DSP_VACT_ST_END_F1		0x019c
#define RK3399_PWM_CTRL				0x01a0
#define RK3399_PWM_PERIOD_HPR			0x01a4
#define RK3399_PWM_DUTY_LPR			0x01a8
#define RK3399_PWM_CNT				0x01ac
#define RK3399_BCSH_COLOR_BAR			0x01b0
#define RK3399_BCSH_BCS				0x01b4
#define RK3399_BCSH_H				0x01b8
#define RK3399_BCSH_CTRL			0x01bc
#define RK3399_CABC_CTRL0			0x01c0
#define RK3399_CABC_CTRL1			0x01c4
#define RK3399_CABC_CTRL2			0x01c8
#define RK3399_CABC_CTRL3			0x01cc
#define RK3399_CABC_GAUSS_LINE0_0		0x01d0
#define RK3399_CABC_GAUSS_LINE0_1		0x01d4
#define RK3399_CABC_GAUSS_LINE1_0		0x01d8
#define RK3399_CABC_GAUSS_LINE1_1		0x01dc
#define RK3399_CABC_GAUSS_LINE2_0		0x01e0
#define RK3399_CABC_GAUSS_LINE2_1		0x01e4
#define RK3399_FRC_LOWER01_0			0x01e8
#define RK3399_FRC_LOWER01_1			0x01ec
#define RK3399_FRC_LOWER10_0			0x01f0
#define RK3399_FRC_LOWER10_1			0x01f4
#define RK3399_FRC_LOWER11_0			0x01f8
#define RK3399_FRC_LOWER11_1			0x01fc
#define RK3399_AFBCD0_CTRL			0x0200
#define RK3399_AFBCD0_HDR_PTR			0x0204
#define RK3399_AFBCD0_PIC_SIZE			0x0208
#define RK3399_AFBCD0_STATUS			0x020c
#define RK3399_AFBCD1_CTRL			0x0220
#define RK3399_AFBCD1_HDR_PTR			0x0224
#define RK3399_AFBCD1_PIC_SIZE			0x0228
#define RK3399_AFBCD1_STATUS			0x022c
#define RK3399_AFBCD2_CTRL			0x0240
#define RK3399_AFBCD2_HDR_PTR			0x0244
#define RK3399_AFBCD2_PIC_SIZE			0x0248
#define RK3399_AFBCD2_STATUS			0x024c
#define RK3399_AFBCD3_CTRL			0x0260
#define RK3399_AFBCD3_HDR_PTR			0x0264
#define RK3399_AFBCD3_PIC_SIZE			0x0268
#define RK3399_AFBCD3_STATUS			0x026c
#define RK3399_INTR_EN0				0x0280
#define RK3399_INTR_CLEAR0			0x0284
#define RK3399_INTR_STATUS0			0x0288
#define RK3399_INTR_RAW_STATUS0			0x028c
#define RK3399_INTR_EN1				0x0290
#define RK3399_INTR_CLEAR1			0x0294
#define RK3399_INTR_STATUS1			0x0298
#define RK3399_INTR_RAW_STATUS1			0x029c
#define RK3399_LINE_FLAG			0x02a0
#define RK3399_VOP_STATUS			0x02a4
#define RK3399_BLANKING_VALUE			0x02a8
#define RK3399_MCU_BYPASS_PORT			0x02ac
#define RK3399_WIN0_DSP_BG			0x02b0
#define RK3399_WIN1_DSP_BG			0x02b4
#define RK3399_WIN2_DSP_BG			0x02b8
#define RK3399_WIN3_DSP_BG			0x02bc
#define RK3399_YUV2YUV_WIN			0x02c0
#define RK3399_YUV2YUV_POST			0x02c4
#define RK3399_AUTO_GATING_EN			0x02cc
#define RK3399_DBG_POST_REG1			0x036c
#define RK3399_WIN0_CSC_COE			0x03a0
#define RK3399_WIN1_CSC_COE			0x03c0
#define RK3399_WIN2_CSC_COE			0x03e0
#define RK3399_WIN3_CSC_COE			0x0400
#define RK3399_HWC_CSC_COE			0x0420
#define RK3399_BCSH_R2Y_CSC_COE			0x0440
#define RK3399_BCSH_Y2R_CSC_COE			0x0460
#define RK3399_POST_YUV2YUV_Y2R_COE		0x0480
#define RK3399_POST_YUV2YUV_3X3_COE		0x04a0
#define RK3399_POST_YUV2YUV_R2Y_COE		0x04c0
#define RK3399_WIN0_YUV2YUV_Y2R			0x04e0
#define RK3399_WIN0_YUV2YUV_3X3			0x0500
#define RK3399_WIN0_YUV2YUV_R2Y			0x0520
#define RK3399_WIN1_YUV2YUV_Y2R			0x0540
#define RK3399_WIN1_YUV2YUV_3X3			0x0560
#define RK3399_WIN1_YUV2YUV_R2Y			0x0580
#define RK3399_WIN2_YUV2YUV_Y2R			0x05a0
#define RK3399_WIN2_YUV2YUV_3X3			0x05c0
#define RK3399_WIN2_YUV2YUV_R2Y			0x05e0
#define RK3399_WIN3_YUV2YUV_Y2R			0x0600
#define RK3399_WIN3_YUV2YUV_3X3			0x0620
#define RK3399_WIN3_YUV2YUV_R2Y			0x0640
#define RK3399_WIN2_LUT_ADDR			0x1000
#define RK3399_WIN3_LUT_ADDR			0x1400
#define RK3399_HWC_LUT_ADDR			0x1800
#define RK3399_CABC_GAMMA_LUT_ADDR		0x1c00
#define RK3399_GAMMA_LUT_ADDR			0x2000
/* rk3399 register definition end */

/* rk3328 register definition end */
#define RK3328_REG_CFG_DONE			0x00000000
#define RK3328_VERSION_INFO			0x00000004
#define RK3328_SYS_CTRL				0x00000008
#define RK3328_SYS_CTRL1			0x0000000c
#define RK3328_DSP_CTRL0			0x00000010
#define RK3328_DSP_CTRL1			0x00000014
#define RK3328_DSP_BG				0x00000018
#define RK3328_AUTO_GATING_EN			0x0000003c
#define RK3328_LINE_FLAG			0x00000040
#define RK3328_VOP_STATUS			0x00000044
#define RK3328_BLANKING_VALUE			0x00000048
#define RK3328_WIN0_DSP_BG			0x00000050
#define RK3328_WIN1_DSP_BG			0x00000054
#define RK3328_DBG_PERF_LATENCY_CTRL0		0x000000c0
#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0	0x000000c4
#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0	0x000000c8
#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0	0x000000cc
#define RK3328_INTR_EN0				0x000000e0
#define RK3328_INTR_CLEAR0			0x000000e4
#define RK3328_INTR_STATUS0			0x000000e8
#define RK3328_INTR_RAW_STATUS0			0x000000ec
#define RK3328_INTR_EN1				0x000000f0
#define RK3328_INTR_CLEAR1			0x000000f4
#define RK3328_INTR_STATUS1			0x000000f8
#define RK3328_INTR_RAW_STATUS1			0x000000fc
#define RK3328_WIN0_CTRL0			0x00000100
#define RK3328_WIN0_CTRL1			0x00000104
#define RK3328_WIN0_COLOR_KEY			0x00000108
#define RK3328_WIN0_VIR				0x0000010c
#define RK3328_WIN0_YRGB_MST			0x00000110
#define RK3328_WIN0_CBR_MST			0x00000114
#define RK3328_WIN0_ACT_INFO			0x00000118
#define RK3328_WIN0_DSP_INFO			0x0000011c
#define RK3328_WIN0_DSP_ST			0x00000120
#define RK3328_WIN0_SCL_FACTOR_YRGB		0x00000124
#define RK3328_WIN0_SCL_FACTOR_CBR		0x00000128
#define RK3328_WIN0_SCL_OFFSET			0x0000012c
#define RK3328_WIN0_SRC_ALPHA_CTRL		0x00000130
#define RK3328_WIN0_DST_ALPHA_CTRL		0x00000134
#define RK3328_WIN0_FADING_CTRL			0x00000138
#define RK3328_WIN0_CTRL2			0x0000013c
#define RK3328_DBG_WIN0_REG0			0x000001f0
#define RK3328_DBG_WIN0_REG1			0x000001f4
#define RK3328_DBG_WIN0_REG2			0x000001f8
#define RK3328_DBG_WIN0_RESERVED		0x000001fc
#define RK3328_WIN1_CTRL0			0x00000200
#define RK3328_WIN1_CTRL1			0x00000204
#define RK3328_WIN1_COLOR_KEY			0x00000208
#define RK3328_WIN1_VIR				0x0000020c
#define RK3328_WIN1_YRGB_MST			0x00000210
#define RK3328_WIN1_CBR_MST			0x00000214
#define RK3328_WIN1_ACT_INFO			0x00000218
#define RK3328_WIN1_DSP_INFO			0x0000021c
#define RK3328_WIN1_DSP_ST			0x00000220
#define RK3328_WIN1_SCL_FACTOR_YRGB		0x00000224
#define RK3328_WIN1_SCL_FACTOR_CBR		0x00000228
#define RK3328_WIN1_SCL_OFFSET			0x0000022c
#define RK3328_WIN1_SRC_ALPHA_CTRL		0x00000230
#define RK3328_WIN1_DST_ALPHA_CTRL		0x00000234
#define RK3328_WIN1_FADING_CTRL			0x00000238
#define RK3328_WIN1_CTRL2			0x0000023c
#define RK3328_DBG_WIN1_REG0			0x000002f0
#define RK3328_DBG_WIN1_REG1			0x000002f4
#define RK3328_DBG_WIN1_REG2			0x000002f8
#define RK3328_DBG_WIN1_RESERVED		0x000002fc
#define RK3328_WIN2_CTRL0			0x00000300
#define RK3328_WIN2_CTRL1			0x00000304
#define RK3328_WIN2_COLOR_KEY			0x00000308
#define RK3328_WIN2_VIR				0x0000030c
#define RK3328_WIN2_YRGB_MST			0x00000310
#define RK3328_WIN2_CBR_MST			0x00000314
#define RK3328_WIN2_ACT_INFO			0x00000318
#define RK3328_WIN2_DSP_INFO			0x0000031c
#define RK3328_WIN2_DSP_ST			0x00000320
#define RK3328_WIN2_SCL_FACTOR_YRGB		0x00000324
#define RK3328_WIN2_SCL_FACTOR_CBR		0x00000328
#define RK3328_WIN2_SCL_OFFSET			0x0000032c
#define RK3328_WIN2_SRC_ALPHA_CTRL		0x00000330
#define RK3328_WIN2_DST_ALPHA_CTRL		0x00000334
#define RK3328_WIN2_FADING_CTRL			0x00000338
#define RK3328_WIN2_CTRL2			0x0000033c
#define RK3328_DBG_WIN2_REG0			0x000003f0
#define RK3328_DBG_WIN2_REG1			0x000003f4
#define RK3328_DBG_WIN2_REG2			0x000003f8
#define RK3328_DBG_WIN2_RESERVED		0x000003fc
#define RK3328_WIN3_CTRL0			0x00000400
#define RK3328_WIN3_CTRL1			0x00000404
#define RK3328_WIN3_COLOR_KEY			0x00000408
#define RK3328_WIN3_VIR				0x0000040c
#define RK3328_WIN3_YRGB_MST			0x00000410
#define RK3328_WIN3_CBR_MST			0x00000414
#define RK3328_WIN3_ACT_INFO			0x00000418
#define RK3328_WIN3_DSP_INFO			0x0000041c
#define RK3328_WIN3_DSP_ST			0x00000420
#define RK3328_WIN3_SCL_FACTOR_YRGB		0x00000424
#define RK3328_WIN3_SCL_FACTOR_CBR		0x00000428
#define RK3328_WIN3_SCL_OFFSET			0x0000042c
#define RK3328_WIN3_SRC_ALPHA_CTRL		0x00000430
#define RK3328_WIN3_DST_ALPHA_CTRL		0x00000434
#define RK3328_WIN3_FADING_CTRL			0x00000438
#define RK3328_WIN3_CTRL2			0x0000043c
#define RK3328_DBG_WIN3_REG0			0x000004f0
#define RK3328_DBG_WIN3_REG1			0x000004f4
#define RK3328_DBG_WIN3_REG2			0x000004f8
#define RK3328_DBG_WIN3_RESERVED		0x000004fc

#define RK3328_HWC_CTRL0			0x00000500
#define RK3328_HWC_CTRL1			0x00000504
#define RK3328_HWC_MST				0x00000508
#define RK3328_HWC_DSP_ST			0x0000050c
#define RK3328_HWC_SRC_ALPHA_CTRL		0x00000510
#define RK3328_HWC_DST_ALPHA_CTRL		0x00000514
#define RK3328_HWC_FADING_CTRL			0x00000518
#define RK3328_HWC_RESERVED1			0x0000051c
#define RK3328_POST_DSP_HACT_INFO		0x00000600
#define RK3328_POST_DSP_VACT_INFO		0x00000604
#define RK3328_POST_SCL_FACTOR_YRGB		0x00000608
#define RK3328_POST_RESERVED			0x0000060c
#define RK3328_POST_SCL_CTRL			0x00000610
#define RK3328_POST_DSP_VACT_INFO_F1		0x00000614
#define RK3328_DSP_HTOTAL_HS_END		0x00000618
#define RK3328_DSP_HACT_ST_END			0x0000061c
#define RK3328_DSP_VTOTAL_VS_END		0x00000620
#define RK3328_DSP_VACT_ST_END			0x00000624
#define RK3328_DSP_VS_ST_END_F1			0x00000628
#define RK3328_DSP_VACT_ST_END_F1		0x0000062c
#define RK3328_BCSH_COLOR_BAR			0x00000640
#define RK3328_BCSH_BCS				0x00000644
#define RK3328_BCSH_H				0x00000648
#define RK3328_BCSH_CTRL			0x0000064c
#define RK3328_FRC_LOWER01_0			0x00000678
#define RK3328_FRC_LOWER01_1			0x0000067c
#define RK3328_FRC_LOWER10_0			0x00000680
#define RK3328_FRC_LOWER10_1			0x00000684
#define RK3328_FRC_LOWER11_0			0x00000688
#define RK3328_FRC_LOWER11_1			0x0000068c
#define RK3328_DBG_POST_REG0			0x000006e8
#define RK3328_DBG_POST_RESERVED		0x000006ec
#define RK3328_DBG_DATAO			0x000006f0
#define RK3328_DBG_DATAO_2			0x000006f4
#define RK3328_SDR2HDR_CTRL			0x00000700
#define RK3328_SDR2HDR_EOTF_OETF_Y0		0x00000704
#define RK3328_SDR2HDR_EOTF_OETF_Y1		0x00000710
#define RK3328_SDR2HDR_OETF_DX_DXPOW1		0x00000810
#define RK3328_SDR2HDR_OETF_XN1			0x00000910

#define RK3328_HDR2DR_CTRL			0x00000a10
#define RK3328_HDR2DR_SRC_RANGE			0x00000a14
#define RK3328_HDR2DR_NORMFACEETF		0x00000a18
#define RK3328_HDR2DR_DST_RANGE			0x00000a20
#define RK3328_HDR2DR_NORMFACGAMMA		0x00000a24
#define RK3328_HDR2SDR_EETF_OETF_Y0		0x00000a28
#define RK3328_HDR2DR_SAT_Y0			0x00000a2C
#define RK3328_HDR2SDR_EETF_OETF_Y1		0x00000a30
#define RK3328_HDR2DR_SAT_Y1			0x00000ab0

/* sdr to hdr */
#define RK3328_SDR2HDR_CTRL			0x00000700
#define RK3328_EOTF_OETF_Y0			0x00000704
#define RK3328_RESERVED0001			0x00000708
#define RK3328_RESERVED0002			0x0000070c
#define RK3328_EOTF_OETF_Y1			0x00000710
#define RK3328_EOTF_OETF_Y64			0x0000080c
#define RK3328_OETF_DX_DXPOW1			0x00000810
#define RK3328_OETF_DX_DXPOW64			0x0000090c
#define RK3328_OETF_XN1				0x00000910
#define RK3328_OETF_XN63			0x00000a08

/* hdr to sdr */
#define RK3328_HDR2SDR_CTRL			0x00000a10
#define RK3328_HDR2SDR_SRC_RANGE		0x00000a14
#define RK3328_HDR2SDR_NORMFACEETF		0x00000a18
#define RK3328_RESERVED0003			0x00000a1c
#define RK3328_HDR2SDR_DST_RANGE		0x00000a20
#define RK3328_HDR2SDR_NORMFACCGAMMA		0x00000a24
#define RK3328_EETF_OETF_Y0			0x00000a28
#define RK3328_SAT_Y0				0x00000a2c
#define RK3328_EETF_OETF_Y1			0x00000a30
#define RK3328_SAT_Y1				0x00000ab0
#define RK3328_SAT_Y8				0x00000acc

#define RK3328_HWC_LUT_ADDR			0x00000c00

/* rk3036 register definition */
#define RK3036_SYS_CTRL			0x00
#define RK3036_DSP_CTRL0		0x04
#define RK3036_DSP_CTRL1		0x08
#define RK3036_INT_SCALER		0x0c
#define RK3036_INT_STATUS		0x10
#define RK3036_ALPHA_CTRL		0x14
#define RK3036_WIN0_COLOR_KEY		0x18
#define RK3036_WIN1_COLOR_KEY		0x1c
#define RK3036_WIN0_YRGB_MST		0x20
#define RK3036_WIN0_CBR_MST		0x24
#define RK3036_WIN1_VIR			0x28
#define RK3036_AXI_BUS_CTRL		0x2c
#define RK3036_WIN0_VIR			0x30
#define RK3036_WIN0_ACT_INFO		0x34
#define RK3036_WIN0_DSP_INFO		0x38
#define RK3036_WIN0_DSP_ST		0x3c
#define RK3036_WIN0_SCL_FACTOR_YRGB	0x40
#define RK3036_WIN0_SCL_FACTOR_CBR	0x44
#define RK3036_WIN0_SCL_OFFSET		0x48
#define RK3036_HWC_MST			0x58
#define RK3036_HWC_DSP_ST		0x5c
#define RK3036_DSP_HTOTAL_HS_END	0x6c
#define RK3036_DSP_HACT_ST_END		0x70
#define RK3036_DSP_VTOTAL_VS_END	0x74
#define RK3036_DSP_VACT_ST_END		0x78
#define RK3036_DSP_VS_ST_END_F1		0x7c
#define RK3036_DSP_VACT_ST_END_F1	0x80
#define RK3036_GATHER_TRANSFER		0x84
#define RK3036_VERSION_INFO		0x94
#define RK3036_REG_CFG_DONE		0x90
#define RK3036_WIN1_MST			0xa0
#define RK3036_WIN1_ACT_INFO		0xb4
#define RK3036_WIN1_DSP_INFO		0xb8
#define RK3036_WIN1_DSP_ST		0xbc
#define RK3036_WIN1_SCL_FACTOR_YRGB	0xc0
#define RK3036_WIN1_SCL_OFFSET		0xc8
#define RK3036_BCSH_CTRL		0xd0
#define RK3036_BCSH_COLOR_BAR		0xd4
#define RK3036_BCSH_BCS			0xd8
#define RK3036_BCSH_H			0xdc
#define RK3036_WIN1_LUT_ADDR		0x400
#define RK3036_HWC_LUT_ADDR		0x800
/* rk3036 register definition end */

#define RK3066_SYS_CTRL0		0x00
#define RK3066_SYS_CTRL1		0x04
#define RK3066_DSP_CTRL0		0x08
#define RK3066_DSP_CTRL1		0x0c
#define RK3066_INT_STATUS		0x10
#define RK3066_MCU_CTRL			0x14
#define RK3066_BLEND_CTRL		0x18
#define RK3066_WIN0_COLOR_KEY_CTRL	0x1c
#define RK3066_WIN1_COLOR_KEY_CTRL	0x20
#define RK3066_WIN2_COLOR_KEY_CTRL	0x24
#define RK3066_WIN0_YRGB_MST0		0x28
#define RK3066_WIN0_CBR_MST0		0x2c
#define RK3066_WIN0_YRGB_MST1		0x30
#define RK3066_WIN0_CBR_MST1		0x34
#define RK3066_WIN0_VIR			0x38
#define RK3066_WIN0_ACT_INFO		0x3c
#define RK3066_WIN0_DSP_INFO		0x40
#define RK3066_WIN0_DSP_ST		0x44
#define RK3066_WIN0_SCL_FACTOR_YRGB	0x48
#define RK3066_WIN0_SCL_FACTOR_CBR	0x4c
#define RK3066_WIN0_SCL_OFFSET		0x50
#define RK3066_WIN1_YRGB_MST		0x54
#define RK3066_WIN1_CBR_MST		0x58
#define RK3066_WIN1_VIR			0x5c
#define RK3066_WIN1_ACT_INFO		0x60
#define RK3066_WIN1_DSP_INFO		0x64
#define RK3066_WIN1_DSP_ST		0x68
#define RK3066_WIN1_SCL_FACTOR_YRGB	0x6c
#define RK3066_WIN1_SCL_FACTOR_CBR	0x70
#define RK3066_WIN1_SCL_OFFSET		0x74
#define RK3066_WIN2_MST			0x78
#define RK3066_WIN2_VIR			0x7c
#define RK3066_WIN2_DSP_INFO		0x80
#define RK3066_WIN2_DSP_ST		0x84
#define RK3066_HWC_MST			0x88
#define RK3066_HWC_DSP_ST		0x8c
#define RK3066_HWC_COLOR_LUT0		0x90
#define RK3066_HWC_COLOR_LUT1		0x94
#define RK3066_HWC_COLOR_LUT2		0x98
#define RK3066_DSP_HTOTAL_HS_END	0x9c
#define RK3066_DSP_HACT_ST_END		0xa0
#define RK3066_DSP_VTOTAL_VS_END	0xa4
#define RK3066_DSP_VACT_ST_END		0xa8
#define RK3066_DSP_VS_ST_END_F1		0xac
#define RK3066_DSP_VACT_ST_END_F1	0xb0
#define RK3066_REG_CFG_DONE		0xc0
#define RK3066_MCU_BYPASS_WPORT		0x100
#define RK3066_MCU_BYPASS_RPORT		0x200
#define RK3066_WIN2_LUT_ADDR		0x400
#define RK3066_DSP_LUT_ADDR		0x800

/* rk3366 register definition */
#define RK3366_LIT_REG_CFG_DONE			0x00000
#define RK3366_LIT_VERSION			0x00004
#define RK3366_LIT_DSP_BG			0x00008
#define RK3366_LIT_MCU_CTRL			0x0000c
#define RK3366_LIT_SYS_CTRL0			0x00010
#define RK3366_LIT_SYS_CTRL1			0x00014
#define RK3366_LIT_SYS_CTRL2			0x00018
#define RK3366_LIT_DSP_CTRL0			0x00020
#define RK3366_LIT_DSP_CTRL2			0x00028
#define RK3366_LIT_VOP_STATUS			0x0002c
#define RK3366_LIT_LINE_FLAG			0x00030
#define RK3366_LIT_INTR_EN			0x00034
#define RK3366_LIT_INTR_CLEAR			0x00038
#define RK3366_LIT_INTR_STATUS			0x0003c
#define RK3366_LIT_WIN0_CTRL0			0x00050
#define RK3366_LIT_WIN0_CTRL1			0x00054
#define RK3366_LIT_WIN0_COLOR_KEY		0x00058
#define RK3366_LIT_WIN0_VIR			0x0005c
#define RK3366_LIT_WIN0_YRGB_MST0		0x00060
#define RK3366_LIT_WIN0_CBR_MST0		0x00064
#define RK3366_LIT_WIN0_ACT_INFO		0x00068
#define RK3366_LIT_WIN0_DSP_INFO		0x0006c
#define RK3366_LIT_WIN0_DSP_ST			0x00070
#define RK3366_LIT_WIN0_SCL_FACTOR_YRGB		0x00074
#define RK3366_LIT_WIN0_SCL_FACTOR_CBR		0x00078
#define RK3366_LIT_WIN0_SCL_OFFSET		0x0007c
#define RK3366_LIT_WIN0_ALPHA_CTRL		0x00080
#define RK3366_LIT_WIN1_CTRL0			0x00090
#define RK3366_LIT_WIN1_CTRL1			0x00094
#define RK3366_LIT_WIN1_VIR			0x00098
#define RK3366_LIT_WIN1_MST			0x000a0
#define RK3366_LIT_WIN1_DSP_INFO		0x000a4
#define RK3366_LIT_WIN1_DSP_ST			0x000a8
#define RK3366_LIT_WIN1_COLOR_KEY		0x000ac
#define RK3366_LIT_WIN1_ALPHA_CTRL		0x000bc
#define RK3366_LIT_HWC_CTRL0			0x000e0
#define RK3366_LIT_HWC_CTRL1			0x000e4
#define RK3366_LIT_HWC_MST			0x000e8
#define RK3366_LIT_HWC_DSP_ST			0x000ec
#define RK3366_LIT_HWC_ALPHA_CTRL		0x000f0
#define RK3366_LIT_DSP_HTOTAL_HS_END		0x00100
#define RK3366_LIT_DSP_HACT_ST_END		0x00104
#define RK3366_LIT_DSP_VTOTAL_VS_END		0x00108
#define RK3366_LIT_DSP_VACT_ST_END		0x0010c
#define RK3366_LIT_DSP_VS_ST_END_F1		0x00110
#define RK3366_LIT_DSP_VACT_ST_END_F1		0x00114
#define RK3366_LIT_BCSH_CTRL			0x00160
#define RK3366_LIT_BCSH_COL_BAR			0x00164
#define RK3366_LIT_BCSH_BCS			0x00168
#define RK3366_LIT_BCSH_H			0x0016c
#define RK3366_LIT_FRC_LOWER01_0		0x00170
#define RK3366_LIT_FRC_LOWER01_1		0x00174
#define RK3366_LIT_FRC_LOWER10_0		0x00178
#define RK3366_LIT_FRC_LOWER10_1		0x0017c
#define RK3366_LIT_FRC_LOWER11_0		0x00180
#define RK3366_LIT_FRC_LOWER11_1		0x00184
#define RK3366_LIT_MCU_RW_BYPASS_PORT		0x0018c
#define RK3366_LIT_DBG_REG_000			0x00190
#define RK3366_LIT_BLANKING_VALUE		0x001f4
#define RK3366_LIT_FLAG_REG_FRM_VALID		0x001f8
#define RK3366_LIT_FLAG_REG			0x001fc
#define RK3366_LIT_HWC_LUT_ADDR			0x00600
#define RK3366_LIT_GAMMA_LUT_ADDR		0x00a00
/* rk3366 register definition end */

/* rk3126 register definition */
#define RK3126_WIN1_MST				0x0004c
#define RK3126_WIN1_DSP_INFO			0x00050
#define RK3126_WIN1_DSP_ST			0x00054
/* rk3126 register definition end */

/* px30 register definition */
#define PX30_CABC_CTRL0				0x00200
#define PX30_CABC_CTRL1				0x00204
#define PX30_CABC_CTRL2				0x00208
#define PX30_CABC_CTRL3				0x0020c
#define PX30_CABC_GAUSS_LINE0_0			0x00210
#define PX30_CABC_GAUSS_LINE0_1			0x00214
#define PX30_CABC_GAUSS_LINE1_0			0x00218
#define PX30_CABC_GAUSS_LINE1_1			0x0021c
#define PX30_CABC_GAUSS_LINE2_0			0x00220
#define PX30_CABC_GAUSS_LINE2_1			0x00224
#define PX30_AFBCD0_CTRL			0x00240
#define PX30_AFBCD0_HDR_PTR			0x00244
#define PX30_AFBCD0_PIC_SIZE			0x00248
#define PX30_AFBCD0_PIC_OFFSET			0x0024c
#define PX30_AFBCD0_AXI_CTRL			0x00250
#define PX30_GRF_PD_VO_CON1			0x00438
/* px30 register definition end */

#define RV1106_VENC_GRF_VOP_IO_WRAPPER		0x1000c

#define RV1126_GRF_IOFUNC_CON3			0x1026c

#define RK3562_GRF_IOC_VO_IO_CON		0x10500

/* rk3568 vop registers definition */

#define RK3568_GRF_VO_CON1			0x0364
/* System registers definition */
#define RK3568_REG_CFG_DONE			0x000
#define RK3568_VOP2_WB_CFG_DONE			BIT(14)
#define RK3568_VOP2_GLB_CFG_DONE_EN		BIT(15)
#define RK3568_VERSION_INFO			0x004
#define RK3568_SYS_AUTO_GATING_CTRL		0x008
#define RK3568_SYS_AXI_LUT_CTRL			0x024
#define RK3568_DSP_IF_EN			0x028
#define RK3568_DSP_IF_CTRL			0x02c
#define RK3568_DSP_IF_POL			0x030
#define RK3568_SYS_PD_CTRL			0x034
#define RK3588_SYS_VAR_FREQ_CTRL		0x038
#define RK3568_WB_CTRL				0x40
#define RK3568_WB_XSCAL_FACTOR			0x44
#define RK3568_WB_YRGB_MST			0x48
#define RK3568_WB_CBR_MST			0x4C
#define RK3568_OTP_WIN_EN			0x50
#define RK3568_LUT_PORT_SEL			0x58
#define RK3568_SYS_STATUS0			0x60
#define RK3568_SYS_STATUS1			0x64
#define RK3568_SYS_STATUS2			0x68
#define RK3568_SYS_STATUS3			0x6C
#define RK3568_VP0_LINE_FLAG			0x70
#define RK3568_VP1_LINE_FLAG			0x74
#define RK3568_VP2_LINE_FLAG			0x78
#define RK3588_VP3_LINE_FLAG			0x7C
#define RK3568_SYS0_INT_EN			0x80
#define RK3568_SYS0_INT_CLR			0x84
#define RK3568_SYS0_INT_STATUS			0x88
#define RK3568_SYS1_INT_EN			0x90
#define RK3568_SYS1_INT_CLR			0x94
#define RK3568_SYS1_INT_STATUS			0x98
#define RK3568_VP0_INT_EN			0xA0
#define RK3568_VP0_INT_CLR			0xA4
#define RK3568_VP0_INT_STATUS			0xA8
#define RK3568_VP0_INT_RAW_STATUS		0xAC
#define RK3568_VP1_INT_EN			0xB0
#define RK3568_VP1_INT_CLR			0xB4
#define RK3568_VP1_INT_STATUS			0xB8
#define RK3568_VP1_INT_RAW_STATUS		0xBC
#define RK3568_VP2_INT_EN			0xC0
#define RK3568_VP2_INT_CLR			0xC4
#define RK3568_VP2_INT_STATUS			0xC8
#define RK3568_VP2_INT_RAW_STATUS		0xCC
#define RK3588_VP3_INT_EN			0xD0
#define RK3588_VP3_INT_CLR			0xD4
#define RK3588_VP3_INT_STATUS			0xD8

#define RK3588_DSC_8K_SYS_CTRL			0x200
#define RK3588_DSC_8K_RST			0x204
#define RK3588_DSC_8K_CFG_DONE			0x208
#define RK3588_DSC_8K_INIT_DLY			0x20C
#define RK3588_DSC_8K_HTOTAL_HS_END		0x210
#define RK3588_DSC_8K_HACT_ST_END		0x214
#define RK3588_DSC_8K_VTOTAL_VS_END		0x218
#define RK3588_DSC_8K_VACT_ST_END		0x21C
#define RK3588_DSC_8K_STATUS			0x220
#define RK3588_DSC_4K_SYS_CTRL			0x230
#define RK3588_DSC_4K_RST			0x234
#define RK3588_DSC_4K_CFG_DONE			0x238
#define RK3588_DSC_4K_INIT_DLY			0x23C
#define RK3588_DSC_4K_HTOTAL_HS_END		0x240
#define RK3588_DSC_4K_HACT_ST_END		0x244
#define RK3588_DSC_4K_VTOTAL_VS_END		0x248
#define RK3588_DSC_4K_VACT_ST_END		0x24C
#define RK3588_DSC_4K_STATUS			0x250

/* Video Port registers definition */
#define RK3568_VP0_DSP_CTRL				0xC00
#define RK3568_VP0_DUAL_CHANNEL_CTRL			0xC04
#define RK3568_VP0_COLOR_BAR_CTRL			0xC08
#define RK3568_VP0_CLK_CTRL				0xC0C
#define RK3568_VP0_3D_LUT_CTRL				0xC10
#define RK3568_VP0_3D_LUT_MST				0xC20
#define RK3568_VP0_DSP_BG				0xC2C
#define RK3568_VP0_PRE_SCAN_HTIMING			0xC30
#define RK3568_VP0_POST_DSP_HACT_INFO			0xC34
#define RK3568_VP0_POST_DSP_VACT_INFO			0xC38
#define RK3568_VP0_POST_SCL_FACTOR_YRGB			0xC3C
#define RK3568_VP0_POST_SCL_CTRL			0xC40
#define RK3568_VP0_POST_DSP_VACT_INFO_F1		0xC44
#define RK3568_VP0_DSP_HTOTAL_HS_END			0xC48
#define RK3568_VP0_DSP_HACT_ST_END			0xC4C
#define RK3568_VP0_DSP_VTOTAL_VS_END			0xC50
#define RK3568_VP0_DSP_VACT_ST_END			0xC54
#define RK3568_VP0_DSP_VS_ST_END_F1			0xC58
#define RK3568_VP0_DSP_VACT_ST_END_F1			0xC5C
#define RK3568_VP0_BCSH_CTRL				0xC60
#define RK3568_VP0_BCSH_BCS				0xC64
#define RK3568_VP0_BCSH_H				0xC68
#define RK3568_VP0_BCSH_COLOR_BAR			0xC6C
#define RK3562_VP0_MCU_CTRL				0xCF8
#define RK3562_VP0_MCU_RW_BYPASS_PORT			0xCFC

#define RK3528_VP0_ACM_CTRL				0xCD0
#define RK3528_VP0_CSC_COE01_02				0xCD4
#define RK3528_VP0_CSC_COE10_11				0xCD8
#define RK3528_VP0_CSC_COE12_20				0xCDC
#define RK3528_VP0_CSC_COE21_22				0xCE0
#define RK3528_VP0_CSC_OFFSET0				0xCE4
#define RK3528_VP0_CSC_OFFSET1				0xCE8
#define RK3528_VP0_CSC_OFFSET2				0xCEC
#define RK3528_VP0_MCU_CTRL				0xCF8
#define RK3528_VP0_MCU_RW_BYPASS_PORT			0xCFC

#define RK3568_VP1_DSP_CTRL				0xD00
#define RK3568_VP1_DUAL_CHANNEL_CTRL			0xD04
#define RK3568_VP1_COLOR_BAR_CTRL			0xD08
#define RK3568_VP1_CLK_CTRL				0xD0C
#define RK3588_VP1_3D_LUT_CTRL				0xD10
#define RK3588_VP1_3D_LUT_MST				0xD20
#define RK3568_VP1_DSP_BG				0xD2C
#define RK3568_VP1_PRE_SCAN_HTIMING			0xD30
#define RK3568_VP1_POST_DSP_HACT_INFO			0xD34
#define RK3568_VP1_POST_DSP_VACT_INFO			0xD38
#define RK3568_VP1_POST_SCL_FACTOR_YRGB			0xD3C
#define RK3568_VP1_POST_SCL_CTRL			0xD40
#define RK3568_VP1_DSP_HACT_INFO			0xD34
#define RK3568_VP1_DSP_VACT_INFO			0xD38
#define RK3568_VP1_POST_DSP_VACT_INFO_F1		0xD44
#define RK3568_VP1_DSP_HTOTAL_HS_END			0xD48
#define RK3568_VP1_DSP_HACT_ST_END			0xD4C
#define RK3568_VP1_DSP_VTOTAL_VS_END			0xD50
#define RK3568_VP1_DSP_VACT_ST_END			0xD54
#define RK3568_VP1_DSP_VS_ST_END_F1			0xD58
#define RK3568_VP1_DSP_VACT_ST_END_F1			0xD5C
#define RK3568_VP1_BCSH_CTRL				0xD60
#define RK3568_VP1_BCSH_BCS				0xD64
#define RK3568_VP1_BCSH_H				0xD68
#define RK3568_VP1_BCSH_COLOR_BAR			0xD6C
#define RK3562_VP1_MCU_CTRL				0xDF8
#define RK3562_VP1_MCU_RW_BYPASS_PORT			0xDFC

#define RK3568_VP2_DSP_CTRL				0xE00
#define RK3568_VP2_DUAL_CHANNEL_CTRL			0xE04
#define RK3568_VP2_COLOR_BAR_CTRL			0xE08
#define RK3568_VP2_CLK_CTRL				0xE0C
#define RK3588_VP2_3D_LUT_CTRL				0xE10
#define RK3588_VP2_3D_LUT_MST				0xE20
#define RK3568_VP2_DSP_BG				0xE2C
#define RK3568_VP2_PRE_SCAN_HTIMING			0xE30
#define RK3568_VP2_POST_DSP_HACT_INFO			0xE34
#define RK3568_VP2_POST_DSP_VACT_INFO			0xE38
#define RK3568_VP2_POST_SCL_FACTOR_YRGB			0xE3C
#define RK3568_VP2_POST_SCL_CTRL			0xE40
#define RK3568_VP2_DSP_HACT_INFO			0xE34
#define RK3568_VP2_DSP_VACT_INFO			0xE38
#define RK3568_VP2_POST_DSP_VACT_INFO_F1		0xE44
#define RK3568_VP2_DSP_HTOTAL_HS_END			0xE48
#define RK3568_VP2_DSP_HACT_ST_END			0xE4C
#define RK3568_VP2_DSP_VTOTAL_VS_END			0xE50
#define RK3568_VP2_DSP_VACT_ST_END			0xE54
#define RK3568_VP2_DSP_VS_ST_END_F1			0xE58
#define RK3568_VP2_DSP_VACT_ST_END_F1			0xE5C
#define RK3568_VP2_BCSH_CTRL				0xE60
#define RK3568_VP2_BCSH_BCS				0xE64
#define RK3568_VP2_BCSH_H				0xE68
#define RK3568_VP2_BCSH_COLOR_BAR			0xE6C

#define RK3588_VP3_DSP_CTRL				0xF00
#define RK3588_VP3_DUAL_CHANNEL_CTRL			0xF04
#define RK3588_VP3_COLOR_BAR_CTRL			0xF08
#define RK3568_VP3_CLK_CTRL				0xF0C
#define RK3588_VP3_DSP_BG				0xF2C
#define RK3588_VP3_PRE_SCAN_HTIMING			0xF30
#define RK3588_VP3_POST_DSP_HACT_INFO			0xF34
#define RK3588_VP3_POST_DSP_VACT_INFO			0xF38
#define RK3588_VP3_POST_SCL_FACTOR_YRGB			0xF3C
#define RK3588_VP3_POST_SCL_CTRL			0xF40
#define RK3588_VP3_DSP_HACT_INFO			0xF34
#define RK3588_VP3_DSP_VACT_INFO			0xF38
#define RK3588_VP3_POST_DSP_VACT_INFO_F1		0xF44
#define RK3588_VP3_DSP_HTOTAL_HS_END			0xF48
#define RK3588_VP3_DSP_HACT_ST_END			0xF4C
#define RK3588_VP3_DSP_VTOTAL_VS_END			0xF50
#define RK3588_VP3_DSP_VACT_ST_END			0xF54
#define RK3588_VP3_DSP_VS_ST_END_F1			0xF58
#define RK3588_VP3_DSP_VACT_ST_END_F1			0xF5C
#define RK3588_VP3_BCSH_CTRL				0xF60
#define RK3588_VP3_BCSH_BCS				0xF64
#define RK3588_VP3_BCSH_H				0xF68
#define RK3588_VP3_BCSH_COLOR_BAR			0xF6C
#define RK3528_OVL_SYS					0x500
#define RK3528_OVL_SYS_PORT_SEL_IMD			0x504
#define RK3528_OVL_SYS_GATING_EN_IMD			0x508
#define RK3528_OVL_SYS_CLUSTER0_CTRL			0x510
#define RK3528_OVL_SYS_ESMART0_CTRL			0x520
#define RK3528_OVL_SYS_ESMART1_CTRL			0x524
#define RK3528_OVL_SYS_ESMART2_CTRL			0x528
#define RK3528_OVL_SYS_ESMART3_CTRL			0x52C
#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL		0x530
#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL		0x534
#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL		0x538
#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL		0x53c
#define RK3528_OVL_PORT0_CTRL				0x600
#define RK3528_OVL_PORT0_LAYER_SEL			0x604
#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL		0x620
#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL		0x624
#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL		0x628
#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL		0x62C
#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL		0x630
#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL		0x634
#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL		0x638
#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL		0x63C
#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL		0x640
#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL		0x644
#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL		0x648
#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL		0x64C
#define RK3528_HDR_SRC_COLOR_CTRL			0x660
#define RK3528_HDR_DST_COLOR_CTRL			0x664
#define RK3528_HDR_SRC_ALPHA_CTRL			0x668
#define RK3528_HDR_DST_ALPHA_CTRL			0x66C
#define RK3528_OVL_PORT0_BG_MIX_CTRL			0x670
#define RK3528_OVL_PORT1_CTRL				0x700
#define RK3528_OVL_PORT1_LAYER_SEL			0x704
#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL		0x720
#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL		0x724
#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL		0x728
#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL		0x72C
#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL		0x730
#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL		0x734
#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL		0x738
#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL		0x73C
#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL		0x740
#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL		0x744
#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL		0x748
#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL		0x74C
#define RK3528_OVL_PORT1_BG_MIX_CTRL			0x770

/* Overlay registers definition    */
#define RK3568_OVL_CTRL				0x600
#define RK3568_OVL_LAYER_SEL			0x604
#define RK3568_OVL_PORT_SEL			0x608
#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL	0x610
#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL	0x614
#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x618
#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL	0x61C
#define RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL	0x620
#define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL	0x624
#define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL	0x628
#define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL	0x62C
#define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL	0x630
#define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL	0x634
#define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL	0x638
#define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL	0x63C
#define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL	0x640
#define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL	0x644
#define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL	0x648
#define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL	0x64C
#define RK3568_MIX0_SRC_COLOR_CTRL		0x650
#define RK3568_MIX0_DST_COLOR_CTRL		0x654
#define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
#define RK3568_MIX0_DST_ALPHA_CTRL		0x65C
#define RK3568_HDR0_SRC_COLOR_CTRL		0x6C0
#define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
#define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
#define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
#define RK3568_HDR1_SRC_COLOR_CTRL		0x6D0
#define RK3568_HDR1_DST_COLOR_CTRL		0x6D4
#define RK3568_HDR1_SRC_ALPHA_CTRL		0x6D8
#define RK3568_HDR1_DST_ALPHA_CTRL		0x6DC
#define RK3568_VP0_BG_MIX_CTRL			0x6E0
#define RK3568_VP1_BG_MIX_CTRL			0x6E4
#define RK3568_VP2_BG_MIX_CTRL			0x6E8
#define RK3588_VP3_BG_MIX_CTRL			0x6EC
#define RK3568_CLUSTER_DLY_NUM			0x6F0
#define RK3568_CLUSTER_DLY_NUM1			0x6F4
#define RK3568_SMART_DLY_NUM			0x6F8

/* Cluster0 register definition */
#define RK3568_CLUSTER0_WIN0_CTRL0		0x1000
#define RK3568_CLUSTER0_WIN0_CTRL1		0x1004
#define RK3528_CLUSTER0_WIN0_CTRL1		0x1004
#define RK3528_CLUSTER0_WIN0_CTRL2		0x1008
#define RK3568_CLUSTER0_WIN0_CTRL2		0x1008
#define RK3568_CLUSTER0_WIN0_YRGB_MST		0x1010
#define RK3568_CLUSTER0_WIN0_CBR_MST		0x1014
#define RK3568_CLUSTER0_WIN0_VIR		0x1018
#define RK3568_CLUSTER0_WIN0_ACT_INFO		0x1020
#define RK3568_CLUSTER0_WIN0_DSP_INFO		0x1024
#define RK3568_CLUSTER0_WIN0_DSP_ST		0x1028
#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB	0x1030
#define RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET	0x103C
#define RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL	0x1050
#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE	0x1054
#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR	0x1058
#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH	0x105C
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE	0x1060
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET	0x1064
#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET	0x1068
#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL		0x106C

#define RK3568_CLUSTER0_WIN1_CTRL0		0x1080
#define RK3568_CLUSTER0_WIN1_CTRL1		0x1084
#define RK3528_CLUSTER0_WIN1_CTRL1		0x1084
#define RK3528_CLUSTER0_WIN1_CTRL2		0x1088
#define RK3568_CLUSTER0_WIN1_YRGB_MST		0x1090
#define RK3568_CLUSTER0_WIN1_CBR_MST		0x1094
#define RK3568_CLUSTER0_WIN1_VIR		0x1098
#define RK3568_CLUSTER0_WIN1_ACT_INFO		0x10A0
#define RK3568_CLUSTER0_WIN1_DSP_INFO		0x10A4
#define RK3568_CLUSTER0_WIN1_DSP_ST		0x10A8
#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB	0x10B0
#define RK3568_CLUSTER0_WIN1_AFBCD_OUTPUT_CTRL	0x10D0
#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE	0x10D4
#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR	0x10D8
#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH	0x10DC
#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE	0x10E0
#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET	0x10E4
#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET	0x10E8
#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL		0x10EC

#define RK3568_CLUSTER0_CTRL			0x1100

#define RK3568_CLUSTER1_WIN0_CTRL0		0x1200
#define RK3568_CLUSTER1_WIN0_CTRL1		0x1204
#define RK3568_CLUSTER1_WIN0_CTRL2		0x1208
#define RK3568_CLUSTER1_WIN0_YRGB_MST		0x1210
#define RK3568_CLUSTER1_WIN0_CBR_MST		0x1214
#define RK3568_CLUSTER1_WIN0_VIR		0x1218
#define RK3568_CLUSTER1_WIN0_ACT_INFO		0x1220
#define RK3568_CLUSTER1_WIN0_DSP_INFO		0x1224
#define RK3568_CLUSTER1_WIN0_DSP_ST		0x1228
#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB	0x1230
#define RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET	0x123C
#define RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL	0x1250
#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE	0x1254
#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR	0x1258
#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH	0x125C
#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE	0x1260
#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET	0x1264
#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET	0x1268
#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL		0x126C

#define RK3568_CLUSTER1_WIN1_CTRL0		0x1280
#define RK3568_CLUSTER1_WIN1_CTRL1		0x1284
#define RK3568_CLUSTER1_WIN1_YRGB_MST		0x1290
#define RK3568_CLUSTER1_WIN1_CBR_MST		0x1294
#define RK3568_CLUSTER1_WIN1_VIR		0x1298
#define RK3568_CLUSTER1_WIN1_ACT_INFO		0x12A0
#define RK3568_CLUSTER1_WIN1_DSP_INFO		0x12A4
#define RK3568_CLUSTER1_WIN1_DSP_ST		0x12A8
#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB	0x12B0
#define RK3568_CLUSTER1_WIN1_AFBCD_OUTPUT_CTRL	0x12D0
#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE	0x12D4
#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR	0x12D8
#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH	0x12DC
#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE	0x12E0
#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET	0x12E4
#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET	0x12E8
#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL		0x12EC

#define RK3568_CLUSTER1_CTRL			0x1300

#define RK3588_CLUSTER2_WIN0_CTRL0		0x1400
#define RK3588_CLUSTER2_WIN0_CTRL1		0x1404
#define RK3588_CLUSTER2_WIN0_CTRL2		0x1408
#define RK3588_CLUSTER2_WIN0_YRGB_MST		0x1410
#define RK3588_CLUSTER2_WIN0_CBR_MST		0x1414
#define RK3588_CLUSTER2_WIN0_VIR		0x1418
#define RK3588_CLUSTER2_WIN0_ACT_INFO		0x1420
#define RK3588_CLUSTER2_WIN0_DSP_INFO		0x1424
#define RK3588_CLUSTER2_WIN0_DSP_ST		0x1428
#define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB	0x1430
#define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET	0x143C
#define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL	0x1450
#define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE	0x1454
#define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR	0x1458
#define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH	0x145C
#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE	0x1460
#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET	0x1464
#define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET	0x1468
#define RK3588_CLUSTER2_WIN0_AFBCD_CTRL		0x146C

#define RK3588_CLUSTER2_WIN1_CTRL0		0x1480
#define RK3588_CLUSTER2_WIN1_CTRL1		0x1484
#define RK3588_CLUSTER2_WIN1_YRGB_MST		0x1490
#define RK3588_CLUSTER2_WIN1_CBR_MST		0x1494
#define RK3588_CLUSTER2_WIN1_VIR		0x1498
#define RK3588_CLUSTER2_WIN1_ACT_INFO		0x14A0
#define RK3588_CLUSTER2_WIN1_DSP_INFO		0x14A4
#define RK3588_CLUSTER2_WIN1_DSP_ST		0x14A8
#define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB	0x14B0
#define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL	0x14D0
#define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE	0x14D4
#define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR	0x14D8
#define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH	0x14DC
#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE	0x14E0
#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET	0x14E4
#define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET	0x14E8
#define RK3588_CLUSTER2_WIN1_AFBCD_CTRL		0x14EC

#define RK3588_CLUSTER2_CTRL			0x1500

#define RK3588_CLUSTER3_WIN0_CTRL0		0x1600
#define RK3588_CLUSTER3_WIN0_CTRL1		0x1604
#define RK3588_CLUSTER3_WIN0_CTRL2		0x1608
#define RK3588_CLUSTER3_WIN0_YRGB_MST		0x1610
#define RK3588_CLUSTER3_WIN0_CBR_MST		0x1614
#define RK3588_CLUSTER3_WIN0_VIR		0x1618
#define RK3588_CLUSTER3_WIN0_ACT_INFO		0x1620
#define RK3588_CLUSTER3_WIN0_DSP_INFO		0x1624
#define RK3588_CLUSTER3_WIN0_DSP_ST		0x1628
#define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB	0x1630
#define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET	0x163C
#define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL	0x1650
#define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE	0x1654
#define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR	0x1658
#define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH	0x165C
#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE	0x1660
#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET	0x1664
#define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET	0x1668
#define RK3588_CLUSTER3_WIN0_AFBCD_CTRL		0x166C

#define RK3588_CLUSTER3_WIN1_CTRL0		0x1680
#define RK3588_CLUSTER3_WIN1_CTRL1		0x1684
#define RK3588_CLUSTER3_WIN1_YRGB_MST		0x1690
#define RK3588_CLUSTER3_WIN1_CBR_MST		0x1694
#define RK3588_CLUSTER3_WIN1_VIR		0x1698
#define RK3588_CLUSTER3_WIN1_ACT_INFO		0x16A0
#define RK3588_CLUSTER3_WIN1_DSP_INFO		0x16A4
#define RK3588_CLUSTER3_WIN1_DSP_ST		0x16A8
#define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB	0x16B0
#define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL	0x16D0
#define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE	0x16D4
#define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR	0x16D8
#define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH	0x16DC
#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE	0x16E0
#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET	0x16E4
#define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET	0x16E8
#define RK3588_CLUSTER3_WIN1_AFBCD_CTRL		0x16EC

#define RK3588_CLUSTER3_CTRL			0x1700

/* Esmart register definition */
#define RK3568_ESMART0_CTRL0			0x1800
#define RK3568_ESMART0_CTRL1			0x1804
#define RK3568_ESMART0_AXI_CTRL			0x1808
#define RK3568_ESMART0_REGION0_CTRL		0x1810
#define RK3568_ESMART0_REGION0_YRGB_MST		0x1814
#define RK3568_ESMART0_REGION0_CBR_MST		0x1818
#define RK3568_ESMART0_REGION0_VIR		0x181C
#define RK3568_ESMART0_REGION0_ACT_INFO		0x1820
#define RK3568_ESMART0_REGION0_DSP_INFO		0x1824
#define RK3568_ESMART0_REGION0_DSP_ST		0x1828
#define RK3568_ESMART0_REGION0_SCL_CTRL		0x1830
#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB	0x1834
#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR	0x1838
#define RK3568_ESMART0_REGION0_SCL_OFFSET	0x183C
#define RK3568_ESMART0_REGION1_CTRL		0x1840
#define RK3568_ESMART0_REGION1_YRGB_MST		0x1844
#define RK3568_ESMART0_REGION1_CBR_MST		0x1848
#define RK3568_ESMART0_REGION1_VIR		0x184C
#define RK3568_ESMART0_REGION1_ACT_INFO		0x1850
#define RK3568_ESMART0_REGION1_DSP_INFO		0x1854
#define RK3568_ESMART0_REGION1_DSP_ST		0x1858
#define RK3568_ESMART0_REGION1_SCL_CTRL		0x1860
#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB	0x1864
#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR	0x1868
#define RK3568_ESMART0_REGION1_SCL_OFFSET	0x186C
#define RK3568_ESMART0_REGION2_CTRL		0x1870
#define RK3568_ESMART0_REGION2_YRGB_MST		0x1874
#define RK3568_ESMART0_REGION2_CBR_MST		0x1878
#define RK3568_ESMART0_REGION2_VIR		0x187C
#define RK3568_ESMART0_REGION2_ACT_INFO		0x1880
#define RK3568_ESMART0_REGION2_DSP_INFO		0x1884
#define RK3568_ESMART0_REGION2_DSP_ST		0x1888
#define RK3568_ESMART0_REGION2_SCL_CTRL		0x1890
#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB	0x1894
#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR	0x1898
#define RK3568_ESMART0_REGION2_SCL_OFFSET	0x189C
#define RK3568_ESMART0_REGION3_CTRL		0x18A0
#define RK3568_ESMART0_REGION3_YRGB_MST		0x18A4
#define RK3568_ESMART0_REGION3_CBR_MST		0x18A8
#define RK3568_ESMART0_REGION3_VIR		0x18AC
#define RK3568_ESMART0_REGION3_ACT_INFO		0x18B0
#define RK3568_ESMART0_REGION3_DSP_INFO		0x18B4
#define RK3568_ESMART0_REGION3_DSP_ST		0x18B8
#define RK3568_ESMART0_REGION3_SCL_CTRL		0x18C0
#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB	0x18C4
#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR	0x18C8
#define RK3568_ESMART0_REGION3_SCL_OFFSET	0x18CC
#define RK3568_ESMART0_COLOR_KEY_CTRL		0x18D0

#define RK3568_ESMART1_CTRL0			0x1A00
#define RK3568_ESMART1_CTRL1			0x1A04
#define RK3568_ESMART1_REGION0_CTRL		0x1A10
#define RK3568_ESMART1_REGION0_YRGB_MST		0x1A14
#define RK3568_ESMART1_REGION0_CBR_MST		0x1A18
#define RK3568_ESMART1_REGION0_VIR		0x1A1C
#define RK3568_ESMART1_REGION0_ACT_INFO		0x1A20
#define RK3568_ESMART1_REGION0_DSP_INFO		0x1A24
#define RK3568_ESMART1_REGION0_DSP_ST		0x1A28
#define RK3568_ESMART1_REGION0_SCL_CTRL		0x1A30
#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB	0x1A34
#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR	0x1A38
#define RK3568_ESMART1_REGION0_SCL_OFFSET	0x1A3C
#define RK3568_ESMART1_REGION1_CTRL		0x1A40
#define RK3568_ESMART1_REGION1_YRGB_MST		0x1A44
#define RK3568_ESMART1_REGION1_CBR_MST		0x1A48
#define RK3568_ESMART1_REGION1_VIR		0x1A4C
#define RK3568_ESMART1_REGION1_ACT_INFO		0x1A50
#define RK3568_ESMART1_REGION1_DSP_INFO		0x1A54
#define RK3568_ESMART1_REGION1_DSP_ST		0x1A58
#define RK3568_ESMART1_REGION1_SCL_CTRL		0x1A60
#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB	0x1A64
#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR	0x1A68
#define RK3568_ESMART1_REGION1_SCL_OFFSET	0x1A6C
#define RK3568_ESMART1_REGION2_CTRL		0x1A70
#define RK3568_ESMART1_REGION2_YRGB_MST		0x1A74
#define RK3568_ESMART1_REGION2_CBR_MST		0x1A78
#define RK3568_ESMART1_REGION2_VIR		0x1A7C
#define RK3568_ESMART1_REGION2_ACT_INFO		0x1A80
#define RK3568_ESMART1_REGION2_DSP_INFO		0x1A84
#define RK3568_ESMART1_REGION2_DSP_ST		0x1A88
#define RK3568_ESMART1_REGION2_SCL_CTRL		0x1A90
#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB	0x1A94
#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR	0x1A98
#define RK3568_ESMART1_REGION2_SCL_OFFSET	0x1A9C
#define RK3568_ESMART1_REGION3_CTRL		0x1AA0
#define RK3568_ESMART1_REGION3_YRGB_MST		0x1AA4
#define RK3568_ESMART1_REGION3_CBR_MST		0x1AA8
#define RK3568_ESMART1_REGION3_VIR		0x1AAC
#define RK3568_ESMART1_REGION3_ACT_INFO		0x1AB0
#define RK3568_ESMART1_REGION3_DSP_INFO		0x1AB4
#define RK3568_ESMART1_REGION3_DSP_ST		0x1AB8
#define RK3568_ESMART1_REGION3_SCL_CTRL		0x1AC0
#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB	0x1AC4
#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR	0x1AC8
#define RK3568_ESMART1_REGION3_SCL_OFFSET	0x1ACC

#define RK3568_SMART0_CTRL0			0x1C00
#define RK3568_SMART0_CTRL1			0x1C04
#define RK3568_SMART0_REGION0_CTRL		0x1C10
#define RK3568_SMART0_REGION0_YRGB_MST		0x1C14
#define RK3568_SMART0_REGION0_CBR_MST		0x1C18
#define RK3568_SMART0_REGION0_VIR		0x1C1C
#define RK3568_SMART0_REGION0_ACT_INFO		0x1C20
#define RK3568_SMART0_REGION0_DSP_INFO		0x1C24
#define RK3568_SMART0_REGION0_DSP_ST		0x1C28
#define RK3568_SMART0_REGION0_SCL_CTRL		0x1C30
#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB	0x1C34
#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR	0x1C38
#define RK3568_SMART0_REGION0_SCL_OFFSET	0x1C3C
#define RK3568_SMART0_REGION1_CTRL		0x1C40
#define RK3568_SMART0_REGION1_YRGB_MST		0x1C44
#define RK3568_SMART0_REGION1_CBR_MST		0x1C48
#define RK3568_SMART0_REGION1_VIR		0x1C4C
#define RK3568_SMART0_REGION1_ACT_INFO		0x1C50
#define RK3568_SMART0_REGION1_DSP_INFO		0x1C54
#define RK3568_SMART0_REGION1_DSP_ST		0x1C58
#define RK3568_SMART0_REGION1_SCL_CTRL		0x1C60
#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB	0x1C64
#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR	0x1C68
#define RK3568_SMART0_REGION1_SCL_OFFSET	0x1C6C
#define RK3568_SMART0_REGION2_CTRL		0x1C70
#define RK3568_SMART0_REGION2_YRGB_MST		0x1C74
#define RK3568_SMART0_REGION2_CBR_MST		0x1C78
#define RK3568_SMART0_REGION2_VIR		0x1C7C
#define RK3568_SMART0_REGION2_ACT_INFO		0x1C80
#define RK3568_SMART0_REGION2_DSP_INFO		0x1C84
#define RK3568_SMART0_REGION2_DSP_ST		0x1C88
#define RK3568_SMART0_REGION2_SCL_CTRL		0x1C90
#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB	0x1C94
#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR	0x1C98
#define RK3568_SMART0_REGION2_SCL_OFFSET	0x1C9C
#define RK3568_SMART0_REGION3_CTRL		0x1CA0
#define RK3568_SMART0_REGION3_YRGB_MST		0x1CA4
#define RK3568_SMART0_REGION3_CBR_MST		0x1CA8
#define RK3568_SMART0_REGION3_VIR		0x1CAC
#define RK3568_SMART0_REGION3_ACT_INFO		0x1CB0
#define RK3568_SMART0_REGION3_DSP_INFO		0x1CB4
#define RK3568_SMART0_REGION3_DSP_ST		0x1CB8
#define RK3568_SMART0_REGION3_SCL_CTRL		0x1CC0
#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB	0x1CC4
#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR	0x1CC8
#define RK3568_SMART0_REGION3_SCL_OFFSET	0x1CCC

#define RK3568_SMART1_CTRL0			0x1E00
#define RK3568_SMART1_CTRL1			0x1E04
#define RK3568_SMART1_REGION0_CTRL		0x1E10
#define RK3568_SMART1_REGION0_YRGB_MST		0x1E14
#define RK3568_SMART1_REGION0_CBR_MST		0x1E18
#define RK3568_SMART1_REGION0_VIR		0x1E1C
#define RK3568_SMART1_REGION0_ACT_INFO		0x1E20
#define RK3568_SMART1_REGION0_DSP_INFO		0x1E24
#define RK3568_SMART1_REGION0_DSP_ST		0x1E28
#define RK3568_SMART1_REGION0_SCL_CTRL		0x1E30
#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB	0x1E34
#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR	0x1E38
#define RK3568_SMART1_REGION0_SCL_OFFSET	0x1E3C
#define RK3568_SMART1_REGION1_CTRL		0x1E40
#define RK3568_SMART1_REGION1_YRGB_MST		0x1E44
#define RK3568_SMART1_REGION1_CBR_MST		0x1E48
#define RK3568_SMART1_REGION1_VIR		0x1E4C
#define RK3568_SMART1_REGION1_ACT_INFO		0x1E50
#define RK3568_SMART1_REGION1_DSP_INFO		0x1E54
#define RK3568_SMART1_REGION1_DSP_ST		0x1E58
#define RK3568_SMART1_REGION1_SCL_CTRL		0x1E60
#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB	0x1E64
#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR	0x1E68
#define RK3568_SMART1_REGION1_SCL_OFFSET	0x1E6C
#define RK3568_SMART1_REGION2_CTRL		0x1E70
#define RK3568_SMART1_REGION2_YRGB_MST		0x1E74
#define RK3568_SMART1_REGION2_CBR_MST		0x1E78
#define RK3568_SMART1_REGION2_VIR		0x1E7C
#define RK3568_SMART1_REGION2_ACT_INFO		0x1E80
#define RK3568_SMART1_REGION2_DSP_INFO		0x1E84
#define RK3568_SMART1_REGION2_DSP_ST		0x1E88
#define RK3568_SMART1_REGION2_SCL_CTRL		0x1E90
#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB	0x1E94
#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR	0x1E98
#define RK3568_SMART1_REGION2_SCL_OFFSET	0x1E9C
#define RK3568_SMART1_REGION3_CTRL		0x1EA0
#define RK3568_SMART1_REGION3_YRGB_MST		0x1EA4
#define RK3568_SMART1_REGION3_CBR_MST		0x1EA8
#define RK3568_SMART1_REGION3_VIR		0x1EAC
#define RK3568_SMART1_REGION3_ACT_INFO		0x1EB0
#define RK3568_SMART1_REGION3_DSP_INFO		0x1EB4
#define RK3568_SMART1_REGION3_DSP_ST		0x1EB8
#define RK3568_SMART1_REGION3_SCL_CTRL		0x1EC0
#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB	0x1EC4
#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR	0x1EC8
#define RK3568_SMART1_REGION3_SCL_OFFSET	0x1ECC

/* HDR register definition */
#define RK3568_HDR_LUT_CTRL				0x2000
#define RK3568_HDR_LUT_MST				0x2004
#define RK3568_SDR2HDR_CTRL				0x2010
/* for HDR10 controller1 */
#define RK3568_SDR2HDR_CTRL1				0x2018
#define RK3568_HDR2SDR_CTRL1				0x201C
#define RK3568_HDR2SDR_CTRL				0x2020
#define RK3568_HDR2SDR_SRC_RANGE			0x2024
#define RK3568_HDR2SDR_NORMFACEETF			0x2028
#define RK3568_HDR2SDR_DST_RANGE			0x202C
#define RK3568_HDR2SDR_NORMFACCGAMMA			0x2030
#define RK3568_HDR_EETF_OETF_Y0				0x203C
#define RK3568_HDR_SAT_Y0				0x20C0
#define RK3568_HDR_EOTF_OETF_Y0				0x20F0
#define RK3568_HDR_OETF_DX_POW1				0x2200
#define RK3568_HDR_OETF_XN1				0x2300

/* DSC register definition */
#define RK3588_DSC_8K_PPS0_3				0x4000
#define RK3588_DSC_8K_CTRL0				0x40A0
#define RK3588_DSC_8K_CTRL1				0x40A4
#define RK3588_DSC_8K_STS0				0x40A8
#define RK3588_DSC_8K_ERS				0x40C4

#define RK3588_DSC_4K_PPS0_3				0x4100
#define RK3588_DSC_4K_CTRL0				0x41A0
#define RK3588_DSC_4K_CTRL1				0x41A4
#define RK3588_DSC_4K_STS0				0x41A8
#define RK3588_DSC_4K_ERS				0x41C4

#define RK3588_GRF_SOC_CON1				0x0304
#define RK3588_GRF_VOP_CON2				0x08
#define RK3588_GRF_VO1_CON0				0x00


#define RK3588_PMU_PWR_GATE_CON1			0x150
#define RK3588_PMU_SUBMEM_PWR_GATE_CON1			0x1B4
#define RK3588_PMU_SUBMEM_PWR_GATE_CON2			0x1B8
#define RK3588_PMU_SUBMEM_PWR_GATE_STATUS		0x1BC
#define RK3588_PMU_BISR_CON3				0x20C
#define RK3588_PMU_BISR_STATUS5				0x294

/* RK3528 HDR register definition */
#define RK3528_HDR_LUT_CTRL			0x2000
#define RK3528_HDR_LUT_MST			0x2004
#define RK3528_HDR_LUT_STATUS			0x2008
#define RK3528_SDR2HDR_CTRL			0x2010
#define RK3528_SDR_CFG_COE0			0x2014
#define RK3528_SDR_CFG_COE1			0x2018
#define RK3528_SDR_CSC_COE00_01			0x201C
#define RK3528_SDR_CSC_COE02_10			0x2020
#define RK3528_SDR_CSC_COE11_12			0x2024
#define RK3528_SDR_CSC_COE20_21			0x2028
#define RK3528_SDR_CSC_COE22			0x202C
#define RK3528_HDRVIVID_CTRL			0x2040
#define RK3528_HDR_PQ_GAMMA			0x2044
#define RK3528_HLG_RFIX_SCALEFAC		0x2048
#define RK3528_HLG_MAXLUMA			0x204C
#define RK3528_HLG_R_TM_LIN2NON			0x2050
#define RK3528_HDR_CSC_COE00_01			0x2054
#define RK3528_HDR_CSC_COE02_10			0x2058
#define RK3528_HDR_CSC_COE11_12			0x205C
#define RK3528_HDR_CSC_COE20_21			0x2060
#define RK3528_HDR_CSC_COE22			0x2064
#define RK3528_INK_CFG				0x2080
#define RK3528_INK_POINT0_CFG			0x2084
#define RK3528_INK_POINT1_CFG			0x2088
#define RK3528_INK_POINT0_R0			0x208C
#define RK3528_INK_POINT0_G0			0x2090
#define RK3528_INK_POINT0_B0			0x2094
#define RK3528_INK_POINT0_R1			0x2098
#define RK3528_INK_POINT0_G1			0x209C
#define RK3528_INK_POINT0_B1			0x20A0
#define RK3528_INK_POINT1_R0			0x20A4
#define RK3528_INK_POINT1_G0			0x20A8
#define RK3528_INK_POINT1_B0			0x20AC
#define RK3528_INK_POINT1_R1			0x20B0
#define RK3528_INK_POINT1_G1			0x20B4
#define RK3528_INK_POINT1_B1			0x20B8
#define RK3528_HDR_TONE_SCA			0x213C
#define RK3528_HDRGAMMA_CURVE			0x2540
#define RK3528_HDRGAMMA_MDFVALUE		0x2690
#define RK3528_SDRINVGAMMA_CURVE		0x2700
#define RK3528_SDRINVGAMMA_STARTIDX		0x2820
#define RK3528_SDRINVGAMMA_CHANGEIDX		0x2840
#define RK3528_SDR_SMGAIN			0x2900

/* RK3588 ACM register definition */
#define RK3528_ACM_CTRL				0x0000
#define RK3528_ACM_ENABLE			BIT(0)
#define RK3528_ACM_BYPASS			BIT(1)
#define RK3528_ACM_DELTA_RANGE			0x0004
#define RK3528_ACM_FETCH_START			0x0008
#define RK3528_ACM_DEBUG_POINT0			0x0010
#define RK3528_ACM_DEBUG_POINT1			0x0014
#define RK3528_ACM_DEBUG_POINT2			0x0018
#define RK3528_ACM_DEBUG_POINT3			0x001c
#define RK3528_ACM_FETCH_DONE			0x0020
#define RK3528_ACM_DEBUG0_DATA0			0x0030
#define RK3528_ACM_DEBUG0_DATA1			0x0034
#define RK3528_ACM_DEBUG0_DATA2			0x0038
#define RK3528_ACM_DEBUG0_DATA3			0x003c
#define RK3528_ACM_DEBUG1_DATA0			0x0040
#define RK3528_ACM_DEBUG1_DATA1			0x0044
#define RK3528_ACM_DEBUG1_DATA2			0x0048
#define RK3528_ACM_DEBUG1_DATA3			0x004c
#define RK3528_ACM_DEBUG2_DATA0			0x0050
#define RK3528_ACM_DEBUG2_DATA1			0x0054
#define RK3528_ACM_DEBUG2_DATA2			0x0058
#define RK3528_ACM_DEBUG2_DATA3			0x005c
#define RK3528_ACM_DEBUG3_DATA0			0x0060
#define RK3528_ACM_DEBUG3_DATA1			0x0064
#define RK3528_ACM_DEBUG3_DATA2			0x0068
#define RK3528_ACM_DEBUG3_DATA3			0x006c
#define RK3528_ACM_YHS_DEL_HY_SEG0		0x0100
#define RK3528_ACM_YHS_DEL_HY_SEG152		0x0360
#define RK3528_ACM_YHS_DEL_HS_SEG0		0x0364
#define RK3528_ACM_YHS_DEL_HS_SEG220		0x06d4
#define RK3528_ACM_YHS_DEL_HGAIN_SEG0		0x06d8
#define RK3528_ACM_YHS_DEL_HGAIN_SEG64		0x07d8
#endif /* _ROCKCHIP_VOP_REG_H */