Searched +full:0 +full:x100008 (Results 1 – 10 of 10) sorted by relevance
65 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;68 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,69 <&mdma1 22 0x10 0x100008 0x0 0x0>;75 #size-cells = <0>;77 flash@0 {79 reg = <0>;
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */33 #define MCFINTC_IRLR 0x18 /* */34 #define MCFINTC_IACKL 0x19 /* */[all …]
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */33 #define MCFINTC_IRLR 0x18 /* */34 #define MCFINTC_IACKL 0x19 /* */[all …]
48 #define A_ELMER0_VERSION 0x10000049 #define A_ELMER0_PHY_CFG 0x10000450 #define A_ELMER0_INT_ENABLE 0x10000851 #define A_ELMER0_INT_CAUSE 0x10000c52 #define A_ELMER0_GPI_CFG 0x10001053 #define A_ELMER0_GPI_STAT 0x10001454 #define A_ELMER0_GPO 0x10001855 #define A_ELMER0_PORT0_MI1_CFG 0x40000057 #define S_MI1_MDI_ENABLE 070 #define M_MI1_SOF 0x3[all …]
22 #define MCF_FMPLL_SYNCR 0x12000023 #define MCF_FMPLL_SYNSR 0x12000425 #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)26 #define MCF_SYNCR_MFD_4X 0x0000000027 #define MCF_SYNCR_MFD_6X 0x0100000028 #define MCF_SYNCR_MFD_8X 0x0200000029 #define MCF_SYNCR_MFD_10X 0x0300000030 #define MCF_SYNCR_MFD_12X 0x0400000031 #define MCF_SYNCR_MFD_14X 0x0500000032 #define MCF_SYNCR_MFD_16X 0x06000000[all …]
15 #define PLL_SYNCR_LOLRE (0x8000)16 #define PLL_SYNCR_MFD2 (0x4000)17 #define PLL_SYNCR_MFD1 (0x2000)18 #define PLL_SYNCR_MFD0 (0x1000)19 #define PLL_SYNCR_LOCRE (0x0800)20 #define PLL_SYNCR_RFC2 (0x0400)21 #define PLL_SYNCR_RFC1 (0x0200)22 #define PLL_SYNCR_RFC0 (0x0100)23 #define PLL_SYNCR_LOCEN (0x0080)24 #define PLL_SYNCR_DISCLK (0x0040)[all …]
125 int err, offset = 0x20; in platinumfb_set_par()127 if((err = platinum_var_to_par(&info->var, pinfo, 0))) { in platinumfb_set_par()138 offset = 0x10; in platinumfb_set_par()149 return 0; in platinumfb_set_par()155 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL in platinumfb_blank()157 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due in platinumfb_blank()169 ctrl = le32_to_cpup(&info->platinum_regs->ctrl.r) | 0x33; in platinumfb_blank()175 ctrl &= ~0x30; in platinumfb_blank()179 return 0; in platinumfb_blank()218 return 0; in platinumfb_setcolreg()[all …]
16 #size-cells = <0>;18 cpu0: cpu@0 {22 reg = <0>;42 reg = <0xa0021000 0x1000>,43 <0xa0022000 0x2000>;57 #clock-cells = <0>;63 #clock-cells = <0>;69 #clock-cells = <0>;75 #clock-cells = <0>;81 #clock-cells = <0>;[all …]
21 #define QM_VF_AEQ_INT_SOURCE 0x022 #define QM_VF_AEQ_INT_MASK 0x423 #define QM_VF_EQ_INT_SOURCE 0x824 #define QM_VF_EQ_INT_MASK 0xc29 #define QM_EQ_EVENT_IRQ_VECTOR 034 #define QM_MB_CMD_SQC 0x035 #define QM_MB_CMD_CQC 0x136 #define QM_MB_CMD_EQC 0x237 #define QM_MB_CMD_AEQC 0x338 #define QM_MB_CMD_SQC_BT 0x4[all …]
13 #define RISC_CNT_INC 0x0001000014 #define RISC_CNT_RESET 0x0003000015 #define RISC_IRQ1 0x0100000016 #define RISC_IRQ2 0x0200000017 #define RISC_EOL 0x0400000018 #define RISC_SOL 0x0800000019 #define RISC_WRITE 0x1000000020 #define RISC_SKIP 0x2000000021 #define RISC_JUMP 0x7000000022 #define RISC_SYNC 0x80000000[all …]