1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * mcf5282.h -- Definitions for Motorola Coldfire 5282 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /****************************************************************************/ 8*4882a593Smuzhiyun #ifndef m5282_h 9*4882a593Smuzhiyun #define m5282_h 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /********************************************************************* 12*4882a593Smuzhiyun * PLL Clock Module 13*4882a593Smuzhiyun *********************************************************************/ 14*4882a593Smuzhiyun /* Bit definitions and macros for PLL_SYNCR */ 15*4882a593Smuzhiyun #define PLL_SYNCR_LOLRE (0x8000) 16*4882a593Smuzhiyun #define PLL_SYNCR_MFD2 (0x4000) 17*4882a593Smuzhiyun #define PLL_SYNCR_MFD1 (0x2000) 18*4882a593Smuzhiyun #define PLL_SYNCR_MFD0 (0x1000) 19*4882a593Smuzhiyun #define PLL_SYNCR_LOCRE (0x0800) 20*4882a593Smuzhiyun #define PLL_SYNCR_RFC2 (0x0400) 21*4882a593Smuzhiyun #define PLL_SYNCR_RFC1 (0x0200) 22*4882a593Smuzhiyun #define PLL_SYNCR_RFC0 (0x0100) 23*4882a593Smuzhiyun #define PLL_SYNCR_LOCEN (0x0080) 24*4882a593Smuzhiyun #define PLL_SYNCR_DISCLK (0x0040) 25*4882a593Smuzhiyun #define PLL_SYNCR_FWKUP (0x0020) 26*4882a593Smuzhiyun #define PLL_SYNCR_STPMD1 (0x0008) 27*4882a593Smuzhiyun #define PLL_SYNCR_STPMD0 (0x0004) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Bit definitions and macros for PLL_SYNSR */ 30*4882a593Smuzhiyun #define PLL_SYNSR_MODE (0x0080) 31*4882a593Smuzhiyun #define PLL_SYNSR_PLLSEL (0x0040) 32*4882a593Smuzhiyun #define PLL_SYNSR_PLLREF (0x0020) 33*4882a593Smuzhiyun #define PLL_SYNSR_LOCKS (0x0010) 34*4882a593Smuzhiyun #define PLL_SYNSR_LOCK (0x0008) 35*4882a593Smuzhiyun #define PLL_SYNSR_LOCS (0x0004) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /********************************************************************* 38*4882a593Smuzhiyun * Interrupt Controller (INTC) 39*4882a593Smuzhiyun *********************************************************************/ 40*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 41*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 42*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 43*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 44*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 45*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 46*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 47*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 48*4882a593Smuzhiyun #define INT0_LO_SCM_SWT1 (8) 49*4882a593Smuzhiyun #define INT0_LO_DMA_00 (9) 50*4882a593Smuzhiyun #define INT0_LO_DMA_01 (10) 51*4882a593Smuzhiyun #define INT0_LO_DMA_02 (11) 52*4882a593Smuzhiyun #define INT0_LO_DMA_03 (12) 53*4882a593Smuzhiyun #define INT0_LO_UART0 (13) 54*4882a593Smuzhiyun #define INT0_LO_UART1 (14) 55*4882a593Smuzhiyun #define INT0_LO_UART2 (15) 56*4882a593Smuzhiyun #define INT0_LO_RSVD1 (16) 57*4882a593Smuzhiyun #define INT0_LO_I2C (17) 58*4882a593Smuzhiyun #define INT0_LO_QSPI (18) 59*4882a593Smuzhiyun #define INT0_LO_DTMR0 (19) 60*4882a593Smuzhiyun #define INT0_LO_DTMR1 (20) 61*4882a593Smuzhiyun #define INT0_LO_DTMR2 (21) 62*4882a593Smuzhiyun #define INT0_LO_DTMR3 (22) 63*4882a593Smuzhiyun #define INT0_LO_FEC_TXF (23) 64*4882a593Smuzhiyun #define INT0_LO_FEC_TXB (24) 65*4882a593Smuzhiyun #define INT0_LO_FEC_UN (25) 66*4882a593Smuzhiyun #define INT0_LO_FEC_RL (26) 67*4882a593Smuzhiyun #define INT0_LO_FEC_RXF (27) 68*4882a593Smuzhiyun #define INT0_LO_FEC_RXB (28) 69*4882a593Smuzhiyun #define INT0_LO_FEC_MII (29) 70*4882a593Smuzhiyun #define INT0_LO_FEC_LC (30) 71*4882a593Smuzhiyun #define INT0_LO_FEC_HBERR (31) 72*4882a593Smuzhiyun #define INT0_HI_FEC_GRA (32) 73*4882a593Smuzhiyun #define INT0_HI_FEC_EBERR (33) 74*4882a593Smuzhiyun #define INT0_HI_FEC_BABT (34) 75*4882a593Smuzhiyun #define INT0_HI_FEC_BABR (35) 76*4882a593Smuzhiyun #define INT0_HI_PMM_LVDF (36) 77*4882a593Smuzhiyun #define INT0_HI_QADC_CF1 (37) 78*4882a593Smuzhiyun #define INT0_HI_QADC_CF2 (38) 79*4882a593Smuzhiyun #define INT0_HI_QADC_PF1 (39) 80*4882a593Smuzhiyun #define INT0_HI_QADC_PF2 (40) 81*4882a593Smuzhiyun #define INT0_HI_GPTA_TOF (41) 82*4882a593Smuzhiyun #define INT0_HI_GPTA_PAIF (42) 83*4882a593Smuzhiyun #define INT0_HI_GPTA_PAOVF (43) 84*4882a593Smuzhiyun #define INT0_HI_GPTA_C0F (44) 85*4882a593Smuzhiyun #define INT0_HI_GPTA_C1F (45) 86*4882a593Smuzhiyun #define INT0_HI_GPTA_C2F (46) 87*4882a593Smuzhiyun #define INT0_HI_GPTA_C3F (47) 88*4882a593Smuzhiyun #define INT0_HI_GPTB_TOF (48) 89*4882a593Smuzhiyun #define INT0_HI_GPTB_PAIF (49) 90*4882a593Smuzhiyun #define INT0_HI_GPTB_PAOVF (50) 91*4882a593Smuzhiyun #define INT0_HI_GPTB_C0F (51) 92*4882a593Smuzhiyun #define INT0_HI_GPTB_C1F (52) 93*4882a593Smuzhiyun #define INT0_HI_GPTB_C2F (53) 94*4882a593Smuzhiyun #define INT0_HI_GPTB_C3F (54) 95*4882a593Smuzhiyun #define INT0_HI_PIT0 (55) 96*4882a593Smuzhiyun #define INT0_HI_PIT1 (56) 97*4882a593Smuzhiyun #define INT0_HI_PIT2 (57) 98*4882a593Smuzhiyun #define INT0_HI_PIT3 (58) 99*4882a593Smuzhiyun #define INT0_HI_CFM_CBEIF (59) 100*4882a593Smuzhiyun #define INT0_HI_CFM_CCIF (60) 101*4882a593Smuzhiyun #define INT0_HI_CFM_PVIF (61) 102*4882a593Smuzhiyun #define INT0_HI_CFM_AEIF (62) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * Size of internal RAM 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define INT_RAM_SIZE 65536 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* General Purpose I/O Module GPIO */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) 113*4882a593Smuzhiyun #define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) 114*4882a593Smuzhiyun #define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) 115*4882a593Smuzhiyun #define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) 116*4882a593Smuzhiyun #define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) 117*4882a593Smuzhiyun #define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) 118*4882a593Smuzhiyun #define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) 119*4882a593Smuzhiyun #define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) 120*4882a593Smuzhiyun #define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) 121*4882a593Smuzhiyun #define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) 122*4882a593Smuzhiyun #define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) 123*4882a593Smuzhiyun #define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) 124*4882a593Smuzhiyun #define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) 125*4882a593Smuzhiyun #define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) 126*4882a593Smuzhiyun #define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) 127*4882a593Smuzhiyun #define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) 128*4882a593Smuzhiyun #define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) 129*4882a593Smuzhiyun #define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) 132*4882a593Smuzhiyun #define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) 133*4882a593Smuzhiyun #define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) 134*4882a593Smuzhiyun #define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) 135*4882a593Smuzhiyun #define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) 136*4882a593Smuzhiyun #define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) 137*4882a593Smuzhiyun #define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) 138*4882a593Smuzhiyun #define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) 139*4882a593Smuzhiyun #define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) 140*4882a593Smuzhiyun #define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) 141*4882a593Smuzhiyun #define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) 142*4882a593Smuzhiyun #define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) 143*4882a593Smuzhiyun #define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) 144*4882a593Smuzhiyun #define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) 145*4882a593Smuzhiyun #define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) 146*4882a593Smuzhiyun #define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) 147*4882a593Smuzhiyun #define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) 148*4882a593Smuzhiyun #define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) 151*4882a593Smuzhiyun #define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) 152*4882a593Smuzhiyun #define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) 153*4882a593Smuzhiyun #define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) 154*4882a593Smuzhiyun #define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) 155*4882a593Smuzhiyun #define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) 156*4882a593Smuzhiyun #define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) 157*4882a593Smuzhiyun #define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) 158*4882a593Smuzhiyun #define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) 159*4882a593Smuzhiyun #define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) 160*4882a593Smuzhiyun #define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) 161*4882a593Smuzhiyun #define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) 162*4882a593Smuzhiyun #define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) 163*4882a593Smuzhiyun #define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) 164*4882a593Smuzhiyun #define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) 165*4882a593Smuzhiyun #define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) 166*4882a593Smuzhiyun #define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) 167*4882a593Smuzhiyun #define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) 170*4882a593Smuzhiyun #define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) 171*4882a593Smuzhiyun #define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) 172*4882a593Smuzhiyun #define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) 173*4882a593Smuzhiyun #define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) 174*4882a593Smuzhiyun #define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) 175*4882a593Smuzhiyun #define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) 176*4882a593Smuzhiyun #define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) 177*4882a593Smuzhiyun #define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) 178*4882a593Smuzhiyun #define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) 179*4882a593Smuzhiyun #define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) 180*4882a593Smuzhiyun #define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) 181*4882a593Smuzhiyun #define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) 182*4882a593Smuzhiyun #define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) 183*4882a593Smuzhiyun #define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) 184*4882a593Smuzhiyun #define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) 185*4882a593Smuzhiyun #define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) 186*4882a593Smuzhiyun #define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) 189*4882a593Smuzhiyun #define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) 190*4882a593Smuzhiyun #define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) 191*4882a593Smuzhiyun #define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) 192*4882a593Smuzhiyun #define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) 193*4882a593Smuzhiyun #define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) 194*4882a593Smuzhiyun #define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) 195*4882a593Smuzhiyun #define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) 196*4882a593Smuzhiyun #define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) 197*4882a593Smuzhiyun #define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) 198*4882a593Smuzhiyun #define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) 199*4882a593Smuzhiyun #define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) 200*4882a593Smuzhiyun #define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) 201*4882a593Smuzhiyun #define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) 202*4882a593Smuzhiyun #define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) 203*4882a593Smuzhiyun #define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) 204*4882a593Smuzhiyun #define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) 205*4882a593Smuzhiyun #define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) 208*4882a593Smuzhiyun #define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) 209*4882a593Smuzhiyun #define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) 210*4882a593Smuzhiyun #define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) 211*4882a593Smuzhiyun #define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) 212*4882a593Smuzhiyun #define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) 213*4882a593Smuzhiyun #define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) 214*4882a593Smuzhiyun #define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) 215*4882a593Smuzhiyun #define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) 216*4882a593Smuzhiyun #define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) 217*4882a593Smuzhiyun #define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* Bit level definitions and macros */ 220*4882a593Smuzhiyun #define MCFGPIO_PORT7 (0x80) 221*4882a593Smuzhiyun #define MCFGPIO_PORT6 (0x40) 222*4882a593Smuzhiyun #define MCFGPIO_PORT5 (0x20) 223*4882a593Smuzhiyun #define MCFGPIO_PORT4 (0x10) 224*4882a593Smuzhiyun #define MCFGPIO_PORT3 (0x08) 225*4882a593Smuzhiyun #define MCFGPIO_PORT2 (0x04) 226*4882a593Smuzhiyun #define MCFGPIO_PORT1 (0x02) 227*4882a593Smuzhiyun #define MCFGPIO_PORT0 (0x01) 228*4882a593Smuzhiyun #define MCFGPIO_PORT(x) (0x01<<x) 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define MCFGPIO_DDR7 (0x80) 231*4882a593Smuzhiyun #define MCFGPIO_DDR6 (0x40) 232*4882a593Smuzhiyun #define MCFGPIO_DDR5 (0x20) 233*4882a593Smuzhiyun #define MCFGPIO_DDR4 (0x10) 234*4882a593Smuzhiyun #define MCFGPIO_DDR3 (0x08) 235*4882a593Smuzhiyun #define MCFGPIO_DDR2 (0x04) 236*4882a593Smuzhiyun #define MCFGPIO_DDR1 (0x02) 237*4882a593Smuzhiyun #define MCFGPIO_DDR0 (0x01) 238*4882a593Smuzhiyun #define MCFGPIO_DDR(x) (0x01<<x) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define MCFGPIO_Px7 (0x80) 241*4882a593Smuzhiyun #define MCFGPIO_Px6 (0x40) 242*4882a593Smuzhiyun #define MCFGPIO_Px5 (0x20) 243*4882a593Smuzhiyun #define MCFGPIO_Px4 (0x10) 244*4882a593Smuzhiyun #define MCFGPIO_Px3 (0x08) 245*4882a593Smuzhiyun #define MCFGPIO_Px2 (0x04) 246*4882a593Smuzhiyun #define MCFGPIO_Px1 (0x02) 247*4882a593Smuzhiyun #define MCFGPIO_Px0 (0x01) 248*4882a593Smuzhiyun #define MCFGPIO_Px(x) (0x01<<x) 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #define MCFGPIO_PBCDPAR_PBPA (0x80) 251*4882a593Smuzhiyun #define MCFGPIO_PBCDPAR_PCDPA (0x40) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA7 (0x4000) 254*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA6 (0x1000) 255*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA5 (0x0400) 256*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA4 (0x0100) 257*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA3 (0x0040) 258*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA2 (0x0010) 259*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) 260*4882a593Smuzhiyun #define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3)) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define MCFGPIO_PFPAR_PFPA7 (0x80) 263*4882a593Smuzhiyun #define MCFGPIO_PFPAR_PFPA6 (0x40) 264*4882a593Smuzhiyun #define MCFGPIO_PFPAR_PFPA5 (0x20) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA7 (0x80) 267*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA6 (0x40) 268*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA5 (0x20) 269*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA4 (0x10) 270*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA3 (0x08) 271*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA2 (0x04) 272*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA1 (0x02) 273*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA0 (0x01) 274*4882a593Smuzhiyun #define MCFGPIO_PJPAR_PJPA(x) (0x01<<x) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define MCFGPIO_PSDPAR_PSDPA (0x80) 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) 279*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) 280*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) 281*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) 282*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) 283*4882a593Smuzhiyun #define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3)) 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define MCFGPIO_PEHLPAR_PEHPA (0x80) 286*4882a593Smuzhiyun #define MCFGPIO_PEHLPAR_PELPA (0x40) 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA6 (0x40) 289*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA5 (0x20) 290*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA4 (0x10) 291*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA3 (0x08) 292*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA2 (0x04) 293*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA1 (0x02) 294*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA0 (0x01) 295*4882a593Smuzhiyun #define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x) 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) 298*4882a593Smuzhiyun #define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) 299*4882a593Smuzhiyun #define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) 300*4882a593Smuzhiyun #define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) 303*4882a593Smuzhiyun #define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) 304*4882a593Smuzhiyun #define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) 305*4882a593Smuzhiyun #define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #define MCFGPIO_PUAPAR_PUAPA3 (0x08) 308*4882a593Smuzhiyun #define MCFGPIO_PUAPAR_PUAPA2 (0x04) 309*4882a593Smuzhiyun #define MCFGPIO_PUAPAR_PUAPA1 (0x02) 310*4882a593Smuzhiyun #define MCFGPIO_PUAPAR_PUAPA0 (0x01) 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun /* System Conrol Module SCM */ 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) 315*4882a593Smuzhiyun #define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) 316*4882a593Smuzhiyun #define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) 317*4882a593Smuzhiyun #define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) 318*4882a593Smuzhiyun #define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) 321*4882a593Smuzhiyun #define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) 322*4882a593Smuzhiyun #define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) 323*4882a593Smuzhiyun #define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) 324*4882a593Smuzhiyun #define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) 325*4882a593Smuzhiyun #define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) 326*4882a593Smuzhiyun #define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) 327*4882a593Smuzhiyun #define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) 328*4882a593Smuzhiyun #define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) 329*4882a593Smuzhiyun #define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) 330*4882a593Smuzhiyun #define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) 331*4882a593Smuzhiyun #define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) 332*4882a593Smuzhiyun #define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun #define MCFSCM_CRSR_EXT (0x80) 335*4882a593Smuzhiyun #define MCFSCM_CRSR_CWDR (0x20) 336*4882a593Smuzhiyun #define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000) 337*4882a593Smuzhiyun #define MCFSCM_RAMBAR_BDE (0x00000200) 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun /* Reset Controller Module RCM */ 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) 342*4882a593Smuzhiyun #define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define MCFRESET_RCR_SOFTRST (0x80) 345*4882a593Smuzhiyun #define MCFRESET_RCR_FRCRSTOUT (0x40) 346*4882a593Smuzhiyun #define MCFRESET_RCR_LVDF (0x10) 347*4882a593Smuzhiyun #define MCFRESET_RCR_LVDIE (0x08) 348*4882a593Smuzhiyun #define MCFRESET_RCR_LVDRE (0x04) 349*4882a593Smuzhiyun #define MCFRESET_RCR_LVDE (0x01) 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun #define MCFRESET_RSR_LVD (0x40) 352*4882a593Smuzhiyun #define MCFRESET_RSR_SOFT (0x20) 353*4882a593Smuzhiyun #define MCFRESET_RSR_WDR (0x10) 354*4882a593Smuzhiyun #define MCFRESET_RSR_POR (0x08) 355*4882a593Smuzhiyun #define MCFRESET_RSR_EXT (0x04) 356*4882a593Smuzhiyun #define MCFRESET_RSR_LOC (0x02) 357*4882a593Smuzhiyun #define MCFRESET_RSR_LOL (0x01) 358*4882a593Smuzhiyun #define MCFRESET_RSR_ALL (0x7F) 359*4882a593Smuzhiyun #define MCFRESET_RCR_SOFTRST (0x80) 360*4882a593Smuzhiyun #define MCFRESET_RCR_FRCRSTOUT (0x40) 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /* Chip Configuration Module CCM */ 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun #define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) 365*4882a593Smuzhiyun #define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) 366*4882a593Smuzhiyun #define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /* Bit level definitions and macros */ 369*4882a593Smuzhiyun #define MCFCCM_CCR_LOAD (0x8000) 370*4882a593Smuzhiyun #define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) 371*4882a593Smuzhiyun #define MCFCCM_CCR_SZEN (0x0040) 372*4882a593Smuzhiyun #define MCFCCM_CCR_PSTEN (0x0020) 373*4882a593Smuzhiyun #define MCFCCM_CCR_BME (0x0008) 374*4882a593Smuzhiyun #define MCFCCM_CCR_BMT(x) (((x)&0x0007)) 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun #define MCFCCM_CIR_PIN_MASK (0xFF00) 377*4882a593Smuzhiyun #define MCFCCM_CIR_PRN_MASK (0x00FF) 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* Clock Module */ 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun #define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) 382*4882a593Smuzhiyun #define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) 385*4882a593Smuzhiyun #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) 386*4882a593Smuzhiyun #define MCFCLOCK_SYNSR_LOCK 0x08 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) 389*4882a593Smuzhiyun #define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) 390*4882a593Smuzhiyun #define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) 391*4882a593Smuzhiyun #define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) 392*4882a593Smuzhiyun #define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun #define MCFSDRAMC_DCR_NAM (0x2000) 395*4882a593Smuzhiyun #define MCFSDRAMC_DCR_COC (0x1000) 396*4882a593Smuzhiyun #define MCFSDRAMC_DCR_IS (0x0800) 397*4882a593Smuzhiyun #define MCFSDRAMC_DCR_RTIM_3 (0x0000) 398*4882a593Smuzhiyun #define MCFSDRAMC_DCR_RTIM_6 (0x0200) 399*4882a593Smuzhiyun #define MCFSDRAMC_DCR_RTIM_9 (0x0400) 400*4882a593Smuzhiyun #define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF) 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) 403*4882a593Smuzhiyun #define MCFSDRAMC_DACR_RE (0x00008000) 404*4882a593Smuzhiyun #define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12) 405*4882a593Smuzhiyun #define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8) 406*4882a593Smuzhiyun #define MCFSDRAMC_DACR_PS_32 (0x00000000) 407*4882a593Smuzhiyun #define MCFSDRAMC_DACR_PS_16 (0x00000020) 408*4882a593Smuzhiyun #define MCFSDRAMC_DACR_PS_8 (0x00000010) 409*4882a593Smuzhiyun #define MCFSDRAMC_DACR_IP (0x00000008) 410*4882a593Smuzhiyun #define MCFSDRAMC_DACR_IMRS (0x00000040) 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define MCFSDRAMC_DMR_BAM_16M (0x00FC0000) 413*4882a593Smuzhiyun #define MCFSDRAMC_DMR_WP (0x00000100) 414*4882a593Smuzhiyun #define MCFSDRAMC_DMR_CI (0x00000040) 415*4882a593Smuzhiyun #define MCFSDRAMC_DMR_AM (0x00000020) 416*4882a593Smuzhiyun #define MCFSDRAMC_DMR_SC (0x00000010) 417*4882a593Smuzhiyun #define MCFSDRAMC_DMR_SD (0x00000008) 418*4882a593Smuzhiyun #define MCFSDRAMC_DMR_UC (0x00000004) 419*4882a593Smuzhiyun #define MCFSDRAMC_DMR_UD (0x00000002) 420*4882a593Smuzhiyun #define MCFSDRAMC_DMR_V (0x00000001) 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun #define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) 423*4882a593Smuzhiyun #define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) 424*4882a593Smuzhiyun #define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) 425*4882a593Smuzhiyun #define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /********************************************************************* 428*4882a593Smuzhiyun * General Purpose Timer (GPT) Module 429*4882a593Smuzhiyun *********************************************************************/ 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) 432*4882a593Smuzhiyun #define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) 433*4882a593Smuzhiyun #define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) 434*4882a593Smuzhiyun #define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) 435*4882a593Smuzhiyun #define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) 436*4882a593Smuzhiyun #define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) 437*4882a593Smuzhiyun #define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) 438*4882a593Smuzhiyun #define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) 439*4882a593Smuzhiyun #define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) 440*4882a593Smuzhiyun #define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) 441*4882a593Smuzhiyun #define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) 442*4882a593Smuzhiyun #define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) 443*4882a593Smuzhiyun #define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) 444*4882a593Smuzhiyun #define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) 445*4882a593Smuzhiyun #define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) 446*4882a593Smuzhiyun #define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) 447*4882a593Smuzhiyun #define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) 448*4882a593Smuzhiyun #define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) 449*4882a593Smuzhiyun #define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) 450*4882a593Smuzhiyun #define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) 451*4882a593Smuzhiyun #define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) 452*4882a593Smuzhiyun #define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun #define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) 455*4882a593Smuzhiyun #define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) 456*4882a593Smuzhiyun #define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) 457*4882a593Smuzhiyun #define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) 458*4882a593Smuzhiyun #define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) 459*4882a593Smuzhiyun #define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) 460*4882a593Smuzhiyun #define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) 461*4882a593Smuzhiyun #define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) 462*4882a593Smuzhiyun #define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) 463*4882a593Smuzhiyun #define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) 464*4882a593Smuzhiyun #define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) 465*4882a593Smuzhiyun #define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) 466*4882a593Smuzhiyun #define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) 467*4882a593Smuzhiyun #define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) 468*4882a593Smuzhiyun #define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) 469*4882a593Smuzhiyun #define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) 470*4882a593Smuzhiyun #define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) 471*4882a593Smuzhiyun #define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) 472*4882a593Smuzhiyun #define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) 473*4882a593Smuzhiyun #define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) 474*4882a593Smuzhiyun #define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) 475*4882a593Smuzhiyun #define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun /* Bit level definitions and macros */ 478*4882a593Smuzhiyun #define MCFGPT_GPTIOS_IOS3 (0x08) 479*4882a593Smuzhiyun #define MCFGPT_GPTIOS_IOS2 (0x04) 480*4882a593Smuzhiyun #define MCFGPT_GPTIOS_IOS1 (0x02) 481*4882a593Smuzhiyun #define MCFGPT_GPTIOS_IOS0 (0x01) 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #define MCFGPT_GPTCFORC_FOC3 (0x08) 484*4882a593Smuzhiyun #define MCFGPT_GPTCFORC_FOC2 (0x04) 485*4882a593Smuzhiyun #define MCFGPT_GPTCFORC_FOC1 (0x02) 486*4882a593Smuzhiyun #define MCFGPT_GPTCFORC_FOC0 (0x01) 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun #define MCFGPT_GPTOC3M_OC3M3 (0x08) 489*4882a593Smuzhiyun #define MCFGPT_GPTOC3M_OC3M2 (0x04) 490*4882a593Smuzhiyun #define MCFGPT_GPTOC3M_OC3M1 (0x02) 491*4882a593Smuzhiyun #define MCFGPT_GPTOC3M_OC3M0 (0x01) 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun #define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04)) 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun #define MCFGPT_GPTSCR1_GPTEN (0x80) 496*4882a593Smuzhiyun #define MCFGPT_GPTSCR1_TFFCA (0x10) 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun #define MCFGPT_GPTTOV3 (0x08) 499*4882a593Smuzhiyun #define MCFGPT_GPTTOV2 (0x04) 500*4882a593Smuzhiyun #define MCFGPT_GPTTOV1 (0x02) 501*4882a593Smuzhiyun #define MCFGPT_GPTTOV0 (0x01) 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun #define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) 504*4882a593Smuzhiyun #define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) 505*4882a593Smuzhiyun #define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) 506*4882a593Smuzhiyun #define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03)) 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun #define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) 509*4882a593Smuzhiyun #define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) 510*4882a593Smuzhiyun #define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) 511*4882a593Smuzhiyun #define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03)) 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun #define MCFGPT_GPTIE_C3I (0x08) 514*4882a593Smuzhiyun #define MCFGPT_GPTIE_C2I (0x04) 515*4882a593Smuzhiyun #define MCFGPT_GPTIE_C1I (0x02) 516*4882a593Smuzhiyun #define MCFGPT_GPTIE_C0I (0x01) 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun #define MCFGPT_GPTSCR2_TOI (0x80) 519*4882a593Smuzhiyun #define MCFGPT_GPTSCR2_PUPT (0x20) 520*4882a593Smuzhiyun #define MCFGPT_GPTSCR2_RDPT (0x10) 521*4882a593Smuzhiyun #define MCFGPT_GPTSCR2_TCRE (0x08) 522*4882a593Smuzhiyun #define MCFGPT_GPTSCR2_PR(x) (((x)&0x07)) 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun #define MCFGPT_GPTFLG1_C3F (0x08) 525*4882a593Smuzhiyun #define MCFGPT_GPTFLG1_C2F (0x04) 526*4882a593Smuzhiyun #define MCFGPT_GPTFLG1_C1F (0x02) 527*4882a593Smuzhiyun #define MCFGPT_GPTFLG1_C0F (0x01) 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun #define MCFGPT_GPTFLG2_TOF (0x80) 530*4882a593Smuzhiyun #define MCFGPT_GPTFLG2_C3F (0x08) 531*4882a593Smuzhiyun #define MCFGPT_GPTFLG2_C2F (0x04) 532*4882a593Smuzhiyun #define MCFGPT_GPTFLG2_C1F (0x02) 533*4882a593Smuzhiyun #define MCFGPT_GPTFLG2_C0F (0x01) 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_PAE (0x40) 536*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_PAMOD (0x20) 537*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_PEDGE (0x10) 538*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_CLK_PACLK (0x04) 539*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08) 540*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C) 541*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) 542*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_PAOVI (0x02) 543*4882a593Smuzhiyun #define MCFGPT_GPTPACTL_PAI (0x01) 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun #define MCFGPT_GPTPAFLG_PAOVF (0x02) 546*4882a593Smuzhiyun #define MCFGPT_GPTPAFLG_PAIF (0x01) 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun #define MCFGPT_GPTPORT_PORTT3 (0x08) 549*4882a593Smuzhiyun #define MCFGPT_GPTPORT_PORTT2 (0x04) 550*4882a593Smuzhiyun #define MCFGPT_GPTPORT_PORTT1 (0x02) 551*4882a593Smuzhiyun #define MCFGPT_GPTPORT_PORTT0 (0x01) 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun #define MCFGPT_GPTDDR_DDRT3 (0x08) 554*4882a593Smuzhiyun #define MCFGPT_GPTDDR_DDRT2 (0x04) 555*4882a593Smuzhiyun #define MCFGPT_GPTDDR_DDRT1 (0x02) 556*4882a593Smuzhiyun #define MCFGPT_GPTDDR_DDRT0 (0x01) 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun /* Coldfire Flash Module CFM */ 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun #define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) 561*4882a593Smuzhiyun #define MCFCFM_MCR_LOCK (0x0400) 562*4882a593Smuzhiyun #define MCFCFM_MCR_PVIE (0x0200) 563*4882a593Smuzhiyun #define MCFCFM_MCR_AEIE (0x0100) 564*4882a593Smuzhiyun #define MCFCFM_MCR_CBEIE (0x0080) 565*4882a593Smuzhiyun #define MCFCFM_MCR_CCIE (0x0040) 566*4882a593Smuzhiyun #define MCFCFM_MCR_KEYACC (0x0020) 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun #define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) 571*4882a593Smuzhiyun #define MCFCFM_SEC_KEYEN (0x80000000) 572*4882a593Smuzhiyun #define MCFCFM_SEC_SECSTAT (0x40000000) 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun #define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) 575*4882a593Smuzhiyun #define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) 576*4882a593Smuzhiyun #define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) 577*4882a593Smuzhiyun #define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) 578*4882a593Smuzhiyun #define MCFCFM_USTAT_CBEIF 0x80 579*4882a593Smuzhiyun #define MCFCFM_USTAT_CCIF 0x40 580*4882a593Smuzhiyun #define MCFCFM_USTAT_PVIOL 0x20 581*4882a593Smuzhiyun #define MCFCFM_USTAT_ACCERR 0x10 582*4882a593Smuzhiyun #define MCFCFM_USTAT_BLANK 0x04 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun #define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) 585*4882a593Smuzhiyun #define MCFCFM_CMD_ERSVER 0x05 586*4882a593Smuzhiyun #define MCFCFM_CMD_PGERSVER 0x06 587*4882a593Smuzhiyun #define MCFCFM_CMD_PGM 0x20 588*4882a593Smuzhiyun #define MCFCFM_CMD_PGERS 0x40 589*4882a593Smuzhiyun #define MCFCFM_CMD_MASERS 0x41 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun /****************************************************************************/ 592*4882a593Smuzhiyun #endif /* m5282_h */ 593