1*4882a593Smuzhiyun /***************************************************************************** 2*4882a593Smuzhiyun * * 3*4882a593Smuzhiyun * File: elmer0.h * 4*4882a593Smuzhiyun * $Revision: 1.6 $ * 5*4882a593Smuzhiyun * $Date: 2005/06/21 22:49:43 $ * 6*4882a593Smuzhiyun * Description: * 7*4882a593Smuzhiyun * part of the Chelsio 10Gb Ethernet Driver. * 8*4882a593Smuzhiyun * * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify * 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, version 2, as * 11*4882a593Smuzhiyun * published by the Free Software Foundation. * 12*4882a593Smuzhiyun * * 13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along * 14*4882a593Smuzhiyun * with this program; if not, see <http://www.gnu.org/licenses/>. * 15*4882a593Smuzhiyun * * 16*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * 17*4882a593Smuzhiyun * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * 18*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * 19*4882a593Smuzhiyun * * 20*4882a593Smuzhiyun * http://www.chelsio.com * 21*4882a593Smuzhiyun * * 22*4882a593Smuzhiyun * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * 23*4882a593Smuzhiyun * All rights reserved. * 24*4882a593Smuzhiyun * * 25*4882a593Smuzhiyun * Maintainers: maintainers@chelsio.com * 26*4882a593Smuzhiyun * * 27*4882a593Smuzhiyun * Authors: Dimitrios Michailidis <dm@chelsio.com> * 28*4882a593Smuzhiyun * Tina Yang <tainay@chelsio.com> * 29*4882a593Smuzhiyun * Felix Marti <felix@chelsio.com> * 30*4882a593Smuzhiyun * Scott Bardone <sbardone@chelsio.com> * 31*4882a593Smuzhiyun * Kurt Ottaway <kottaway@chelsio.com> * 32*4882a593Smuzhiyun * Frank DiMambro <frank@chelsio.com> * 33*4882a593Smuzhiyun * * 34*4882a593Smuzhiyun * History: * 35*4882a593Smuzhiyun * * 36*4882a593Smuzhiyun ****************************************************************************/ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #ifndef _CXGB_ELMER0_H_ 39*4882a593Smuzhiyun #define _CXGB_ELMER0_H_ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* ELMER0 flavors */ 42*4882a593Smuzhiyun enum { 43*4882a593Smuzhiyun ELMER0_XC2S300E_6FT256_C, 44*4882a593Smuzhiyun ELMER0_XC2S100E_6TQ144_C 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* ELMER0 registers */ 48*4882a593Smuzhiyun #define A_ELMER0_VERSION 0x100000 49*4882a593Smuzhiyun #define A_ELMER0_PHY_CFG 0x100004 50*4882a593Smuzhiyun #define A_ELMER0_INT_ENABLE 0x100008 51*4882a593Smuzhiyun #define A_ELMER0_INT_CAUSE 0x10000c 52*4882a593Smuzhiyun #define A_ELMER0_GPI_CFG 0x100010 53*4882a593Smuzhiyun #define A_ELMER0_GPI_STAT 0x100014 54*4882a593Smuzhiyun #define A_ELMER0_GPO 0x100018 55*4882a593Smuzhiyun #define A_ELMER0_PORT0_MI1_CFG 0x400000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define S_MI1_MDI_ENABLE 0 58*4882a593Smuzhiyun #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) 59*4882a593Smuzhiyun #define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define S_MI1_MDI_INVERT 1 62*4882a593Smuzhiyun #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT) 63*4882a593Smuzhiyun #define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define S_MI1_PREAMBLE_ENABLE 2 66*4882a593Smuzhiyun #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE) 67*4882a593Smuzhiyun #define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define S_MI1_SOF 3 70*4882a593Smuzhiyun #define M_MI1_SOF 0x3 71*4882a593Smuzhiyun #define V_MI1_SOF(x) ((x) << S_MI1_SOF) 72*4882a593Smuzhiyun #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define S_MI1_CLK_DIV 5 75*4882a593Smuzhiyun #define M_MI1_CLK_DIV 0xff 76*4882a593Smuzhiyun #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV) 77*4882a593Smuzhiyun #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define A_ELMER0_PORT0_MI1_ADDR 0x400004 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define S_MI1_REG_ADDR 0 82*4882a593Smuzhiyun #define M_MI1_REG_ADDR 0x1f 83*4882a593Smuzhiyun #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR) 84*4882a593Smuzhiyun #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define S_MI1_PHY_ADDR 5 87*4882a593Smuzhiyun #define M_MI1_PHY_ADDR 0x1f 88*4882a593Smuzhiyun #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR) 89*4882a593Smuzhiyun #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define A_ELMER0_PORT0_MI1_DATA 0x400008 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define S_MI1_DATA 0 94*4882a593Smuzhiyun #define M_MI1_DATA 0xffff 95*4882a593Smuzhiyun #define V_MI1_DATA(x) ((x) << S_MI1_DATA) 96*4882a593Smuzhiyun #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define A_ELMER0_PORT0_MI1_OP 0x40000c 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define S_MI1_OP 0 101*4882a593Smuzhiyun #define M_MI1_OP 0x3 102*4882a593Smuzhiyun #define V_MI1_OP(x) ((x) << S_MI1_OP) 103*4882a593Smuzhiyun #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define S_MI1_ADDR_AUTOINC 2 106*4882a593Smuzhiyun #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC) 107*4882a593Smuzhiyun #define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define S_MI1_OP_BUSY 31 110*4882a593Smuzhiyun #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) 111*4882a593Smuzhiyun #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define A_ELMER0_PORT1_MI1_CFG 0x500000 114*4882a593Smuzhiyun #define A_ELMER0_PORT1_MI1_ADDR 0x500004 115*4882a593Smuzhiyun #define A_ELMER0_PORT1_MI1_DATA 0x500008 116*4882a593Smuzhiyun #define A_ELMER0_PORT1_MI1_OP 0x50000c 117*4882a593Smuzhiyun #define A_ELMER0_PORT2_MI1_CFG 0x600000 118*4882a593Smuzhiyun #define A_ELMER0_PORT2_MI1_ADDR 0x600004 119*4882a593Smuzhiyun #define A_ELMER0_PORT2_MI1_DATA 0x600008 120*4882a593Smuzhiyun #define A_ELMER0_PORT2_MI1_OP 0x60000c 121*4882a593Smuzhiyun #define A_ELMER0_PORT3_MI1_CFG 0x700000 122*4882a593Smuzhiyun #define A_ELMER0_PORT3_MI1_ADDR 0x700004 123*4882a593Smuzhiyun #define A_ELMER0_PORT3_MI1_DATA 0x700008 124*4882a593Smuzhiyun #define A_ELMER0_PORT3_MI1_OP 0x70000c 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Simple bit definition for GPI and GP0 registers. */ 127*4882a593Smuzhiyun #define ELMER0_GP_BIT0 0x0001 128*4882a593Smuzhiyun #define ELMER0_GP_BIT1 0x0002 129*4882a593Smuzhiyun #define ELMER0_GP_BIT2 0x0004 130*4882a593Smuzhiyun #define ELMER0_GP_BIT3 0x0008 131*4882a593Smuzhiyun #define ELMER0_GP_BIT4 0x0010 132*4882a593Smuzhiyun #define ELMER0_GP_BIT5 0x0020 133*4882a593Smuzhiyun #define ELMER0_GP_BIT6 0x0040 134*4882a593Smuzhiyun #define ELMER0_GP_BIT7 0x0080 135*4882a593Smuzhiyun #define ELMER0_GP_BIT8 0x0100 136*4882a593Smuzhiyun #define ELMER0_GP_BIT9 0x0200 137*4882a593Smuzhiyun #define ELMER0_GP_BIT10 0x0400 138*4882a593Smuzhiyun #define ELMER0_GP_BIT11 0x0800 139*4882a593Smuzhiyun #define ELMER0_GP_BIT12 0x1000 140*4882a593Smuzhiyun #define ELMER0_GP_BIT13 0x2000 141*4882a593Smuzhiyun #define ELMER0_GP_BIT14 0x4000 142*4882a593Smuzhiyun #define ELMER0_GP_BIT15 0x8000 143*4882a593Smuzhiyun #define ELMER0_GP_BIT16 0x10000 144*4882a593Smuzhiyun #define ELMER0_GP_BIT17 0x20000 145*4882a593Smuzhiyun #define ELMER0_GP_BIT18 0x40000 146*4882a593Smuzhiyun #define ELMER0_GP_BIT19 0x80000 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define MI1_OP_DIRECT_WRITE 1 149*4882a593Smuzhiyun #define MI1_OP_DIRECT_READ 2 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define MI1_OP_INDIRECT_ADDRESS 0 152*4882a593Smuzhiyun #define MI1_OP_INDIRECT_WRITE 1 153*4882a593Smuzhiyun #define MI1_OP_INDIRECT_READ_INC 2 154*4882a593Smuzhiyun #define MI1_OP_INDIRECT_READ 3 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #endif /* _CXGB_ELMER0_H_ */ 157*4882a593Smuzhiyun 158