1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Christophe Kerello <christophe.kerello@st.com> 11*4882a593Smuzhiyun - Patrice Chotard <patrice.chotard@st.com> 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunallOf: 14*4882a593Smuzhiyun - $ref: "spi-controller.yaml#" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: st,stm32f469-qspi 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - description: registers 23*4882a593Smuzhiyun - description: memory mapping 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg-names: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - const: qspi 28*4882a593Smuzhiyun - const: qspi_mm 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupts: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun resets: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun dmas: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - description: tx DMA channel 42*4882a593Smuzhiyun - description: rx DMA channel 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun dma-names: 45*4882a593Smuzhiyun items: 46*4882a593Smuzhiyun - const: tx 47*4882a593Smuzhiyun - const: rx 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunrequired: 50*4882a593Smuzhiyun - compatible 51*4882a593Smuzhiyun - reg 52*4882a593Smuzhiyun - reg-names 53*4882a593Smuzhiyun - clocks 54*4882a593Smuzhiyun - interrupts 55*4882a593Smuzhiyun 56*4882a593SmuzhiyununevaluatedProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 61*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 62*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 63*4882a593Smuzhiyun spi@58003000 { 64*4882a593Smuzhiyun compatible = "st,stm32f469-qspi"; 65*4882a593Smuzhiyun reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 66*4882a593Smuzhiyun reg-names = "qspi", "qspi_mm"; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 68*4882a593Smuzhiyun dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, 69*4882a593Smuzhiyun <&mdma1 22 0x10 0x100008 0x0 0x0>; 70*4882a593Smuzhiyun dma-names = "tx", "rx"; 71*4882a593Smuzhiyun clocks = <&rcc QSPI_K>; 72*4882a593Smuzhiyun resets = <&rcc QSPI_R>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #address-cells = <1>; 75*4882a593Smuzhiyun #size-cells = <0>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun flash@0 { 78*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 79*4882a593Smuzhiyun reg = <0>; 80*4882a593Smuzhiyun spi-rx-bus-width = <4>; 81*4882a593Smuzhiyun spi-max-frequency = <108000000>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun... 86