1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * mcf5271.h -- Definitions for Motorola Coldfire 5271 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com> 5*4882a593Smuzhiyun * Based on mcf5272sim.h of uCLinux distribution: 6*4882a593Smuzhiyun * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 7*4882a593Smuzhiyun * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _MCF5271_H_ 13*4882a593Smuzhiyun #define _MCF5271_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) 16*4882a593Smuzhiyun #define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) 17*4882a593Smuzhiyun #define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) 18*4882a593Smuzhiyun #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y 19*4882a593Smuzhiyun #define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y 20*4882a593Smuzhiyun #define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MCF_FMPLL_SYNCR 0x120000 23*4882a593Smuzhiyun #define MCF_FMPLL_SYNSR 0x120004 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) 26*4882a593Smuzhiyun #define MCF_SYNCR_MFD_4X 0x00000000 27*4882a593Smuzhiyun #define MCF_SYNCR_MFD_6X 0x01000000 28*4882a593Smuzhiyun #define MCF_SYNCR_MFD_8X 0x02000000 29*4882a593Smuzhiyun #define MCF_SYNCR_MFD_10X 0x03000000 30*4882a593Smuzhiyun #define MCF_SYNCR_MFD_12X 0x04000000 31*4882a593Smuzhiyun #define MCF_SYNCR_MFD_14X 0x05000000 32*4882a593Smuzhiyun #define MCF_SYNCR_MFD_16X 0x06000000 33*4882a593Smuzhiyun #define MCF_SYNCR_MFD_18X 0x07000000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) 36*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV1 0x00000000 37*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV2 0x00080000 38*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV4 0x00100000 39*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV8 0x00180000 40*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV16 0x00200000 41*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV32 0x00280000 42*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV64 0x00300000 43*4882a593Smuzhiyun #define MCF_SYNCR_RFD_DIV128 0x00380000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MCF_FMPLL_SYNSR_LOCK 0x8 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MCF_WTM_WCR 0x140000 48*4882a593Smuzhiyun #define MCF_WTM_WCNTR 0x140004 49*4882a593Smuzhiyun #define MCF_WTM_WSR 0x140006 50*4882a593Smuzhiyun #define MCF_WTM_WCR_EN 0x0001 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MCF_RCM_RCR 0x110000 53*4882a593Smuzhiyun #define MCF_RCM_RCR_FRCRSTOUT 0x40 54*4882a593Smuzhiyun #define MCF_RCM_RCR_SOFTRST 0x80 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MCF_GPIO_PODR_ADDR 0x100000 57*4882a593Smuzhiyun #define MCF_GPIO_PODR_DATAH 0x100001 58*4882a593Smuzhiyun #define MCF_GPIO_PODR_DATAL 0x100002 59*4882a593Smuzhiyun #define MCF_GPIO_PODR_BUSCTL 0x100003 60*4882a593Smuzhiyun #define MCF_GPIO_PODR_BS 0x100004 61*4882a593Smuzhiyun #define MCF_GPIO_PODR_CS 0x100005 62*4882a593Smuzhiyun #define MCF_GPIO_PODR_SDRAM 0x100006 63*4882a593Smuzhiyun #define MCF_GPIO_PODR_FECI2C 0x100007 64*4882a593Smuzhiyun #define MCF_GPIO_PODR_UARTH 0x100008 65*4882a593Smuzhiyun #define MCF_GPIO_PODR_UARTL 0x100009 66*4882a593Smuzhiyun #define MCF_GPIO_PODR_QSPI 0x10000A 67*4882a593Smuzhiyun #define MCF_GPIO_PODR_TIMER 0x10000B 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define MCF_GPIO_PDDR_ADDR 0x100010 70*4882a593Smuzhiyun #define MCF_GPIO_PDDR_DATAH 0x100011 71*4882a593Smuzhiyun #define MCF_GPIO_PDDR_DATAL 0x100012 72*4882a593Smuzhiyun #define MCF_GPIO_PDDR_BUSCTL 0x100013 73*4882a593Smuzhiyun #define MCF_GPIO_PDDR_BS 0x100014 74*4882a593Smuzhiyun #define MCF_GPIO_PDDR_CS 0x100015 75*4882a593Smuzhiyun #define MCF_GPIO_PDDR_SDRAM 0x100016 76*4882a593Smuzhiyun #define MCF_GPIO_PDDR_FECI2C 0x100017 77*4882a593Smuzhiyun #define MCF_GPIO_PDDR_UARTH 0x100018 78*4882a593Smuzhiyun #define MCF_GPIO_PDDR_UARTL 0x100019 79*4882a593Smuzhiyun #define MCF_GPIO_PDDR_QSPI 0x10001A 80*4882a593Smuzhiyun #define MCF_GPIO_PDDR_TIMER 0x10001B 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_ADDR 0x100020 83*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_DATAH 0x100021 84*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_DATAL 0x100022 85*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_BUSCTL 0x100023 86*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_BS 0x100024 87*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_CS 0x100025 88*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_SDRAM 0x100026 89*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_FECI2C 0x100027 90*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_UARTH 0x100028 91*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_UARTL 0x100029 92*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_QSPI 0x10002A 93*4882a593Smuzhiyun #define MCF_GPIO_PPDSDR_TIMER 0x10002B 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_ADDR 0x100030 96*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_DATAH 0x100031 97*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_DATAL 0x100032 98*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_BUSCTL 0x100033 99*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_BS 0x100034 100*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_CS 0x100035 101*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_SDRAM 0x100036 102*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_FECI2C 0x100037 103*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_UARTH 0x100038 104*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_UARTL 0x100039 105*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_QSPI 0x10003A 106*4882a593Smuzhiyun #define MCF_GPIO_PCLRR_TIMER 0x10003B 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define MCF_GPIO_PAR_AD 0x100040 109*4882a593Smuzhiyun #define MCF_GPIO_PAR_BUSCTL 0x100042 110*4882a593Smuzhiyun #define MCF_GPIO_PAR_BS 0x100044 111*4882a593Smuzhiyun #define MCF_GPIO_PAR_CS 0x100045 112*4882a593Smuzhiyun #define MCF_GPIO_PAR_SDRAM 0x100046 113*4882a593Smuzhiyun #define MCF_GPIO_PAR_FECI2C 0x100047 114*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART 0x100048 115*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI 0x10004A 116*4882a593Smuzhiyun #define MCF_GPIO_PAR_TIMER 0x10004C 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define MCF_DSCR_EIM 0x100050 119*4882a593Smuzhiyun #define MCF_DCSR_FEC12C 0x100052 120*4882a593Smuzhiyun #define MCF_DCSR_UART 0x100053 121*4882a593Smuzhiyun #define MCF_DCSR_QSPI 0x100054 122*4882a593Smuzhiyun #define MCF_DCSR_TIMER 0x100055 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define MCF_CCM_CIR 0x11000A 125*4882a593Smuzhiyun #define MCF_CCM_CIR_PRN_MASK 0x3F 126*4882a593Smuzhiyun #define MCF_CCM_CIR_PIN_LEN 6 127*4882a593Smuzhiyun #define MCF_CCM_CIR_PIN_MCF5270 0x002e 128*4882a593Smuzhiyun #define MCF_CCM_CIR_PIN_MCF5271 0x0032 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define MCF_GPIO_AD_ADDR23 0x80 131*4882a593Smuzhiyun #define MCF_GPIO_AD_ADDR22 0x40 132*4882a593Smuzhiyun #define MCF_GPIO_AD_ADDR21 0x20 133*4882a593Smuzhiyun #define MCF_GPIO_AD_DATAL 0x01 134*4882a593Smuzhiyun #define MCF_GPIO_AD_MASK 0xe1 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define MCF_GPIO_PAR_CS_PAR_CS2 0x04 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */ 139*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */ 140*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */ 141*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */ 142*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */ 143*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */ 144*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */ 145*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */ 146*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */ 147*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */ 148*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */ 149*4882a593Smuzhiyun #define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U0RTS 0x0001 152*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U0CTS 0x0002 153*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U0TXD 0x0004 154*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U0RXD 0x0008 155*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 156*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Bit definitions and macros for PAR_QSPI */ 159*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F 160*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0 161*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80 162*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00 163*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF 164*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20 165*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00 166*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7 167*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18 168*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10 169*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00 170*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB 171*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04 172*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00 173*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC 174*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03 175*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02 176*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* Bit definitions and macros for PAR_TIMER for QSPI */ 179*4882a593Smuzhiyun #define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF 180*4882a593Smuzhiyun #define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000 181*4882a593Smuzhiyun #define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F 182*4882a593Smuzhiyun #define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define MCF_SDRAMC_DCR 0x000040 187*4882a593Smuzhiyun #define MCF_SDRAMC_DACR0 0x000048 188*4882a593Smuzhiyun #define MCF_SDRAMC_DMR0 0x00004C 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) 191*4882a593Smuzhiyun #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) 192*4882a593Smuzhiyun #define MCF_SDRAMC_DCR_IS 0x0800 193*4882a593Smuzhiyun #define MCF_SDRAMC_DCR_COC 0x1000 194*4882a593Smuzhiyun #define MCF_SDRAMC_DCR_NAM 0x2000 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_IP 0x00000008 197*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4) 198*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_MRS 0x00000040 199*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8) 200*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12) 201*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_RE 0x00008000 202*4882a593Smuzhiyun #define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18) 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000 205*4882a593Smuzhiyun #define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000 206*4882a593Smuzhiyun #define MCF_SDRAMC_DMRn_V 0x00000001 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define MCFSIM_ICR1 0x000C41 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* Interrupt Controller (INTC) */ 211*4882a593Smuzhiyun #define INT0_LO_RSVD0 (0) 212*4882a593Smuzhiyun #define INT0_LO_EPORT1 (1) 213*4882a593Smuzhiyun #define INT0_LO_EPORT2 (2) 214*4882a593Smuzhiyun #define INT0_LO_EPORT3 (3) 215*4882a593Smuzhiyun #define INT0_LO_EPORT4 (4) 216*4882a593Smuzhiyun #define INT0_LO_EPORT5 (5) 217*4882a593Smuzhiyun #define INT0_LO_EPORT6 (6) 218*4882a593Smuzhiyun #define INT0_LO_EPORT7 (7) 219*4882a593Smuzhiyun #define INT0_LO_SCM (8) 220*4882a593Smuzhiyun #define INT0_LO_DMA0 (9) 221*4882a593Smuzhiyun #define INT0_LO_DMA1 (10) 222*4882a593Smuzhiyun #define INT0_LO_DMA2 (11) 223*4882a593Smuzhiyun #define INT0_LO_DMA3 (12) 224*4882a593Smuzhiyun #define INT0_LO_UART0 (13) 225*4882a593Smuzhiyun #define INT0_LO_UART1 (14) 226*4882a593Smuzhiyun #define INT0_LO_UART2 (15) 227*4882a593Smuzhiyun #define INT0_LO_RSVD1 (16) 228*4882a593Smuzhiyun #define INT0_LO_I2C (17) 229*4882a593Smuzhiyun #define INT0_LO_QSPI (18) 230*4882a593Smuzhiyun #define INT0_LO_DTMR0 (19) 231*4882a593Smuzhiyun #define INT0_LO_DTMR1 (20) 232*4882a593Smuzhiyun #define INT0_LO_DTMR2 (21) 233*4882a593Smuzhiyun #define INT0_LO_DTMR3 (22) 234*4882a593Smuzhiyun #define INT0_LO_FEC_TXF (23) 235*4882a593Smuzhiyun #define INT0_LO_FEC_TXB (24) 236*4882a593Smuzhiyun #define INT0_LO_FEC_UN (25) 237*4882a593Smuzhiyun #define INT0_LO_FEC_RL (26) 238*4882a593Smuzhiyun #define INT0_LO_FEC_RXF (27) 239*4882a593Smuzhiyun #define INT0_LO_FEC_RXB (28) 240*4882a593Smuzhiyun #define INT0_LO_FEC_MII (29) 241*4882a593Smuzhiyun #define INT0_LO_FEC_LC (30) 242*4882a593Smuzhiyun #define INT0_LO_FEC_HBERR (31) 243*4882a593Smuzhiyun #define INT0_HI_FEC_GRA (32) 244*4882a593Smuzhiyun #define INT0_HI_FEC_EBERR (33) 245*4882a593Smuzhiyun #define INT0_HI_FEC_BABT (34) 246*4882a593Smuzhiyun #define INT0_HI_FEC_BABR (35) 247*4882a593Smuzhiyun #define INT0_HI_PIT0 (36) 248*4882a593Smuzhiyun #define INT0_HI_PIT1 (37) 249*4882a593Smuzhiyun #define INT0_HI_PIT2 (38) 250*4882a593Smuzhiyun #define INT0_HI_PIT3 (39) 251*4882a593Smuzhiyun #define INT0_HI_RNG (40) 252*4882a593Smuzhiyun #define INT0_HI_SKHA (41) 253*4882a593Smuzhiyun #define INT0_HI_MDHA (42) 254*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF0I (43) 255*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF1I (44) 256*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF2I (45) 257*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF3I (46) 258*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF4I (47) 259*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF5I (48) 260*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF6I (49) 261*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF7I (50) 262*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF8I (51) 263*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF9I (52) 264*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF10I (53) 265*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF11I (54) 266*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF12I (55) 267*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF13I (56) 268*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF14I (57) 269*4882a593Smuzhiyun #define INT0_HI_CAN1_BUF15I (58) 270*4882a593Smuzhiyun #define INT0_HI_CAN1_ERRINT (59) 271*4882a593Smuzhiyun #define INT0_HI_CAN1_BOFFINT (60) 272*4882a593Smuzhiyun /* 60-63 Reserved */ 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #endif /* _MCF5271_H_ */ 275