| /OK3568_Linux_fs/kernel/arch/parisc/kernel/ |
| H A D | perf_images.h | 27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/video/ |
| H A D | cfb_console.c | 146 #define CURSOR_OFF console_cursor(0)
163 #define LINUX_LOGO_LUT_OFFSET 0x20
174 #define VIDEO_LOGO_WIDTH 0
175 #define VIDEO_LOGO_HEIGHT 0
206 #define SWAP16(x) ((((x) & 0x00ff) << 8) | \
209 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | \
210 (((x) & 0x0000ff00) << 8) | \
211 (((x) & 0x00ff0000) >> 8) | \
212 (((x) & 0xff000000) >> 24) \
214 #define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \
[all …]
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/ |
| H A D | g364fb.c | 34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
[all …]
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| H A D | pxa168fb.h | 6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
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| /OK3568_Linux_fs/kernel/drivers/message/fusion/lsi/ |
| H A D | mpi_fc.h | 75 #define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01)
82 U32 NodeNameLow; /* 0Ch */
97 U16 Reserved2; /* 0Ch */
98 U16 IOCStatus; /* 0Eh */
115 #define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80)
117 #define MPI_FC_DID_MASK (0x00FFFFFF)
118 #define MPI_FC_DID_SHIFT (0)
119 #define MPI_FC_RCTL_MASK (0xFF000000)
121 #define MPI_FC_SID_MASK (0x00FFFFFF)
122 #define MPI_FC_SID_SHIFT (0)
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| /OK3568_Linux_fs/kernel/arch/h8300/include/asm/ |
| H A D | flat.h | 15 * is is 0 (davidm@snapgear.com)
18 #define flat_get_relocate_addr(rel) (rel & ~0x00000001)
24 val &= 0x00ffffff; in flat_get_addr_from_rp()
26 return 0; in flat_get_addr_from_rp()
32 put_unaligned((addr & 0x00ffffff) | (*(char *)p << 24), p); in flat_put_addr_at_rp()
33 return 0; in flat_put_addr_at_rp()
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| /OK3568_Linux_fs/kernel/arch/arm/mach-rpc/include/mach/ |
| H A D | uncompress.h | 37 0x00000000,
38 0x000000cc,
39 0x0000cc00, /* Green */
40 0x0000cccc, /* Yellow */
41 0x00cc0000, /* Blue */
42 0x00cc00cc, /* Magenta */
43 0x00cccc00, /* Cyan */
44 0x00cccccc, /* White */
45 0x00000000,
46 0x000000ff,
[all …]
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| /OK3568_Linux_fs/kernel/sound/pci/pcxhr/ |
| H A D | pcxhr_core.h | 26 #define PCXHR_DSP_TIME_MASK 0x00ffffff
27 #define PCXHR_DSP_TIME_INVALID 0x10000000
47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/include/mach/ |
| H A D | hardware.h | 17 #define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
31 #define VIO_BASE 0xf8000000 /* virtual start of IO space */
33 #define PIO_START 0x80000000 /* physical start of IO space */
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
38 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/via/ |
| H A D | via_verifier.c | 49 no_check = 0,
119 {0xf2, check_for_header2_err},
120 {0xf0, check_for_header1_err},
121 {0xee, check_for_fire},
122 {0xcc, check_for_dummy},
123 {0xdd, check_for_dd},
124 {0x00, no_check},
125 {0x10, check_z_buffer_addr0},
126 {0x11, check_z_buffer_addr1},
127 {0x12, check_z_buffer_addr_mode},
[all …]
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| /OK3568_Linux_fs/kernel/sound/soc/sh/rcar/ |
| H A D | ctu.c | 24 * 0001: Connect input data of channel 0
32 * 1001: Connect calculated data by scale values of matrix row 0
42 * [Output4] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
43 * [Output5] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
44 * [Output6] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
45 * [Output7] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
53 * H'40_0000 1 0 H'C0_0000 1 0
56 * H'00_0000 0 Mute H'FF_FFFF 2.38 x 10^-7 -132
60 * 1ch -> 0ch
61 * 0ch -> 1ch
[all …]
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| /OK3568_Linux_fs/kernel/drivers/infiniband/sw/siw/ |
| H A D | siw_mem.c | 23 struct xa_limit limit = XA_LIMIT(1, 0x00ffffff); in siw_mem_add()
27 next &= 0x00ffffff; in siw_mem_add()
30 GFP_KERNEL) < 0) in siw_mem_add()
38 return 0; in siw_mem_add()
74 for (i = 0; num_pages; i++) { in siw_umem_release()
94 struct xa_limit limit = XA_LIMIT(1, 0x00ffffff); in siw_mr_add_mem()
101 mem->stag_valid = 0; in siw_mr_add_mem()
110 next &= 0x00ffffff; in siw_mr_add_mem()
113 GFP_KERNEL) < 0) { in siw_mr_add_mem()
123 return 0; in siw_mr_add_mem()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | regs.h | 5 #define NV04_PGRAPH_DEBUG_0 0x00400080
6 #define NV04_PGRAPH_DEBUG_1 0x00400084
7 #define NV04_PGRAPH_DEBUG_2 0x00400088
8 #define NV04_PGRAPH_DEBUG_3 0x0040008c
9 #define NV10_PGRAPH_DEBUG_4 0x00400090
10 #define NV03_PGRAPH_INTR 0x00400100
11 #define NV03_PGRAPH_NSTATUS 0x00400104
20 #define NV03_PGRAPH_NSOURCE 0x00400108
21 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0)
40 #define NV03_PGRAPH_INTR_EN 0x00400140
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7m/ |
| H A D | systick-timer.c | 31 #define SYSTICK_BASE 0xE000E010
40 #define TIMER_MAX_VAL 0x00FFFFFF
41 #define SYSTICK_CTRL_EN BIT(0)
42 /* Clock source: 0 = Ref clock, 1 = CPU clock */
46 #define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
63 /* Any write to current_val reg clears it to 0 */ in timer_init()
64 writel(0, &systick->current_val); in timer_init()
84 gd->arch.tbl = 0; in timer_init()
85 gd->arch.tbu = 0; in timer_init()
88 return 0; in timer_init()
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| /OK3568_Linux_fs/kernel/drivers/cpufreq/ |
| H A D | amd_freq_sensitivity.c | 25 #define MSR_AMD64_FREQ_SENSITIVITY_ACTUAL 0xc0010080
26 #define MSR_AMD64_FREQ_SENSITIVITY_REFERENCE 0xc0010081
58 actual.h &= 0x00ffffff; in amd_powersave_bias_target()
59 reference.h &= 0x00ffffff; in amd_powersave_bias_target()
70 /* divide by 0, so stay on current frequency as well */ in amd_powersave_bias_target()
71 if (d_reference == 0) { in amd_powersave_bias_target()
79 clamp(sensitivity, 0, POWERSAVE_BIAS_MAX); in amd_powersave_bias_target()
100 data->freq_prev = 0; in amd_powersave_bias_target()
137 return 0; in amd_freq_sensitivity_init()
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/ |
| H A D | nouveau_led.c | 44 div = nvif_rd32(device, 0x61c880) & 0x00ffffff; in nouveau_led_get_brightness()
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
47 if (div > 0) in nouveau_led_get_brightness()
50 return 0; in nouveau_led_get_brightness()
72 nvif_wr32(device, 0x61c880, div); in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()
86 return 0; in nouveau_led_init()
89 if (nvkm_gpio_find(gpio, 0, DCB_GPIO_LOGO_LED_PWM, 0xff, &logo_led)) in nouveau_led_init()
90 return 0; in nouveau_led_init()
109 return 0; in nouveau_led_init()
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| /OK3568_Linux_fs/kernel/include/soc/fsl/ |
| H A D | dpaa2-global.h | 47 #define DPAA2_DQ_STAT_FQEMPTY 0x80
49 #define DPAA2_DQ_STAT_HELDACTIVE 0x40
51 #define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
53 #define DPAA2_DQ_STAT_VALIDFRAME 0x10
55 #define DPAA2_DQ_STAT_ODPVALID 0x04
57 #define DPAA2_DQ_STAT_VOLATILE 0x02
59 #define DPAA2_DQ_STAT_EXPIRED 0x01
61 #define DQ_FQID_MASK 0x00FFFFFF
62 #define DQ_FRAME_COUNT_MASK 0x00FFFFFF
78 * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | sdram.h | 23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
30 u32 dram_timing4; /* 0x10 */
35 u32 dram_addrw; /* 0x2c */
36 u32 dram_if_width; /* 0x30 */
40 u32 sbe_count; /* 0x40 */
44 u32 drop_addr; /* 0x50 */
48 u32 ctrl_width; /* 0x60 */
52 u32 rfifo_cmap; /* 0x70 */
56 u32 fpgaport_rst; /* 0x80 */
60 u32 prot_rule_addr; /* 0x90 */
[all …]
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| /OK3568_Linux_fs/kernel/arch/powerpc/sysdev/xics/ |
| H A D | icp-opal.c | 26 opal_int_set_mfrr(hw_cpu, 0xff); in icp_opal_teardown_cpu()
33 * but want to leave our priority 0. in icp_opal_flush_ipi()
39 if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0) in icp_opal_flush_ipi()
56 if (rc < 0) in icp_opal_get_xirr()
57 return 0; in icp_opal_get_xirr()
68 vec = xirr & 0x00ffffff; in icp_opal_get_irq()
70 return 0; in icp_opal_get_irq()
82 if (opal_int_eoi(xirr) > 0) in icp_opal_get_irq()
85 return 0; in icp_opal_get_irq()
119 if (rc > 0) in icp_opal_eoi()
[all …]
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| /OK3568_Linux_fs/kernel/sound/drivers/vx/ |
| H A D | vx_cmd.h | 86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
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| /OK3568_Linux_fs/kernel/drivers/media/platform/ |
| H A D | imx-pxp.h | 13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/ |
| H A D | phy.h | 91 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
116 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
136 return 0; in rtw_check_supported_rfe()
162 #define MASKBYTE0 0xff
163 #define MASKBYTE1 0xff00
164 #define MASKBYTE2 0xff0000
165 #define MASKBYTE3 0xff000000
166 #define MASKHWORD 0xffff0000
167 #define MASKLWORD 0x0000ffff
168 #define MASKDWORD 0xffffffff
[all …]
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| /OK3568_Linux_fs/kernel/tools/include/uapi/linux/ |
| H A D | lirc.h | 13 #define PULSE_BIT 0x01000000
14 #define PULSE_MASK 0x00FFFFFF
16 #define LIRC_MODE2_SPACE 0x00000000
17 #define LIRC_MODE2_PULSE 0x01000000
18 #define LIRC_MODE2_FREQUENCY 0x02000000
19 #define LIRC_MODE2_TIMEOUT 0x03000000
21 #define LIRC_VALUE_MASK 0x00FFFFFF
22 #define LIRC_MODE2_MASK 0xFF000000
47 #define LIRC_MODE_RAW 0x00000001
48 #define LIRC_MODE_PULSE 0x00000002
[all …]
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| /OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/ |
| H A D | lirc.h | 13 #define PULSE_BIT 0x01000000
14 #define PULSE_MASK 0x00FFFFFF
16 #define LIRC_MODE2_SPACE 0x00000000
17 #define LIRC_MODE2_PULSE 0x01000000
18 #define LIRC_MODE2_FREQUENCY 0x02000000
19 #define LIRC_MODE2_TIMEOUT 0x03000000
21 #define LIRC_VALUE_MASK 0x00FFFFFF
22 #define LIRC_MODE2_MASK 0xFF000000
47 #define LIRC_MODE_RAW 0x00000001
48 #define LIRC_MODE_PULSE 0x00000002
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