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/rk3399_ARM-atf/docs/threat_model/firmware_threat_model/
H A Dthreat_model_el3_spm.rst7 This document provides a threat model for the TF-A :ref:`EL3 Secure Partition Manager`
9 `Arm Firmware Framework for Arm A-profile`_ specification.
16 The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
21 - The TF-A implementation for the EL3 SPMC
22 - The implementation complies with the FF-A v1.1 specification.
23 - Secure partition is statically provisioned at boot time.
24 - Focus on the run-time part of the life-cycle (no specific emphasis on boot
26 - Not covering advanced or invasive physical attacks such as decapsulation,
31 Figure 1 shows a high-level data flow diagram for the SPM split into an SPMD
32 and SPMC component at EL3. The SPMD mostly acts as a relayer/pass-through between
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H A Dthreat_model.rst8 This document provides a generic threat model for TF-A firmware.
17 Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1),
22 TF-A can be configured in various ways. In this threat model we consider
26 - All TF-A images are run from either ROM or on-chip trusted SRAM. This means
27 TF-A is not vulnerable to an attacker that can probe or tamper with off-chip
30 - Trusted boot is enabled. This means an attacker can't boot arbitrary images
33 - There is no Secure-EL2. We don't consider threats that may come with
34 Secure-EL2 software.
36 - There are no Root and Realm worlds. These are introduced by :ref:`Realm
39 The :ref:`Threat Model for TF-A with Arm CCA support` covers these types of
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/rk3399_ARM-atf/docs/
H A Darchitecture_features.rst8 code and determine whether TF-A support them. However, for features that are transparent to EL3, it
10 in TF-A.
13 architectural features within TF-A.
22 * ``OK``: TF-A has explicit support;
29 ---------------
31 +-------------------------+--------+
35 +-------------------------+--------+
37 +-------------------------+--------+
39 +-------------------------+--------+
41 +-------------------------+--------+
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/rk3399_ARM-atf/lib/cpus/aarch32/
H A Dcortex_a72.S2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
13 /* ---------------------------------------------
15 * ---------------------------------------------
27 /* ---------------------------------------------
28 * Disable the load-store hardware prefetcher.
29 * ---------------------------------------------
40 /* ---------------------------------------------
41 * Disable intra-cluster coherency
42 * Clobbers: r0-r1
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H A Dcortex_a32.S2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
14 /* ---------------------------------------------
15 * Disable intra-cluster coherency
16 * Clobbers: r0-r1
17 * ---------------------------------------------
28 /* -------------------------------------------------
29 * The CPU Ops reset function for Cortex-A32.
30 * Clobbers: r0-r1
31 * -------------------------------------------------
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/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-n1sdp.rst1 Runtime Instrumentation Testing - N1SDP
5 contains an SoC consisting of two dual-core Arm N1 clusters.
9 - `TF-A v2.14-rc0`_
10 - `TFTF v2.14-rc0`_
15 `tf-psci-lava-instr/n1sdp-runtime-instrumentation,n1sdp-runtime-instrumentation:n1sdp-fip.tftf-firm…
19 -------
25 +---------+------+----------------+-----------------+----------------+
27 +---------+------+----------------+-----------------+----------------+
28 | 0 | 0 | 3380.0(+1.81%) | 12480.0(-7.00%) | 340.0(+21.43%) |
29 +---------+------+----------------+-----------------+----------------+
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H A Dpsci-performance-juno.rst5 operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
6 implementation, using the in-built Performance Measurement Framework (PMF) and
10 ------
12 We used the `Juno R1 platform`_ for these tests, which has 4 x Cortex-A53 and 2
13 x Cortex-A57 clusters running at the following frequencies:
15 +-----------------+--------------------+
18 | Cortex-A57 | 900 (nominal) |
19 +-----------------+--------------------+
20 | Cortex-A53 | 650 (underdrive) |
21 +-----------------+--------------------+
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/rk3399_ARM-atf/docs/plat/
H A Dxilinx-versal-net.rst4 Trusted Firmware-A implements the EL3 firmware layer for Xilinx Versal NET.
5 The platform only uses the runtime part of TF-A as Xilinx Versal NET already
8 BL31 is TF-A.
10 BL33 is the non-secure world software (U-Boot, Linux etc).
14 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net bl31
19 make CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SPD=tspd RESET_TO_BL31=1 bl31 bl32
22 To build TF-A for JTAG DCC console:
24 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
27 To build TF-A with SDEI_SUPPORT:
29 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SDEI_SUPPORT=1 bl31
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H A Dxilinx-versal.rst4 Trusted Firmware-A implements the EL3 firmware layer for Xilinx Versal.
5 The platform only uses the runtime part of TF-A as Xilinx Versal already has a
8 BL31 is TF-A.
10 BL33 is the non-secure world software (U-Boot, Linux etc).
14 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31
19 make CROSS_COMPILE=aarch64-none-elf- PLAT=versal SPD=tspd RESET_TO_BL31=1 bl31 bl32
22 To build TF-A for JTAG DCC console
24 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
27 To build TF-A with Errata management interface
29 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 ERRATA_ABI_SUPPORT=1
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/rk3399_ARM-atf/plat/common/aarch64/
H A Dplatform_helpers.S2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
26 /* -----------------------------------------------------
29 * -----------------------------------------------------
35 /* -----------------------------------------------------
37 * each platform. This function should preserve x19 - x29.
38 * -----------------------------------------------------
44 /* -----------------------------------------------------
47 * registers x0 - x17.
48 * -----------------------------------------------------
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/rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/
H A Dtegra_helpers.S2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
5 * SPDX-License-Identifier: BSD-3-Clause
53 /* ---------------------
55 * ---------------------
59 /* ------------------------------------------------
62 * ------------------------------------------------
71 /* ---------------------------
73 * ---------------------------
89 /* -------------------------------------------------------
90 * Enable L2 and CPU ECTLR RW access from non-secure world
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/rk3399_ARM-atf/plat/arm/board/juno/aarch32/
H A Djuno_helpers.S4 * SPDX-License-Identifier: BSD-3-Clause
24 /* --------------------------------------------------------------------
28 * --------------------------------------------------------------------
35 /* --------------------------------------------------------------------
39 * - Quad core Cortex-A53 processor cluster;
40 * - Dual core Cortex-A57 processor cluster.
43 * - Implement workaround for defect id 831273 by enabling an event
45 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
46 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
47 * --------------------------------------------------------------------
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/rk3399_ARM-atf/plat/common/aarch32/
H A Dplatform_helpers.S2 * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
19 /* -----------------------------------------------------
22 * -----------------------------------------------------
28 /* -----------------------------------------------------
31 * -----------------------------------------------------
37 /* -----------------------------------------------------
40 * -----------------------------------------------------
46 /* -----------------------------------------------------
49 * -----------------------------------------------------
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/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-a8k-addr-map.rst6 …+-------------------------------------------------------------------------------------------------…
7 …| +-------------+ +--------------+…
8 …| | Memory +----- DRAM CS |…
9 …|+------------+ +-----------+ +-----------+ | Controller | +--------------+…
10 …|| AP DMA | | | | | +-------------+ …
11 …|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ …
12 …|| MCI-0/1 | | | | | | Memory | …
13 …|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+…
14 …| | | | | +----- Translaton | |AP |…
15 …| | | | | | +-------------+ |Configuration|…
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/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_pas_def3.h2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
27 * ---------------------------------------------------------------------
30 * ---------------------------------------------------------------------
33 * ---------------------------------------------------------------------
36 * ---------------------------------------------------------------------
39 * ---------------------------------------------------------------------
42 * ---------------------------------------------------------------------
45 * ---------------------------------------------------------------------
48 * ---------------------------------------------------------------------
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/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dcortex_a72.S2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
20 /* ---------------------------------------------
22 * ---------------------------------------------
35 /* ---------------------------------------------
36 * Disable the load-store hardware prefetcher.
37 * ---------------------------------------------
46 /* ---------------------------------------------
47 * Disable intra-cluster coherency
48 * ---------------------------------------------
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H A Dcortex_a35.S2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
15 /* ---------------------------------------------
16 * Disable intra-cluster coherency
17 * ---------------------------------------------
32 /* -------------------------------------------------
33 * The CPU Ops reset function for Cortex-A35.
34 * -------------------------------------------------
37 /* ---------------------------------------------
39 * ---------------------------------------------
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/rk3399_ARM-atf/bl1/aarch64/
H A Dbl1_exceptions.S2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
13 /* -----------------------------------------------------------------------------
15 * -----------------------------------------------------------------------------
21 /* -----------------------------------------------------
22 * Current EL with SP0 : 0x0 - 0x200
23 * -----------------------------------------------------
49 /* -----------------------------------------------------
50 * Current EL with SPx: 0x200 - 0x400
51 * -----------------------------------------------------
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/rk3399_ARM-atf/bl32/tsp/aarch64/
H A Dtsp_entrypoint.S2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
26 /* ---------------------------------------------
27 * Populate the params in x0-x7 from the pointer
29 * ---------------------------------------------
42 stp \reg1, \reg2, [sp, #-0x10]!
43 stp x30, x18, [sp, #-0x10]!
54 /*---------------------------------------------
55 * Save arguments x0 - x3 from BL1 for future
57 * ---------------------------------------------
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/rk3399_ARM-atf/docs/about/
H A Drelease-information.rst5 -----------------------
9 non-essential changes) up to 4 weeks prior to the target release date. The release
21 |<----------6 months---------->|
22 |<---4 weeks--->| |<---4 weeks--->|
23 +-----------------------------------------------------------> time
30 TF-A version is given in Makefile, through several macros:
32 - VERSION_MAJOR
33 - VERSION_MINOR
34 - VERSION_PATCH
36 For example, TF-A v2.10 has VERSION_MAJOR=2, VERSION_MINOR=10 and VERSION_PATCH=0.
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/rk3399_ARM-atf/plat/rockchip/common/aarch32/
H A Dplat_helpers.S2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
49 /* --------------------------------------------------------------------
56 * --------------------------------------------------------------------
78 /* --------------------------------------------------------------------
83 * --------------------------------------------------------------------
90 /* --------------------------------------------------------------------
93 * --------------------------------------------------------------------
96 push { r4 - r7, lr }
107 /* --------------------------------------------------------------------
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/rk3399_ARM-atf/plat/marvell/armada/common/aarch64/
H A Dmarvell_helpers.S5 * SPDX-License-Identifier: BSD-3-Clause
33 /* -----------------------------------------------------
37 * -----------------------------------------------------
44 /* -----------------------------------------------------
49 * -----------------------------------------------------
58 /* ---------------------------------------------
63 * ---------------------------------------------
84 /* ---------------------------------------------
89 * ---------------------------------------------
101 /* ---------------------------------------------
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/rk3399_ARM-atf/plat/brcm/board/stingray/aarch64/
H A Dplat_helpers.S2 * Copyright (c) 2015-2020, Broadcom
4 * SPDX-License-Identifier: BSD-3-Clause
32 /* ------------------------------------------------------------
41 * --------------------------------------------------------------------
72 /* --------------------------------------------------------------------
76 * docs/firmware-design.md.
78 * --------------------------------------------------------------------
87 /* -----------------------------------------------------
96 * -----------------------------------------------------
99 /*TBD-STINGRAY*/
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/rk3399_ARM-atf/bl2/aarch32/
H A Dbl2_entrypoint.S2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
27 /*---------------------------------------------
28 * Save arguments x0 - x3 from BL1 for future
30 * ---------------------------------------------
37 /* ---------------------------------------------
39 * ---------------------------------------------
45 /* --------------------------------------------------------
46 * Enable the instruction cache - disable speculative loads
47 * --------------------------------------------------------
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/rk3399_ARM-atf/bl2u/aarch32/
H A Dbl2u_entrypoint.S2 * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
27 /*---------------------------------------------
31 * ---------------------------------------------
36 /* ---------------------------------------------
38 * ---------------------------------------------
44 /* --------------------------------------------------------
45 * Enable the instruction cache - disable speculative loads
46 * --------------------------------------------------------
54 /* ---------------------------------------------
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