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2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
26 /* ---------------------------------------------
27 * Populate the params in x0-x7 from the pointer
29 * ---------------------------------------------
42 stp \reg1, \reg2, [sp, #-0x10]!
43 stp x30, x18, [sp, #-0x10]!
54 /*---------------------------------------------
55 * Save arguments x0 - x3 from BL1 for future
57 * ---------------------------------------------
66 * ------------------------------------------------------------
72 * ------------------------------------------------------------
77 mov_imm x1, (BL32_LIMIT - BL32_BASE)
82 /* ---------------------------------------------
84 * ---------------------------------------------
90 /* ---------------------------------------------
93 * ---------------------------------------------
97 /* ---------------------------------------------
101 * ---------------------------------------------
114 /* ---------------------------------------------
125 * ---------------------------------------------
144 /* ---------------------------------------------
146 * - the .bss section;
147 * - the coherent memory section.
148 * ---------------------------------------------
166 /* --------------------------------------------
168 * as Normal-IS-WBWA when the MMU is enabled.
172 * --------------------------------------------
176 /* ---------------------------------------------
179 * ---------------------------------------------
185 /*---------------------------------------------
186 * Save arguments x0 - x3 from prio stage for
188 * ---------------------------------------------
195 /* ---------------------------------------------
197 * ---------------------------------------------
202 /* ---------------------------------------------
205 * ---------------------------------------------
210 /* ---------------------------------------------
212 * ---------------------------------------------
216 /* ---------------------------------------------
218 * ---------------------------------------------
229 /* -------------------------------------------
232 * -------------------------------------------
246 /*---------------------------------------------
252 * re-initialise its state so nothing is done
254 * ---------------------------------------------
261 /*---------------------------------------------
266 * ---------------------------------------------
273 /*---------------------------------------------
278 * ---------------------------------------------
285 /*---------------------------------------------
294 * ---------------------------------------------
297 /* ---------------------------------------------
299 * ---------------------------------------------
308 /* ---------------------------------------------
311 * ---------------------------------------------
319 /* --------------------------------------------
321 * marked as Normal-IS-WBWA when the MMU is
323 * --------------------------------------------
327 /* --------------------------------------------
328 * Enable MMU and D-caches together.
329 * --------------------------------------------
335 /* ---------------------------------------------
338 * ---------------------------------------------
343 /* ---------------------------------------------
346 * ---------------------------------------------
356 /*---------------------------------------------
363 * ---------------------------------------------
370 /*-------------------------------------------------
372 * control for `synchronously` handling a S-EL1
381 * the ELR_EL3 from the non-secure state.
387 * 4. TSP can use 'x0-x18' to enable its C
391 * ------------------------------------------------
399 /*-------------------------------------------------
401 * an exception return from S-EL1 e.g. context
403 * Update statistics and handle the S-EL1
416 * ------------------------------------------------
421 /* Check if the S-EL1 interrupt has been handled */
425 /* Check if the S-EL1 interrupt has been preempted */
439 /*---------------------------------------------
447 * ---------------------------------------------
457 /*---------------------------------------------
460 * ---------------------------------------------
470 /*---------------------------------------------
475 * ---------------------------------------------
487 /*---------------------------------------------------------------------
488 * This entrypoint is used by the TSPD to abort a pre-empted Yielding
489 * SMC. It could be on behalf of non-secure world or because a CPU
491 * --------------------------------------------------------------------
500 /* Reset the stack used by the pre-empted SMC */