| #
fe524532 |
| 27-May-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge "docs(versal-net): update documentation for SDEI" into integration
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| #
da2c9e58 |
| 23-Apr-2025 |
Amit Nagal <amit.nagal@amd.com> |
docs(versal-net): update documentation for SDEI
Update documentation to specify tf-a build option with SDEI support.
Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <
docs(versal-net): update documentation for SDEI
Update documentation to specify tf-a build option with SDEI support.
Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
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| #
778e2452 |
| 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes:
docs(xilinx): update SMC documentation in TF-A
feat(xilinx): add feature check function for TF-A specific
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes:
docs(xilinx): update SMC documentation in TF-A
feat(xilinx): add feature check function for TF-A specific APIs
feat(xilinx): update SiP SVC version number
feat(xilinx): update TF-A to passthrough all PLM commands
fix(xilinx): fix logic to read ipi response
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| #
e1890297 |
| 15-Jul-2024 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
docs(xilinx): update SMC documentation in TF-A
Updated documentation for new SMC SiP calling conventions for Platform
Management specific SiP Service calls.
Signed-off-by: Jay Buddhabhatti <jay.bud
docs(xilinx): update SMC documentation in TF-A
Updated documentation for new SMC SiP calling conventions for Platform
Management specific SiP Service calls.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Iee09d3d843c6bb3f82aad6df703542ba1eb63c6c
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| #
eff1da2a |
| 08-Mar-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_smc_doc" into integration
* changes:
docs(versal-net): update SMC convention
docs(versal): update SMC convention
docs(zynqmp): update SMC convention
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| #
59621c71 |
| 08-Feb-2024 |
Prasad Kummari <prasad.kummari@amd.com> |
docs(versal-net): update SMC convention
Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id:
docs(versal-net): update SMC convention
Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4bd71dd8e16c7adf3f9c5cb202f36aa2e275d03a
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| #
1064bc6c |
| 22-Jan-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add new state to identify cpu power down
feat(xilinx): request cpu power down from reset
feat(xilinx): power down all cores on receiving cpu pwrdwn req
feat(xilinx): add handler for power down req sgi irq
feat(xilinx): add wrapper to handle cpu power down req
fix(versal-net): use arm common GIC handlers
fix(xilinx): rename macros to align with ARM
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| #
ade92a64 |
| 25-Apr-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): add handler for power down req sgi irq
On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ
feat(xilinx): add handler for power down req sgi irq
On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.
By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.
e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
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| #
dd532b9e |
| 03-Nov-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_tsp_feat" into integration
* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
Merge changes from topic "xlnx_tsp_feat" into integration
* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name
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| #
41b5a23c |
| 29-Oct-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
docs(versal-net): add TSP build documentation
Add information about Versal NET platform for TSP and provide
the build commands.
Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: P
docs(versal-net): add TSP build documentation
Add information about Versal NET platform for TSP and provide
the build commands.
Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| #
1548e0e7 |
| 02-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_feat_chores" into integration
* changes:
chore(xilinx): update print information
feat(versal-net): add jtag dcc support
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| #
30e8bc36 |
| 18-Jan-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
f47d38ba |
| 21-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
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| #
4efdc488 |
| 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Idcbb893c6b9e46512308c53ba2a0bee48a022b0a
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