| 7bcaf050 | 27-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
UPSTREAM: usb: host: dwc2: add trace to have clean usb start
Solve issue for the display of "usb start" command on stm32mp1
because one carriage return is missing in DWC2 probe.
Before the patch:
UPSTREAM: usb: host: dwc2: add trace to have clean usb start
Solve issue for the display of "usb start" command on stm32mp1
because one carriage return is missing in DWC2 probe.
Before the patch:
STM32MP> usb start
starting USB...
Bus usb-otg@49000000: Bus usbh-ehci@5800d000: USB EHCI 1.00
after the patch:
STM32MP> usb start
starting USB...
Bus usb-otg@49000000: USB DWC2
Bus usbh-ehci@5800d000: USB EHCI 1.00
Change-Id: I821e082679cacfc53d49b95882982983810c42de
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 245847f06570a74ecff59809a2befc1dce7a354e)
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| 3fd577de | 27-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
UPSTREAM: usb: host: dwc2: force reset assert
Assert reset before deassert in dwc2_reset;
this patch solve issues when the DWC2 registers are already
initialized with value incompatible with host mo
UPSTREAM: usb: host: dwc2: force reset assert
Assert reset before deassert in dwc2_reset;
this patch solve issues when the DWC2 registers are already
initialized with value incompatible with host mode.
Force a hardware reset of the IP reset all the DWC2 registers at
default value, the host driver start with a clean state
(Core Soft reset doen in dwc_otg_core_reset is not enought
to reset all register).
The error can occurs in U-Boot when DWC2 device gadget driver
force device mode (called by ums or dfu command, before to execute
the usb start command).
Change-Id: Iaf1494bc58c6b2d6c0323e0eb4bc6d18f8edf557
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 66004381661386d14183a436c5e0caeb19f4b415)
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| 1966f56e | 27-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
UPSTREAM: usb: host: dwc2: add clk support
Add support for clock with driver model.
This patch don't added dependency because when CONFIG_CLK
is not activated the clk function are stubbed.
Change-
UPSTREAM: usb: host: dwc2: add clk support
Add support for clock with driver model.
This patch don't added dependency because when CONFIG_CLK
is not activated the clk function are stubbed.
Change-Id: I06a8762639274a0d79ab737898b504b7989eb5f3
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 0bc632c9b189f0350b2ef81d6583704bd10cfdc9)
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| 1422d140 | 29-Oct-2023 |
Hector Martin <marcan@marcan.st> |
BACKPORT: usb: xhci: Guard all calls to xhci_wait_for_event
xhci_wait_for_event returns NULL on timeout, so the caller always has to
check for that. This addresses immediate explosions in this part
BACKPORT: usb: xhci: Guard all calls to xhci_wait_for_event
xhci_wait_for_event returns NULL on timeout, so the caller always has to
check for that. This addresses immediate explosions in this part
of the code when timeouts happen, but not the root cause for the
timeout.
Change-Id: Ib899b615349ed5d1d00885b6508c765b6e773d6a
Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 8d1e03f984c7467d7c8883f15dea14b2f8b4c0e2)
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| d4f95349 | 04-Mar-2020 |
Kever Yang <kever.yang@rock-chips.com> |
FROMLIST: usb: ehci-msm: Use dev interface to get device address
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.
Change-Id: I373931c2bfbe4ad4422ee974560e690c775
FROMLIST: usb: ehci-msm: Use dev interface to get device address
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.
Change-Id: I373931c2bfbe4ad4422ee974560e690c775d670d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(am from http://patchwork.ozlabs.org/patch/1248684/)
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| db0e15c2 | 06-Oct-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
UPSTREAM: usb: ehci-hcd: Keep async schedule running
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disablin
UPSTREAM: usb: ehci-hcd: Keep async schedule running
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.
This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.
However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.
Change-Id: I33a5eccac2579be09c5f1c9385ae245e680bc125
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 02b0e1a36c5bc20174299312556ec4e266872bd6)
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| 48afbe4f | 24-Oct-2019 |
Ye Li <ye.li@nxp.com> |
UPSTREAM: ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar a
UPSTREAM: ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
Change-Id: Iccbcd113f87e5382eab12558abbb7ff596e4688d
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 235f5e158e336371759f98ffbf265fe078cda251)
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| a9aeb7ee | 10-Oct-2019 |
Igor Opaniuk <igor.opaniuk@toradex.com> |
UPSTREAM: usb: ehci-mx6: Fix bus enumeration for iMX7 SoCs
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed nex
UPSTREAM: usb: ehci-mx6: Fix bus enumeration for iMX7 SoCs
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.
Example of USB nodes for iMX7S/D:
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
^^^^^^^^^^
....
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b20000 0x200>;
^^^^^^^^^^
....
usbh: usb@30b30000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
^^^^^^^^^^
....
Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Change-Id: I2c458dfa9e590ba054f63bb1e7ce1fad525eb56c
Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1198a104d37b10064cd90f36d472787d549eda02)
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| 541cc577 | 28-Aug-2019 |
Kever Yang <kever.yang@rock-chips.com> |
UPSTREAM: usb: ohci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other mo
UPSTREAM: usb: ohci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Change-Id: I6a87df188857287f860d4c7d9e66694e561da2dd
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
(cherry picked from commit 6578db896113816e5b61d1914169fad5f06d7903)
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| 5311a685 | 28-Aug-2019 |
Kever Yang <kever.yang@rock-chips.com> |
UPSTREAM: usb: ehci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other mo
UPSTREAM: usb: ehci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Change-Id: I4686a87238ff5dff7a8f1c2e4df03cce4581aa0b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
(cherry picked from commit 54a0c7b2e7a233aa3975771592afb8e0e2f6acc0)
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| 85bca00e | 18-Aug-2019 |
Michal Suchanek <msuchanek@suse.de> |
UPSTREAM: dwc2: use the nonblock argument in submit_int_msg
An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable key
UPSTREAM: dwc2: use the nonblock argument in submit_int_msg
An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable keyboard
by pressing a key while USB devices are probed. Without a keypress no
state is reported and the probe times out. We don't want to wait for a
keypress or timeout while polling for keypresses so implement an int_msg
nonblock variant that exits early on error.
Change-Id: I6d89952ca5c00a1b076ae3fe9d9632ebdc6af843
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 9dcab2c4d2cb50ab1864c818b82a72393c160236)
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| 5e8c228d | 09-Sep-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
UPSTREAM: usb: xhci-dwc3: Add support for dis_u2_susphy_quirk
This quirk is necessary for the Amlogic GXL SoCs otherwise the
Port 2 PHY doesn't get out of suspend and U-Boot resets the board after:
UPSTREAM: usb: xhci-dwc3: Add support for dis_u2_susphy_quirk
This quirk is necessary for the Amlogic GXL SoCs otherwise the
Port 2 PHY doesn't get out of suspend and U-Boot resets the board after:
XHCI timeout on event type 33... cannot recover.
BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()!
BUG!
This quirk is also handled in the dwc3 core code, but until the
xhci-dwc3 driver uses the dwc3 core, the quirk must be handled here
to fix USB support on the Amlogic libretech-cc and libretech-ac board
when a device is only plugged in the OTG port.
Change-Id: Iba72fb52411856785b6bd6ed829e1585ba00bebe
Cc: Yuri Frolov <crashing.kernel@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Fixes: dc9cdf859e ("usb: dwc3: Add DWC3 controller driver support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b35b8076828d1059c1fcc648ed8c8210ebe6a3dd)
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