1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 PX30_CPUCLK_RATE(408000000, 1, 1), 90 }; 91 92 static u8 pll_mode_shift[PLL_COUNT] = { 93 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 94 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 95 }; 96 static u32 pll_mode_mask[PLL_COUNT] = { 97 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 98 NPLL_MODE_MASK, GPLL_MODE_MASK 99 }; 100 101 static struct pll_rate_table auto_table; 102 103 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 104 enum px30_pll_id pll_id); 105 106 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 107 { 108 struct pll_rate_table *rate = &auto_table; 109 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 110 u32 postdiv1, postdiv2 = 1; 111 u32 fref_khz; 112 u32 diff_khz, best_diff_khz; 113 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 114 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 115 u32 vco_khz; 116 u32 rate_khz = drate / KHz; 117 118 if (!drate) { 119 printf("%s: the frequency can't be 0 Hz\n", __func__); 120 return NULL; 121 } 122 123 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 124 if (postdiv1 > max_postdiv1) { 125 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 126 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 127 } 128 129 vco_khz = rate_khz * postdiv1 * postdiv2; 130 131 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 132 postdiv2 > max_postdiv2) { 133 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 134 __func__, rate_khz); 135 return NULL; 136 } 137 138 rate->postdiv1 = postdiv1; 139 rate->postdiv2 = postdiv2; 140 141 best_diff_khz = vco_khz; 142 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 143 fref_khz = ref_khz / refdiv; 144 145 fbdiv = vco_khz / fref_khz; 146 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 147 continue; 148 diff_khz = vco_khz - fbdiv * fref_khz; 149 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 150 fbdiv++; 151 diff_khz = fref_khz - diff_khz; 152 } 153 154 if (diff_khz >= best_diff_khz) 155 continue; 156 157 best_diff_khz = diff_khz; 158 rate->refdiv = refdiv; 159 rate->fbdiv = fbdiv; 160 } 161 162 if (best_diff_khz > 4 * (MHz / KHz)) { 163 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 164 __func__, rate_khz, 165 best_diff_khz * KHz); 166 return NULL; 167 } 168 169 return rate; 170 } 171 172 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 173 { 174 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 175 int i; 176 177 for (i = 0; i < rate_count; i++) { 178 if (rate == px30_pll_rates[i].rate) 179 return &px30_pll_rates[i]; 180 } 181 182 return pll_clk_set_by_auto(rate); 183 } 184 185 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 186 { 187 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 188 int i; 189 190 for (i = 0; i < rate_count; i++) { 191 if (rate == px30_cpu_rates[i].rate) 192 return &px30_cpu_rates[i]; 193 } 194 195 return NULL; 196 } 197 198 /* 199 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 200 * Formulas also embedded within the Fractional PLL Verilog model: 201 * If DSMPD = 1 (DSM is disabled, "integer mode") 202 * FOUTVCO = FREF / REFDIV * FBDIV 203 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 204 * Where: 205 * FOUTVCO = Fractional PLL non-divided output frequency 206 * FOUTPOSTDIV = Fractional PLL divided output frequency 207 * (output of second post divider) 208 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 209 * REFDIV = Fractional PLL input reference clock divider 210 * FBDIV = Integer value programmed into feedback divide 211 * 212 */ 213 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 214 enum px30_pll_id pll_id, 215 unsigned long drate) 216 { 217 const struct pll_rate_table *rate; 218 uint vco_hz, output_hz; 219 220 rate = get_pll_settings(drate); 221 if (!rate) { 222 printf("%s unsupport rate\n", __func__); 223 return -EINVAL; 224 } 225 226 /* All PLLs have same VCO and output frequency range restrictions. */ 227 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 228 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 229 230 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 231 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 232 rate->postdiv2, vco_hz, output_hz); 233 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 234 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 235 236 /* 237 * When power on or changing PLL setting, 238 * we must force PLL into slow mode to ensure output stable clock. 239 */ 240 rk_clrsetreg(mode, pll_mode_mask[pll_id], 241 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 242 243 /* use integer mode */ 244 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 245 /* Power down */ 246 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 247 248 rk_clrsetreg(&pll->con0, 249 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 250 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 251 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 252 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 253 rate->refdiv << PLL_REFDIV_SHIFT)); 254 255 /* Power Up */ 256 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 257 258 /* waiting for pll lock */ 259 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 260 udelay(1); 261 262 rk_clrsetreg(mode, pll_mode_mask[pll_id], 263 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 264 265 return 0; 266 } 267 268 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 269 enum px30_pll_id pll_id) 270 { 271 u32 refdiv, fbdiv, postdiv1, postdiv2; 272 u32 con, shift, mask; 273 274 con = readl(mode); 275 shift = pll_mode_shift[pll_id]; 276 mask = pll_mode_mask[pll_id]; 277 278 switch ((con & mask) >> shift) { 279 case PLLMUX_FROM_XIN24M: 280 return OSC_HZ; 281 case PLLMUX_FROM_PLL: 282 /* normal mode */ 283 con = readl(&pll->con0); 284 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 285 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 286 con = readl(&pll->con1); 287 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 288 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 289 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 290 case PLLMUX_FROM_RTC32K: 291 default: 292 return 32768; 293 } 294 } 295 296 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 297 { 298 struct px30_cru *cru = priv->cru; 299 u32 div, con; 300 301 switch (clk_id) { 302 case SCLK_I2C0: 303 con = readl(&cru->clksel_con[49]); 304 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 305 break; 306 case SCLK_I2C1: 307 con = readl(&cru->clksel_con[49]); 308 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 309 break; 310 case SCLK_I2C2: 311 con = readl(&cru->clksel_con[50]); 312 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 313 break; 314 case SCLK_I2C3: 315 con = readl(&cru->clksel_con[50]); 316 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 317 break; 318 default: 319 printf("do not support this i2c bus\n"); 320 return -EINVAL; 321 } 322 323 return DIV_TO_RATE(priv->gpll_hz, div); 324 } 325 326 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 327 { 328 struct px30_cru *cru = priv->cru; 329 int src_clk_div; 330 331 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 332 assert(src_clk_div - 1 <= 127); 333 334 switch (clk_id) { 335 case SCLK_I2C0: 336 rk_clrsetreg(&cru->clksel_con[49], 337 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 338 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 339 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 340 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 341 break; 342 case SCLK_I2C1: 343 rk_clrsetreg(&cru->clksel_con[49], 344 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 345 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 346 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 347 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 348 break; 349 case SCLK_I2C2: 350 rk_clrsetreg(&cru->clksel_con[50], 351 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 352 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 353 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 354 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 355 break; 356 case SCLK_I2C3: 357 rk_clrsetreg(&cru->clksel_con[50], 358 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 359 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 360 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 361 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 362 break; 363 default: 364 printf("do not support this i2c bus\n"); 365 return -EINVAL; 366 } 367 368 return px30_i2c_get_clk(priv, clk_id); 369 } 370 371 /* 372 * calculate best rational approximation for a given fraction 373 * taking into account restricted register size, e.g. to find 374 * appropriate values for a pll with 5 bit denominator and 375 * 8 bit numerator register fields, trying to set up with a 376 * frequency ratio of 3.1415, one would say: 377 * 378 * rational_best_approximation(31415, 10000, 379 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 380 * 381 * you may look at given_numerator as a fixed point number, 382 * with the fractional part size described in given_denominator. 383 * 384 * for theoretical background, see: 385 * http://en.wikipedia.org/wiki/Continued_fraction 386 */ 387 static void rational_best_approximation( 388 unsigned long given_numerator, unsigned long given_denominator, 389 unsigned long max_numerator, unsigned long max_denominator, 390 unsigned long *best_numerator, unsigned long *best_denominator) 391 { 392 unsigned long n, d, n0, d0, n1, d1; 393 394 n = given_numerator; 395 d = given_denominator; 396 n0 = 0; 397 d1 = 0; 398 n1 = 1; 399 d0 = 1; 400 for (;;) { 401 unsigned long t, a; 402 403 if (n1 > max_numerator || d1 > max_denominator) { 404 n1 = n0; 405 d1 = d0; 406 break; 407 } 408 if (d == 0) 409 break; 410 t = d; 411 a = n / d; 412 d = n % d; 413 n = t; 414 t = n0 + a * n1; 415 n0 = n1; 416 n1 = t; 417 t = d0 + a * d1; 418 d0 = d1; 419 d1 = t; 420 } 421 *best_numerator = n1; 422 *best_denominator = d1; 423 } 424 425 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 426 { 427 u32 con, fracdiv, gate; 428 u32 clk_src = GPLL_HZ / 2; 429 unsigned long m, n; 430 struct px30_cru *cru = priv->cru; 431 432 switch (clk_id) { 433 case SCLK_I2S1: 434 con = readl(&cru->clksel_con[30]); 435 fracdiv = readl(&cru->clksel_con[31]); 436 gate = readl(&cru->clkgate_con[10]); 437 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 438 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 439 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 440 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 441 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 442 con, gate, fracdiv); 443 break; 444 default: 445 printf("do not support this i2s bus\n"); 446 return -EINVAL; 447 } 448 449 return clk_src * n / m; 450 } 451 452 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 453 { 454 u32 clk_src; 455 unsigned long m, n, val; 456 struct px30_cru *cru = priv->cru; 457 458 clk_src = GPLL_HZ / 2; 459 rational_best_approximation(hz, clk_src, 460 GENMASK(16 - 1, 0), 461 GENMASK(16 - 1, 0), 462 &m, &n); 463 switch (clk_id) { 464 case SCLK_I2S1: 465 rk_clrsetreg(&cru->clksel_con[30], 466 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 467 rk_clrsetreg(&cru->clksel_con[30], 468 CLK_I2S1_DIV_CON_MASK, 0x1); 469 rk_clrsetreg(&cru->clksel_con[30], 470 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 471 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 472 writel(val, &cru->clksel_con[31]); 473 rk_clrsetreg(&cru->clkgate_con[10], 474 CLK_I2S1_OUT_MCLK_PAD_MASK, 475 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 476 break; 477 default: 478 printf("do not support this i2s bus\n"); 479 return -EINVAL; 480 } 481 482 return px30_i2s_get_clk(priv, clk_id); 483 } 484 485 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 486 { 487 struct px30_cru *cru = priv->cru; 488 u32 div, con; 489 490 con = readl(&cru->clksel_con[15]); 491 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 492 493 return DIV_TO_RATE(priv->gpll_hz, div); 494 } 495 496 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 497 ulong set_rate) 498 { 499 struct px30_cru *cru = priv->cru; 500 int src_clk_div; 501 502 /* Select nandc source from GPLL by default */ 503 /* nandc clock defaulg div 2 internal, need provide double in cru */ 504 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 505 assert(src_clk_div - 1 <= 31); 506 507 rk_clrsetreg(&cru->clksel_con[15], 508 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 509 NANDC_DIV_MASK, 510 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 511 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 512 (src_clk_div - 1) << NANDC_DIV_SHIFT); 513 514 return px30_nandc_get_clk(priv); 515 } 516 517 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 518 { 519 struct px30_cru *cru = priv->cru; 520 u32 div, con, con_id; 521 522 switch (clk_id) { 523 case HCLK_SDMMC: 524 case SCLK_SDMMC: 525 con_id = 16; 526 break; 527 case HCLK_EMMC: 528 case SCLK_EMMC: 529 case SCLK_EMMC_SAMPLE: 530 con_id = 20; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 con = readl(&cru->clksel_con[con_id]); 537 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 538 539 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 540 == EMMC_SEL_24M) 541 return DIV_TO_RATE(OSC_HZ, div) / 2; 542 else 543 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 544 545 } 546 547 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 548 ulong clk_id, ulong set_rate) 549 { 550 struct px30_cru *cru = priv->cru; 551 int src_clk_div; 552 u32 con_id; 553 554 switch (clk_id) { 555 case HCLK_SDMMC: 556 case SCLK_SDMMC: 557 con_id = 16; 558 break; 559 case HCLK_EMMC: 560 case SCLK_EMMC: 561 con_id = 20; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 /* Select clk_sdmmc/emmc source from GPLL by default */ 568 /* mmc clock defaulg div 2 internal, need provide double in cru */ 569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 570 571 if (src_clk_div > 127) { 572 /* use 24MHz source for 400KHz clock */ 573 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 574 rk_clrsetreg(&cru->clksel_con[con_id], 575 EMMC_PLL_MASK | EMMC_DIV_MASK, 576 EMMC_SEL_24M << EMMC_PLL_SHIFT | 577 (src_clk_div - 1) << EMMC_DIV_SHIFT); 578 } else { 579 rk_clrsetreg(&cru->clksel_con[con_id], 580 EMMC_PLL_MASK | EMMC_DIV_MASK, 581 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 582 (src_clk_div - 1) << EMMC_DIV_SHIFT); 583 } 584 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 585 EMMC_CLK_SEL_EMMC); 586 587 return px30_mmc_get_clk(priv, clk_id); 588 } 589 590 static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id) 591 { 592 struct px30_cru *cru = priv->cru; 593 u32 div, con; 594 595 con = readl(&cru->clksel_con[22]); 596 div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT; 597 598 return DIV_TO_RATE(priv->gpll_hz, div); 599 } 600 601 static ulong px30_sfc_set_clk(struct px30_clk_priv *priv, 602 ulong clk_id, ulong set_rate) 603 { 604 struct px30_cru *cru = priv->cru; 605 int src_clk_div; 606 607 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 608 rk_clrsetreg(&cru->clksel_con[22], 609 SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK, 610 0 << SFC_PLL_SEL_SHIFT | 611 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); 612 613 return px30_sfc_get_clk(priv, clk_id); 614 } 615 616 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 617 { 618 struct px30_cru *cru = priv->cru; 619 u32 div, con; 620 621 switch (clk_id) { 622 case SCLK_PWM0: 623 con = readl(&cru->clksel_con[52]); 624 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 625 break; 626 case SCLK_PWM1: 627 con = readl(&cru->clksel_con[52]); 628 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 629 break; 630 default: 631 printf("do not support this pwm bus\n"); 632 return -EINVAL; 633 } 634 635 return DIV_TO_RATE(priv->gpll_hz, div); 636 } 637 638 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 639 { 640 struct px30_cru *cru = priv->cru; 641 int src_clk_div; 642 643 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 644 assert(src_clk_div - 1 <= 127); 645 646 switch (clk_id) { 647 case SCLK_PWM0: 648 rk_clrsetreg(&cru->clksel_con[52], 649 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 650 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 651 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 652 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 653 break; 654 case SCLK_PWM1: 655 rk_clrsetreg(&cru->clksel_con[52], 656 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 657 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 658 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 659 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 660 break; 661 default: 662 printf("do not support this pwm bus\n"); 663 return -EINVAL; 664 } 665 666 return px30_pwm_get_clk(priv, clk_id); 667 } 668 669 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 670 { 671 struct px30_cru *cru = priv->cru; 672 u32 div, con; 673 674 con = readl(&cru->clksel_con[55]); 675 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 676 677 return DIV_TO_RATE(OSC_HZ, div); 678 } 679 680 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 681 { 682 struct px30_cru *cru = priv->cru; 683 int src_clk_div; 684 685 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 686 assert(src_clk_div - 1 <= 2047); 687 688 rk_clrsetreg(&cru->clksel_con[55], 689 CLK_SARADC_DIV_CON_MASK, 690 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 691 692 return px30_saradc_get_clk(priv); 693 } 694 695 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv) 696 { 697 struct px30_cru *cru = priv->cru; 698 u32 div, con; 699 700 con = readl(&cru->clksel_con[54]); 701 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 702 703 return DIV_TO_RATE(OSC_HZ, div); 704 } 705 706 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) 707 { 708 struct px30_cru *cru = priv->cru; 709 int src_clk_div; 710 711 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 712 assert(src_clk_div - 1 <= 2047); 713 714 rk_clrsetreg(&cru->clksel_con[54], 715 CLK_SARADC_DIV_CON_MASK, 716 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 717 718 return px30_tsadc_get_clk(priv); 719 } 720 721 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 722 { 723 struct px30_cru *cru = priv->cru; 724 u32 div, con; 725 726 switch (clk_id) { 727 case SCLK_SPI0: 728 con = readl(&cru->clksel_con[53]); 729 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 730 break; 731 case SCLK_SPI1: 732 con = readl(&cru->clksel_con[53]); 733 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 734 break; 735 default: 736 printf("do not support this pwm bus\n"); 737 return -EINVAL; 738 } 739 740 return DIV_TO_RATE(priv->gpll_hz, div); 741 } 742 743 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 744 { 745 struct px30_cru *cru = priv->cru; 746 int src_clk_div; 747 748 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 749 assert(src_clk_div - 1 <= 127); 750 751 switch (clk_id) { 752 case SCLK_SPI0: 753 rk_clrsetreg(&cru->clksel_con[53], 754 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 755 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 756 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 757 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 758 break; 759 case SCLK_SPI1: 760 rk_clrsetreg(&cru->clksel_con[53], 761 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 762 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 763 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 764 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 765 break; 766 default: 767 printf("do not support this pwm bus\n"); 768 return -EINVAL; 769 } 770 771 return px30_spi_get_clk(priv, clk_id); 772 } 773 774 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 775 { 776 struct px30_cru *cru = priv->cru; 777 u32 div, con, parent; 778 779 switch (clk_id) { 780 case ACLK_VOPB: 781 case ACLK_VOPL: 782 con = readl(&cru->clksel_con[3]); 783 div = con & ACLK_VO_DIV_MASK; 784 parent = priv->gpll_hz; 785 break; 786 case DCLK_VOPB: 787 con = readl(&cru->clksel_con[5]); 788 div = con & DCLK_VOPB_DIV_MASK; 789 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 790 break; 791 case DCLK_VOPL: 792 con = readl(&cru->clksel_con[8]); 793 div = con & DCLK_VOPL_DIV_MASK; 794 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 795 break; 796 default: 797 return -ENOENT; 798 } 799 800 return DIV_TO_RATE(parent, div); 801 } 802 803 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 804 { 805 struct px30_cru *cru = priv->cru; 806 ulong npll_hz; 807 int src_clk_div; 808 809 switch (clk_id) { 810 case ACLK_VOPB: 811 case ACLK_VOPL: 812 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 813 assert(src_clk_div - 1 <= 31); 814 rk_clrsetreg(&cru->clksel_con[3], 815 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 816 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 817 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 818 break; 819 case DCLK_VOPB: 820 if (hz < PX30_VOP_PLL_LIMIT) { 821 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 822 if (src_clk_div % 2) 823 src_clk_div = src_clk_div - 1; 824 } else { 825 src_clk_div = 1; 826 } 827 assert(src_clk_div - 1 <= 255); 828 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 829 rk_clrsetreg(&cru->clksel_con[5], 830 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 831 DCLK_VOPB_DIV_MASK, 832 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 833 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 834 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 835 break; 836 case DCLK_VOPL: 837 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 838 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 839 src_clk_div = npll_hz / hz; 840 assert(src_clk_div - 1 <= 255); 841 } else { 842 if (hz < PX30_VOP_PLL_LIMIT) { 843 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 844 if (src_clk_div % 2) 845 src_clk_div = src_clk_div - 1; 846 } else { 847 src_clk_div = 1; 848 } 849 assert(src_clk_div - 1 <= 255); 850 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 851 } 852 rk_clrsetreg(&cru->clksel_con[8], 853 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 854 DCLK_VOPL_DIV_MASK, 855 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 856 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 857 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 858 break; 859 default: 860 printf("do not support this vop freq\n"); 861 return -EINVAL; 862 } 863 864 return px30_vop_get_clk(priv, clk_id); 865 } 866 867 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 868 { 869 struct px30_cru *cru = priv->cru; 870 u32 div, con, parent; 871 872 switch (clk_id) { 873 case ACLK_BUS_PRE: 874 con = readl(&cru->clksel_con[23]); 875 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 876 parent = priv->gpll_hz; 877 break; 878 case HCLK_BUS_PRE: 879 con = readl(&cru->clksel_con[24]); 880 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 881 parent = priv->gpll_hz; 882 break; 883 case PCLK_BUS_PRE: 884 case PCLK_WDT_NS: 885 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 886 con = readl(&cru->clksel_con[24]); 887 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 888 break; 889 default: 890 return -ENOENT; 891 } 892 893 return DIV_TO_RATE(parent, div); 894 } 895 896 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 897 ulong hz) 898 { 899 struct px30_cru *cru = priv->cru; 900 int src_clk_div; 901 902 /* 903 * select gpll as pd_bus bus clock source and 904 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 905 */ 906 switch (clk_id) { 907 case ACLK_BUS_PRE: 908 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 909 assert(src_clk_div - 1 <= 31); 910 rk_clrsetreg(&cru->clksel_con[23], 911 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 912 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 913 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 914 break; 915 case HCLK_BUS_PRE: 916 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 917 assert(src_clk_div - 1 <= 31); 918 rk_clrsetreg(&cru->clksel_con[24], 919 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 920 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 921 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 922 break; 923 case PCLK_BUS_PRE: 924 src_clk_div = 925 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 926 assert(src_clk_div - 1 <= 3); 927 rk_clrsetreg(&cru->clksel_con[24], 928 BUS_PCLK_DIV_MASK, 929 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 930 break; 931 default: 932 printf("do not support this bus freq\n"); 933 return -EINVAL; 934 } 935 936 return px30_bus_get_clk(priv, clk_id); 937 } 938 939 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 940 { 941 struct px30_cru *cru = priv->cru; 942 u32 div, con, parent; 943 944 switch (clk_id) { 945 case ACLK_PERI_PRE: 946 con = readl(&cru->clksel_con[14]); 947 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 948 parent = priv->gpll_hz; 949 break; 950 case HCLK_PERI_PRE: 951 con = readl(&cru->clksel_con[14]); 952 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 953 parent = priv->gpll_hz; 954 break; 955 default: 956 return -ENOENT; 957 } 958 959 return DIV_TO_RATE(parent, div); 960 } 961 962 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 963 ulong hz) 964 { 965 struct px30_cru *cru = priv->cru; 966 int src_clk_div; 967 968 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 969 assert(src_clk_div - 1 <= 31); 970 971 /* 972 * select gpll as pd_peri bus clock source and 973 * set up dependent divisors for HCLK and ACLK clocks. 974 */ 975 switch (clk_id) { 976 case ACLK_PERI_PRE: 977 rk_clrsetreg(&cru->clksel_con[14], 978 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 979 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 980 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 981 break; 982 case HCLK_PERI_PRE: 983 rk_clrsetreg(&cru->clksel_con[14], 984 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 985 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 986 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 987 break; 988 default: 989 printf("do not support this peri freq\n"); 990 return -EINVAL; 991 } 992 993 return px30_peri_get_clk(priv, clk_id); 994 } 995 996 #ifndef CONFIG_SPL_BUILD 997 static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) 998 { 999 struct px30_cru *cru = priv->cru; 1000 u32 div, con, parent; 1001 1002 switch (clk_id) { 1003 case SCLK_CRYPTO: 1004 con = readl(&cru->clksel_con[25]); 1005 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; 1006 parent = priv->gpll_hz; 1007 break; 1008 case SCLK_CRYPTO_APK: 1009 con = readl(&cru->clksel_con[25]); 1010 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; 1011 parent = priv->gpll_hz; 1012 break; 1013 default: 1014 return -ENOENT; 1015 } 1016 1017 return DIV_TO_RATE(parent, div); 1018 } 1019 1020 static ulong px30_crypto_set_clk(struct px30_clk_priv *priv, ulong clk_id, 1021 ulong hz) 1022 { 1023 struct px30_cru *cru = priv->cru; 1024 int src_clk_div; 1025 1026 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1027 assert(src_clk_div - 1 <= 31); 1028 1029 /* 1030 * select gpll as crypto clock source and 1031 * set up dependent divisors for crypto clocks. 1032 */ 1033 switch (clk_id) { 1034 case SCLK_CRYPTO: 1035 rk_clrsetreg(&cru->clksel_con[25], 1036 CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK, 1037 CRYPTO_PLL_SEL_GPLL << CRYPTO_PLL_SEL_SHIFT | 1038 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); 1039 break; 1040 case SCLK_CRYPTO_APK: 1041 rk_clrsetreg(&cru->clksel_con[25], 1042 CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK, 1043 CRYPTO_PLL_SEL_GPLL << CRYPTO_APK_SEL_SHIFT | 1044 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); 1045 break; 1046 default: 1047 printf("do not support this peri freq\n"); 1048 return -EINVAL; 1049 } 1050 1051 return px30_crypto_get_clk(priv, clk_id); 1052 } 1053 1054 static ulong px30_i2s1_mclk_get_clk(struct px30_clk_priv *priv, ulong clk_id) 1055 { 1056 struct px30_cru *cru = priv->cru; 1057 u32 con; 1058 1059 con = readl(&cru->clksel_con[30]); 1060 1061 if (!(con & CLK_I2S1_OUT_SEL_MASK)) 1062 return -ENOENT; 1063 1064 return 12000000; 1065 } 1066 1067 static ulong px30_i2s1_mclk_set_clk(struct px30_clk_priv *priv, ulong clk_id, 1068 ulong hz) 1069 { 1070 struct px30_cru *cru = priv->cru; 1071 1072 if (hz != 12000000) { 1073 printf("do not support this i2s1_mclk freq\n"); 1074 return -EINVAL; 1075 } 1076 1077 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, 1078 CLK_I2S1_OUT_SEL_OSC); 1079 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK, 1080 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 1081 1082 return px30_i2s1_mclk_get_clk(priv, clk_id); 1083 } 1084 1085 static ulong px30_mac_set_clk(struct clk *clk, uint hz) 1086 { 1087 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1088 struct px30_cru *cru = priv->cru; 1089 u32 con = readl(&cru->clksel_con[22]); 1090 ulong pll_rate; 1091 u8 div; 1092 1093 if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_CPLL) 1094 pll_rate = px30_clk_get_pll_rate(priv, CPLL); 1095 else if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_NPLL) 1096 pll_rate = px30_clk_get_pll_rate(priv, NPLL); 1097 else 1098 pll_rate = priv->gpll_hz; 1099 1100 /*default set 50MHZ for gmac*/ 1101 if (!hz) 1102 hz = 50000000; 1103 1104 div = DIV_ROUND_UP(pll_rate, hz) - 1; 1105 assert(div < 32); 1106 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK, 1107 div << CLK_GMAC_DIV_SHIFT); 1108 1109 return DIV_TO_RATE(pll_rate, div); 1110 } 1111 1112 static int px30_mac_set_speed_clk(struct clk *clk, uint hz) 1113 { 1114 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1115 struct px30_cru *cru = priv->cru; 1116 1117 if (hz != 2500000 && hz != 25000000) { 1118 debug("Unsupported mac speed:%d\n", hz); 1119 return -EINVAL; 1120 } 1121 1122 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK, 1123 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT); 1124 1125 return 0; 1126 } 1127 1128 #endif 1129 1130 static int px30_clk_get_gpll_rate(ulong *rate) 1131 { 1132 struct udevice *pmucru_dev; 1133 struct px30_pmuclk_priv *priv; 1134 int ret; 1135 1136 ret = uclass_get_device_by_driver(UCLASS_CLK, 1137 DM_GET_DRIVER(rockchip_px30_pmucru), 1138 &pmucru_dev); 1139 if (ret) { 1140 printf("%s: could not find pmucru device\n", __func__); 1141 return ret; 1142 } 1143 priv = dev_get_priv(pmucru_dev); 1144 *rate = priv->gpll_hz; 1145 1146 return 0; 1147 } 1148 1149 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 1150 enum px30_pll_id pll_id) 1151 { 1152 struct px30_cru *cru = priv->cru; 1153 1154 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1155 } 1156 1157 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 1158 enum px30_pll_id pll_id, ulong hz) 1159 { 1160 struct px30_cru *cru = priv->cru; 1161 1162 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 1163 return -EINVAL; 1164 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1165 } 1166 1167 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 1168 { 1169 struct px30_cru *cru = priv->cru; 1170 const struct cpu_rate_table *rate; 1171 ulong old_rate; 1172 1173 rate = get_cpu_settings(hz); 1174 if (!rate) { 1175 printf("%s unsupport rate\n", __func__); 1176 return -EINVAL; 1177 } 1178 1179 /* 1180 * select apll as cpu/core clock pll source and 1181 * set up dependent divisors for PERI and ACLK clocks. 1182 * core hz : apll = 1:1 1183 */ 1184 old_rate = px30_clk_get_pll_rate(priv, APLL); 1185 if (old_rate > hz) { 1186 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1187 return -EINVAL; 1188 rk_clrsetreg(&cru->clksel_con[0], 1189 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1190 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1191 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1192 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1193 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1194 0 << CORE_DIV_CON_SHIFT); 1195 } else if (old_rate < hz) { 1196 rk_clrsetreg(&cru->clksel_con[0], 1197 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1198 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1199 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1200 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1201 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1202 0 << CORE_DIV_CON_SHIFT); 1203 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1204 return -EINVAL; 1205 } 1206 1207 return px30_clk_get_pll_rate(priv, APLL); 1208 } 1209 1210 static ulong px30_clk_get_rate(struct clk *clk) 1211 { 1212 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1213 ulong rate = 0; 1214 1215 if (!priv->gpll_hz && clk->id > ARMCLK) { 1216 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1217 return -ENOENT; 1218 } 1219 1220 debug("%s %ld\n", __func__, clk->id); 1221 switch (clk->id) { 1222 case PLL_APLL: 1223 rate = px30_clk_get_pll_rate(priv, APLL); 1224 break; 1225 case PLL_DPLL: 1226 rate = px30_clk_get_pll_rate(priv, DPLL); 1227 break; 1228 case PLL_CPLL: 1229 rate = px30_clk_get_pll_rate(priv, CPLL); 1230 break; 1231 case PLL_NPLL: 1232 rate = px30_clk_get_pll_rate(priv, NPLL); 1233 break; 1234 case ARMCLK: 1235 rate = px30_clk_get_pll_rate(priv, APLL); 1236 break; 1237 case HCLK_SDMMC: 1238 case HCLK_EMMC: 1239 case SCLK_SDMMC: 1240 case SCLK_EMMC: 1241 case SCLK_EMMC_SAMPLE: 1242 rate = px30_mmc_get_clk(priv, clk->id); 1243 break; 1244 case SCLK_SFC: 1245 rate = px30_sfc_get_clk(priv, clk->id); 1246 break; 1247 case SCLK_I2C0: 1248 case SCLK_I2C1: 1249 case SCLK_I2C2: 1250 case SCLK_I2C3: 1251 rate = px30_i2c_get_clk(priv, clk->id); 1252 break; 1253 case SCLK_I2S1: 1254 rate = px30_i2s_get_clk(priv, clk->id); 1255 break; 1256 case SCLK_PWM0: 1257 case SCLK_PWM1: 1258 rate = px30_pwm_get_clk(priv, clk->id); 1259 break; 1260 case SCLK_SARADC: 1261 rate = px30_saradc_get_clk(priv); 1262 break; 1263 case SCLK_TSADC: 1264 rate = px30_tsadc_get_clk(priv); 1265 break; 1266 case SCLK_SPI0: 1267 case SCLK_SPI1: 1268 rate = px30_spi_get_clk(priv, clk->id); 1269 break; 1270 case ACLK_VOPB: 1271 case ACLK_VOPL: 1272 case DCLK_VOPB: 1273 case DCLK_VOPL: 1274 rate = px30_vop_get_clk(priv, clk->id); 1275 break; 1276 case ACLK_BUS_PRE: 1277 case HCLK_BUS_PRE: 1278 case PCLK_BUS_PRE: 1279 case PCLK_WDT_NS: 1280 rate = px30_bus_get_clk(priv, clk->id); 1281 break; 1282 case ACLK_PERI_PRE: 1283 case HCLK_PERI_PRE: 1284 rate = px30_peri_get_clk(priv, clk->id); 1285 break; 1286 #ifndef CONFIG_SPL_BUILD 1287 case SCLK_CRYPTO: 1288 case SCLK_CRYPTO_APK: 1289 rate = px30_crypto_get_clk(priv, clk->id); 1290 break; 1291 #endif 1292 default: 1293 return -ENOENT; 1294 } 1295 1296 return rate; 1297 } 1298 1299 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1300 { 1301 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1302 ulong ret = 0; 1303 1304 if (!priv->gpll_hz && clk->id > ARMCLK) { 1305 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1306 return -ENOENT; 1307 } 1308 1309 debug("%s %ld %ld\n", __func__, clk->id, rate); 1310 switch (clk->id) { 1311 case PLL_NPLL: 1312 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1313 break; 1314 case ARMCLK: 1315 if (priv->armclk_hz) 1316 px30_armclk_set_clk(priv, rate); 1317 priv->armclk_hz = rate; 1318 break; 1319 case HCLK_SDMMC: 1320 case HCLK_EMMC: 1321 case SCLK_SDMMC: 1322 case SCLK_EMMC: 1323 ret = px30_mmc_set_clk(priv, clk->id, rate); 1324 break; 1325 case SCLK_SFC: 1326 ret = px30_sfc_set_clk(priv, clk->id, rate); 1327 break; 1328 case SCLK_I2C0: 1329 case SCLK_I2C1: 1330 case SCLK_I2C2: 1331 case SCLK_I2C3: 1332 ret = px30_i2c_set_clk(priv, clk->id, rate); 1333 break; 1334 case SCLK_I2S1: 1335 ret = px30_i2s_set_clk(priv, clk->id, rate); 1336 break; 1337 case SCLK_PWM0: 1338 case SCLK_PWM1: 1339 ret = px30_pwm_set_clk(priv, clk->id, rate); 1340 break; 1341 case SCLK_SARADC: 1342 ret = px30_saradc_set_clk(priv, rate); 1343 break; 1344 case SCLK_TSADC: 1345 ret = px30_tsadc_set_clk(priv, rate); 1346 break; 1347 case SCLK_SPI0: 1348 case SCLK_SPI1: 1349 ret = px30_spi_set_clk(priv, clk->id, rate); 1350 break; 1351 case ACLK_VOPB: 1352 case ACLK_VOPL: 1353 case DCLK_VOPB: 1354 case DCLK_VOPL: 1355 ret = px30_vop_set_clk(priv, clk->id, rate); 1356 break; 1357 case ACLK_BUS_PRE: 1358 case HCLK_BUS_PRE: 1359 case PCLK_BUS_PRE: 1360 ret = px30_bus_set_clk(priv, clk->id, rate); 1361 break; 1362 case ACLK_PERI_PRE: 1363 case HCLK_PERI_PRE: 1364 ret = px30_peri_set_clk(priv, clk->id, rate); 1365 break; 1366 #ifndef CONFIG_SPL_BUILD 1367 case SCLK_CRYPTO: 1368 case SCLK_CRYPTO_APK: 1369 ret = px30_crypto_set_clk(priv, clk->id, rate); 1370 break; 1371 case SCLK_I2S1_OUT: 1372 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); 1373 break; 1374 case SCLK_GMAC: 1375 case SCLK_GMAC_SRC: 1376 ret = px30_mac_set_clk(clk, rate); 1377 break; 1378 case SCLK_GMAC_RMII: 1379 ret = px30_mac_set_speed_clk(clk, rate); 1380 break; 1381 #endif 1382 default: 1383 return -ENOENT; 1384 } 1385 1386 return ret; 1387 } 1388 1389 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1390 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1391 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1392 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1393 1394 #define PSECS_PER_SEC 1000000000000LL 1395 /* 1396 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1397 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1398 */ 1399 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1400 1401 int rockchip_mmc_get_phase(struct clk *clk) 1402 { 1403 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1404 struct px30_cru *cru = priv->cru; 1405 u32 raw_value, delay_num; 1406 u16 degrees = 0; 1407 ulong rate; 1408 1409 rate = px30_clk_get_rate(clk); 1410 1411 if (rate < 0) 1412 return rate; 1413 1414 if (clk->id == SCLK_EMMC_SAMPLE) 1415 raw_value = readl(&cru->emmc_con[1]); 1416 else 1417 raw_value = readl(&cru->sdmmc_con[1]); 1418 1419 raw_value >>= 1; 1420 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1421 1422 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1423 /* degrees/delaynum * 10000 */ 1424 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1425 36 * (rate / 1000000); 1426 1427 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1428 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1429 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1430 } 1431 1432 return degrees % 360; 1433 } 1434 1435 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1436 { 1437 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1438 struct px30_cru *cru = priv->cru; 1439 u8 nineties, remainder, delay_num; 1440 u32 raw_value, delay; 1441 ulong rate; 1442 1443 rate = px30_clk_get_rate(clk); 1444 1445 if (rate < 0) 1446 return rate; 1447 1448 nineties = degrees / 90; 1449 remainder = (degrees % 90); 1450 1451 /* 1452 * Convert to delay; do a little extra work to make sure we 1453 * don't overflow 32-bit / 64-bit numbers. 1454 */ 1455 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1456 delay *= remainder; 1457 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1458 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1459 1460 delay_num = (u8)min_t(u32, delay, 255); 1461 1462 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1463 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1464 raw_value |= nineties; 1465 1466 raw_value <<= 1; 1467 if (clk->id == SCLK_EMMC_SAMPLE) 1468 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1469 else 1470 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1471 1472 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1473 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1474 1475 return 0; 1476 } 1477 1478 static int px30_clk_get_phase(struct clk *clk) 1479 { 1480 int ret; 1481 1482 debug("%s %ld\n", __func__, clk->id); 1483 switch (clk->id) { 1484 case SCLK_EMMC_SAMPLE: 1485 case SCLK_SDMMC_SAMPLE: 1486 ret = rockchip_mmc_get_phase(clk); 1487 break; 1488 default: 1489 return -ENOENT; 1490 } 1491 1492 return ret; 1493 } 1494 1495 static int px30_clk_set_phase(struct clk *clk, int degrees) 1496 { 1497 int ret; 1498 1499 debug("%s %ld\n", __func__, clk->id); 1500 switch (clk->id) { 1501 case SCLK_EMMC_SAMPLE: 1502 case SCLK_SDMMC_SAMPLE: 1503 ret = rockchip_mmc_set_phase(clk, degrees); 1504 break; 1505 default: 1506 return -ENOENT; 1507 } 1508 1509 return ret; 1510 } 1511 1512 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1513 static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) 1514 { 1515 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1516 struct px30_cru *cru = priv->cru; 1517 1518 if (parent->id == SCLK_GMAC_SRC) { 1519 debug("%s: switching GAMC to SCLK_GMAC_SRC\n", __func__); 1520 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1521 RMII_EXTCLK_SEL_INT << RMII_EXTCLK_SEL_SHIFT); 1522 } else { 1523 debug("%s: switching GMAC to external clock\n", __func__); 1524 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1525 RMII_EXTCLK_SEL_EXT << RMII_EXTCLK_SEL_SHIFT); 1526 } 1527 return 0; 1528 } 1529 1530 static int px30_clk_set_parent(struct clk *clk, struct clk *parent) 1531 { 1532 switch (clk->id) { 1533 case SCLK_GMAC: 1534 return px30_gmac_set_parent(clk, parent); 1535 default: 1536 return -ENOENT; 1537 } 1538 } 1539 #endif 1540 1541 static struct clk_ops px30_clk_ops = { 1542 .get_rate = px30_clk_get_rate, 1543 .set_rate = px30_clk_set_rate, 1544 .get_phase = px30_clk_get_phase, 1545 .set_phase = px30_clk_set_phase, 1546 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1547 .set_parent = px30_clk_set_parent, 1548 #endif 1549 }; 1550 1551 static int px30_clk_probe(struct udevice *dev) 1552 { 1553 struct px30_clk_priv *priv = dev_get_priv(dev); 1554 int ret; 1555 1556 priv->sync_kernel = false; 1557 if (!priv->armclk_enter_hz) { 1558 priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL); 1559 priv->armclk_init_hz = priv->armclk_enter_hz; 1560 } 1561 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1562 ret = px30_armclk_set_clk(priv, APLL_HZ); 1563 if (ret < 0) 1564 printf("%s failed to set armclk rate\n", __func__); 1565 priv->armclk_init_hz = APLL_HZ; 1566 } 1567 1568 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1569 ret = clk_set_defaults(dev); 1570 if (ret) 1571 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1572 else 1573 priv->sync_kernel = true; 1574 1575 if (!priv->gpll_hz) { 1576 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1577 if (ret) { 1578 printf("%s failed to get gpll rate\n", __func__); 1579 return ret; 1580 } 1581 } 1582 1583 return 0; 1584 } 1585 1586 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1587 { 1588 struct px30_clk_priv *priv = dev_get_priv(dev); 1589 1590 priv->cru = dev_read_addr_ptr(dev); 1591 1592 return 0; 1593 } 1594 1595 static int px30_clk_bind(struct udevice *dev) 1596 { 1597 int ret; 1598 struct udevice *sys_child, *sf_child; 1599 struct sysreset_reg *priv; 1600 struct softreset_reg *sf_priv; 1601 1602 /* The reset driver does not have a device node, so bind it here */ 1603 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1604 &sys_child); 1605 if (ret) { 1606 debug("Warning: No sysreset driver: ret=%d\n", ret); 1607 } else { 1608 priv = malloc(sizeof(struct sysreset_reg)); 1609 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1610 glb_srst_fst); 1611 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1612 glb_srst_snd); 1613 sys_child->priv = priv; 1614 } 1615 1616 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1617 dev_ofnode(dev), &sf_child); 1618 if (ret) { 1619 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1620 } else { 1621 sf_priv = malloc(sizeof(struct softreset_reg)); 1622 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1623 softrst_con[0]); 1624 sf_priv->sf_reset_num = 12; 1625 sf_child->priv = sf_priv; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static const struct udevice_id px30_clk_ids[] = { 1632 { .compatible = "rockchip,px30-cru" }, 1633 { } 1634 }; 1635 1636 U_BOOT_DRIVER(rockchip_px30_cru) = { 1637 .name = "rockchip_px30_cru", 1638 .id = UCLASS_CLK, 1639 .of_match = px30_clk_ids, 1640 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1641 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1642 .ops = &px30_clk_ops, 1643 .bind = px30_clk_bind, 1644 .probe = px30_clk_probe, 1645 }; 1646 1647 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1648 { 1649 struct px30_pmucru *pmucru = priv->pmucru; 1650 u32 div, con; 1651 1652 con = readl(&pmucru->pmu_clksel_con[0]); 1653 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1654 1655 return DIV_TO_RATE(priv->gpll_hz, div); 1656 } 1657 1658 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1659 { 1660 struct px30_pmucru *pmucru = priv->pmucru; 1661 int src_clk_div; 1662 1663 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1664 assert(src_clk_div - 1 <= 31); 1665 1666 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1667 CLK_PMU_PCLK_DIV_MASK, 1668 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1669 1670 return px30_pclk_pmu_get_pmuclk(priv); 1671 } 1672 1673 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1674 { 1675 struct px30_pmucru *pmucru = priv->pmucru; 1676 1677 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1678 } 1679 1680 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1681 { 1682 struct udevice *cru_dev; 1683 struct px30_clk_priv *cru_priv; 1684 struct px30_pmucru *pmucru = priv->pmucru; 1685 u32 div; 1686 ulong emmc_rate, sdmmc_rate, nandc_rate, sfc_rate; 1687 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1688 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1689 int ret; 1690 1691 ret = uclass_get_device_by_name(UCLASS_CLK, 1692 "clock-controller@ff2b0000", 1693 &cru_dev); 1694 if (ret) { 1695 printf("%s failed to get cru device\n", __func__); 1696 return ret; 1697 } 1698 cru_priv = dev_get_priv(cru_dev); 1699 1700 if (priv->gpll_hz == hz) 1701 return priv->gpll_hz; 1702 1703 cru_priv->gpll_hz = priv->gpll_hz; 1704 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1705 1706 /* save clock rate */ 1707 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1708 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1709 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1710 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1711 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1712 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1713 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1714 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1715 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1716 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1717 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1718 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1719 nandc_rate = px30_nandc_get_clk(cru_priv); 1720 sfc_rate = px30_sfc_get_clk(cru_priv, SCLK_SFC); 1721 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu sfc=%lu\n", __func__, 1722 emmc_rate, sdmmc_rate, nandc_rate, sfc_rate); 1723 1724 /* avoid rate too large, reduce rate first */ 1725 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1726 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1727 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1728 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1729 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1730 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1731 1732 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1733 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1734 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1735 px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate / div); 1736 1737 /* change gpll rate */ 1738 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1739 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1740 cru_priv->gpll_hz = priv->gpll_hz; 1741 1742 /* restore clock rate */ 1743 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1744 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1745 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1746 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1747 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1748 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1749 1750 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1751 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1752 px30_nandc_set_clk(cru_priv, nandc_rate); 1753 px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate); 1754 1755 return priv->gpll_hz; 1756 } 1757 1758 static ulong px30_pmuclk_get_rate(struct clk *clk) 1759 { 1760 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1761 ulong rate = 0; 1762 1763 debug("%s %ld\n", __func__, clk->id); 1764 switch (clk->id) { 1765 case PLL_GPLL: 1766 rate = px30_gpll_get_pmuclk(priv); 1767 break; 1768 case PCLK_PMU_PRE: 1769 rate = px30_pclk_pmu_get_pmuclk(priv); 1770 break; 1771 default: 1772 return -ENOENT; 1773 } 1774 1775 return rate; 1776 } 1777 1778 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1779 { 1780 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1781 ulong ret = 0; 1782 1783 debug("%s %ld %ld\n", __func__, clk->id, rate); 1784 switch (clk->id) { 1785 case PLL_GPLL: 1786 ret = px30_gpll_set_pmuclk(priv, rate); 1787 break; 1788 case PCLK_PMU_PRE: 1789 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1790 break; 1791 default: 1792 return -ENOENT; 1793 } 1794 1795 return ret; 1796 } 1797 1798 static struct clk_ops px30_pmuclk_ops = { 1799 .get_rate = px30_pmuclk_get_rate, 1800 .set_rate = px30_pmuclk_set_rate, 1801 }; 1802 1803 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1804 { 1805 struct udevice *cru_dev; 1806 struct px30_clk_priv *cru_priv; 1807 ulong npll_hz; 1808 int ret; 1809 1810 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1811 if (priv->gpll_hz != GPLL_HZ) { 1812 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1813 if (ret < 0) 1814 printf("%s failed to set gpll rate\n", __func__); 1815 } 1816 1817 ret = uclass_get_device_by_name(UCLASS_CLK, 1818 "clock-controller@ff2b0000", 1819 &cru_dev); 1820 if (ret) { 1821 printf("%s failed to get cru device\n", __func__); 1822 return; 1823 } 1824 cru_priv = dev_get_priv(cru_dev); 1825 cru_priv->gpll_hz = priv->gpll_hz; 1826 1827 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1828 if (npll_hz != NPLL_HZ) { 1829 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1830 if (ret < 0) 1831 printf("%s failed to set npll rate\n", __func__); 1832 } 1833 1834 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1835 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1836 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1837 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1838 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1839 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1840 } 1841 1842 static int px30_pmuclk_probe(struct udevice *dev) 1843 { 1844 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1845 int ret; 1846 1847 px30_clk_init(priv); 1848 1849 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1850 ret = clk_set_defaults(dev); 1851 if (ret) 1852 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1853 1854 return 0; 1855 } 1856 1857 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1858 { 1859 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1860 1861 priv->pmucru = dev_read_addr_ptr(dev); 1862 1863 return 0; 1864 } 1865 1866 static const struct udevice_id px30_pmuclk_ids[] = { 1867 { .compatible = "rockchip,px30-pmucru" }, 1868 { } 1869 }; 1870 1871 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1872 .name = "rockchip_px30_pmucru", 1873 .id = UCLASS_CLK, 1874 .of_match = px30_pmuclk_ids, 1875 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1876 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1877 .ops = &px30_pmuclk_ops, 1878 .probe = px30_pmuclk_probe, 1879 }; 1880 1881 /** 1882 * soc_clk_dump() - Print clock frequencies 1883 * Returns zero on success 1884 * 1885 * Implementation for the clk dump command. 1886 */ 1887 int soc_clk_dump(void) 1888 { 1889 struct udevice *cru_dev, *pmucru_dev; 1890 struct px30_clk_priv *priv; 1891 const struct px30_clk_info *clk_dump; 1892 struct clk clk; 1893 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1894 unsigned long rate; 1895 int i, ret; 1896 1897 ret = uclass_get_device_by_driver(UCLASS_CLK, 1898 DM_GET_DRIVER(rockchip_px30_cru), 1899 &cru_dev); 1900 if (ret) { 1901 printf("%s failed to get cru device\n", __func__); 1902 return ret; 1903 } 1904 1905 ret = uclass_get_device_by_driver(UCLASS_CLK, 1906 DM_GET_DRIVER(rockchip_px30_pmucru), 1907 &pmucru_dev); 1908 if (ret) { 1909 printf("%s failed to get pmucru device\n", __func__); 1910 return ret; 1911 } 1912 1913 priv = dev_get_priv(cru_dev); 1914 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1915 priv->sync_kernel ? "sync kernel" : "uboot", 1916 priv->armclk_enter_hz / 1000, 1917 priv->armclk_init_hz / 1000, 1918 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 1919 priv->set_armclk_rate ? " KHz" : "N/A"); 1920 for (i = 0; i < clk_count; i++) { 1921 clk_dump = &clks_dump[i]; 1922 if (clk_dump->name) { 1923 clk.id = clk_dump->id; 1924 if (clk_dump->is_cru) 1925 ret = clk_request(cru_dev, &clk); 1926 else 1927 ret = clk_request(pmucru_dev, &clk); 1928 if (ret < 0) 1929 return ret; 1930 1931 rate = clk_get_rate(&clk); 1932 clk_free(&clk); 1933 if (i == 0) { 1934 if (rate < 0) 1935 printf(" %s %s\n", clk_dump->name, 1936 "unknown"); 1937 else 1938 printf(" %s %lu KHz\n", clk_dump->name, 1939 rate / 1000); 1940 } else { 1941 if (rate < 0) 1942 printf(" %s %s\n", clk_dump->name, 1943 "unknown"); 1944 else 1945 printf(" %s %lu KHz\n", clk_dump->name, 1946 rate / 1000); 1947 } 1948 } 1949 } 1950 1951 return 0; 1952 } 1953