1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_rst: phy reset control. 153 * @phy_cfg: phy register configuration, assigned by driver data. 154 */ 155 struct rockchip_usb2phy { 156 u8 dcd_retries; 157 u8 primary_retries; 158 struct regmap *grf_base; 159 struct regmap *usbgrf_base; 160 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 161 struct reset_ctl phy_rst; 162 const struct rockchip_usb2phy_cfg *phy_cfg; 163 }; 164 165 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 166 { 167 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 168 } 169 170 static inline int property_enable(struct regmap *base, 171 const struct usb2phy_reg *reg, bool en) 172 { 173 u32 val, mask, tmp; 174 175 tmp = en ? reg->enable : reg->disable; 176 mask = GENMASK(reg->bitend, reg->bitstart); 177 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 178 179 return regmap_write(base, reg->offset, val); 180 } 181 182 static inline bool property_enabled(struct regmap *base, 183 const struct usb2phy_reg *reg) 184 { 185 u32 tmp, orig; 186 u32 mask = GENMASK(reg->bitend, reg->bitstart); 187 188 regmap_read(base, reg->offset, &orig); 189 190 tmp = (orig & mask) >> reg->bitstart; 191 192 return tmp == reg->enable; 193 } 194 195 static const char *chg_to_string(enum power_supply_type chg_type) 196 { 197 switch (chg_type) { 198 case POWER_SUPPLY_TYPE_USB: 199 return "USB_SDP_CHARGER"; 200 case POWER_SUPPLY_TYPE_USB_DCP: 201 return "USB_DCP_CHARGER"; 202 case POWER_SUPPLY_TYPE_USB_CDP: 203 return "USB_CDP_CHARGER"; 204 case POWER_SUPPLY_TYPE_USB_FLOATING: 205 return "USB_FLOATING_CHARGER"; 206 default: 207 return "INVALID_CHARGER"; 208 } 209 } 210 211 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 212 bool en) 213 { 214 struct regmap *base = get_reg_base(rphy); 215 216 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 217 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 218 } 219 220 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 221 bool en) 222 { 223 struct regmap *base = get_reg_base(rphy); 224 225 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 226 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 227 } 228 229 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 230 bool en) 231 { 232 struct regmap *base = get_reg_base(rphy); 233 234 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 235 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 236 } 237 238 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 239 { 240 bool vout = false; 241 struct regmap *base = get_reg_base(rphy); 242 243 while (rphy->primary_retries--) { 244 /* voltage source on DP, probe on DM */ 245 rockchip_chg_enable_primary_det(rphy, true); 246 mdelay(CHG_PRIMARY_DET_TIME); 247 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 248 if (vout) 249 break; 250 } 251 252 rockchip_chg_enable_primary_det(rphy, false); 253 return vout; 254 } 255 256 int rockchip_chg_get_type(void) 257 { 258 const struct rockchip_usb2phy_port_cfg *port_cfg; 259 enum power_supply_type chg_type; 260 struct rockchip_usb2phy *rphy; 261 struct udevice *udev; 262 struct regmap *base; 263 bool is_dcd, vout; 264 int ret; 265 266 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 267 if (ret == -ENODEV) { 268 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 269 return ret; 270 } 271 272 rphy = dev_get_priv(udev); 273 base = get_reg_base(rphy); 274 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 275 276 /* Check USB-Vbus status first */ 277 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 278 pr_info("%s: no charger found\n", __func__); 279 return POWER_SUPPLY_TYPE_UNKNOWN; 280 } 281 282 /* Suspend USB-PHY and put the controller in non-driving mode */ 283 property_enable(base, &port_cfg->phy_sus, true); 284 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 285 286 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 287 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 288 289 /* stage 1, start DCD processing stage */ 290 rockchip_chg_enable_dcd(rphy, true); 291 292 while (rphy->dcd_retries--) { 293 mdelay(CHG_DCD_POLL_TIME); 294 295 /* get data contact detection status */ 296 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 297 298 if (is_dcd || !rphy->dcd_retries) { 299 /* 300 * stage 2, turn off DCD circuitry, then 301 * voltage source on DP, probe on DM. 302 */ 303 rockchip_chg_enable_dcd(rphy, false); 304 rockchip_chg_enable_primary_det(rphy, true); 305 break; 306 } 307 } 308 309 mdelay(CHG_PRIMARY_DET_TIME); 310 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 311 rockchip_chg_enable_primary_det(rphy, false); 312 if (vout) { 313 /* stage 3, voltage source on DM, probe on DP */ 314 rockchip_chg_enable_secondary_det(rphy, true); 315 } else { 316 if (!rphy->dcd_retries) { 317 /* floating charger found */ 318 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 319 goto out; 320 } else { 321 /* 322 * Retry some times to make sure that it's 323 * really a USB SDP charger. 324 */ 325 vout = rockchip_chg_primary_det_retry(rphy); 326 if (vout) { 327 /* stage 3, voltage source on DM, probe on DP */ 328 rockchip_chg_enable_secondary_det(rphy, true); 329 } else { 330 /* USB SDP charger found */ 331 chg_type = POWER_SUPPLY_TYPE_USB; 332 goto out; 333 } 334 } 335 } 336 337 mdelay(CHG_SECONDARY_DET_TIME); 338 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 339 /* stage 4, turn off voltage source */ 340 rockchip_chg_enable_secondary_det(rphy, false); 341 if (vout) 342 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 343 else 344 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 345 346 out: 347 /* Resume USB-PHY and put the controller in normal mode */ 348 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 349 property_enable(base, &port_cfg->phy_sus, false); 350 351 debug("charger is %s\n", chg_to_string(chg_type)); 352 353 return chg_type; 354 } 355 356 int rockchip_u2phy_vbus_detect(void) 357 { 358 int chg_type; 359 360 chg_type = rockchip_chg_get_type(); 361 362 return (chg_type == POWER_SUPPLY_TYPE_USB || 363 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 364 } 365 366 void otg_phy_init(struct dwc2_udc *dev) 367 { 368 const struct rockchip_usb2phy_port_cfg *port_cfg; 369 struct rockchip_usb2phy *rphy; 370 struct udevice *udev; 371 struct regmap *base; 372 int ret; 373 374 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 375 if (ret == -ENODEV) { 376 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 377 return; 378 } 379 380 rphy = dev_get_priv(udev); 381 base = get_reg_base(rphy); 382 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 383 384 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 385 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 386 387 /* Reset USB-PHY */ 388 property_enable(base, &port_cfg->phy_sus, true); 389 udelay(20); 390 property_enable(base, &port_cfg->phy_sus, false); 391 mdelay(2); 392 } 393 394 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 395 { 396 struct udevice *parent = phy->dev->parent; 397 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 398 const struct rockchip_usb2phy_port_cfg *port_cfg; 399 struct regmap *base = get_reg_base(rphy); 400 struct udevice *vbus = NULL; 401 bool iddig = true; 402 403 if (phy->id == USB2PHY_PORT_HOST) { 404 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 405 } else if (phy->id == USB2PHY_PORT_OTG) { 406 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 407 if (port_cfg->utmi_iddig.offset) { 408 iddig = property_enabled(base, &port_cfg->utmi_iddig); 409 if (!iddig) 410 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 411 } 412 } 413 414 return vbus; 415 } 416 417 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 418 { 419 int ret; 420 421 if (rphy->phy_rst.dev) { 422 ret = reset_assert(&rphy->phy_rst); 423 if (ret < 0) { 424 pr_err("u2phy assert reset failed: %d", ret); 425 return ret; 426 } 427 428 udelay(20); 429 430 ret = reset_deassert(&rphy->phy_rst); 431 if (ret < 0) { 432 pr_err("u2phy deassert reset failed: %d", ret); 433 return ret; 434 } 435 436 udelay(100); 437 } 438 439 return 0; 440 } 441 442 static int rockchip_usb2phy_init(struct phy *phy) 443 { 444 struct udevice *parent = phy->dev->parent; 445 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 446 const struct rockchip_usb2phy_port_cfg *port_cfg; 447 struct regmap *base = get_reg_base(rphy); 448 449 if (phy->id == USB2PHY_PORT_OTG) { 450 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 451 } else if (phy->id == USB2PHY_PORT_HOST) { 452 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 453 } else { 454 dev_err(phy->dev, "phy id %lu not support", phy->id); 455 return -EINVAL; 456 } 457 458 property_enable(base, &port_cfg->phy_sus, false); 459 460 /* waiting for the utmi_clk to become stable */ 461 udelay(2000); 462 463 return 0; 464 } 465 466 static int rockchip_usb2phy_exit(struct phy *phy) 467 { 468 struct udevice *parent = phy->dev->parent; 469 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 470 const struct rockchip_usb2phy_port_cfg *port_cfg; 471 struct regmap *base = get_reg_base(rphy); 472 473 if (phy->id == USB2PHY_PORT_OTG) { 474 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 475 } else if (phy->id == USB2PHY_PORT_HOST) { 476 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 477 } else { 478 dev_err(phy->dev, "phy id %lu not support", phy->id); 479 return -EINVAL; 480 } 481 482 property_enable(base, &port_cfg->phy_sus, true); 483 484 return 0; 485 } 486 487 static int rockchip_usb2phy_power_on(struct phy *phy) 488 { 489 struct udevice *vbus = NULL; 490 int ret; 491 492 vbus = rockchip_usb2phy_check_vbus(phy); 493 if (vbus) { 494 ret = regulator_set_enable(vbus, true); 495 if (ret) { 496 pr_err("%s: Failed to set VBus supply\n", __func__); 497 return ret; 498 } 499 } 500 501 return 0; 502 } 503 504 static int rockchip_usb2phy_power_off(struct phy *phy) 505 { 506 struct udevice *vbus = NULL; 507 int ret; 508 509 vbus = rockchip_usb2phy_check_vbus(phy); 510 if (vbus) { 511 ret = regulator_set_enable(vbus, false); 512 if (ret) { 513 pr_err("%s: Failed to set VBus supply\n", __func__); 514 return ret; 515 } 516 } 517 518 return 0; 519 } 520 521 static int rockchip_usb2phy_of_xlate(struct phy *phy, 522 struct ofnode_phandle_args *args) 523 { 524 const char *dev_name = phy->dev->name; 525 struct udevice *parent = phy->dev->parent; 526 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 527 528 if (!strcasecmp(dev_name, "host-port")) { 529 phy->id = USB2PHY_PORT_HOST; 530 device_get_supply_regulator(phy->dev, "phy-supply", 531 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 532 } else if (!strcasecmp(dev_name, "otg-port")) { 533 phy->id = USB2PHY_PORT_OTG; 534 device_get_supply_regulator(phy->dev, "phy-supply", 535 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 536 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 537 device_get_supply_regulator(phy->dev, "vbus-supply", 538 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 539 } else { 540 pr_err("%s: invalid dev name\n", __func__); 541 return -EINVAL; 542 } 543 544 return 0; 545 } 546 547 static int rockchip_usb2phy_bind(struct udevice *dev) 548 { 549 struct udevice *child; 550 ofnode subnode; 551 const char *node_name; 552 int ret; 553 554 dev_for_each_subnode(subnode, dev) { 555 if (!ofnode_valid(subnode)) { 556 debug("%s: %s subnode not found", __func__, dev->name); 557 return -ENXIO; 558 } 559 560 node_name = ofnode_get_name(subnode); 561 debug("%s: subnode %s\n", __func__, node_name); 562 563 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 564 node_name, subnode, &child); 565 if (ret) { 566 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 567 __func__, node_name); 568 return ret; 569 } 570 } 571 572 return 0; 573 } 574 575 static int rockchip_usb2phy_probe(struct udevice *dev) 576 { 577 const struct rockchip_usb2phy_cfg *phy_cfgs; 578 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 579 struct udevice *parent = dev->parent; 580 struct udevice *syscon; 581 struct resource res; 582 u32 reg, index; 583 int ret; 584 585 if (!strncmp(parent->name, "root_driver", 11) && 586 dev_read_bool(dev, "rockchip,grf")) { 587 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 588 "rockchip,grf", &syscon); 589 if (ret) { 590 dev_err(dev, "get syscon grf failed\n"); 591 return ret; 592 } 593 594 rphy->grf_base = syscon_get_regmap(syscon); 595 } else { 596 rphy->grf_base = syscon_get_regmap(parent); 597 } 598 599 if (rphy->grf_base <= 0) { 600 dev_err(dev, "get syscon grf regmap failed\n"); 601 return -EINVAL; 602 } 603 604 if (dev_read_bool(dev, "rockchip,usbgrf")) { 605 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 606 "rockchip,usbgrf", &syscon); 607 if (ret) { 608 dev_err(dev, "get syscon usbgrf failed\n"); 609 return ret; 610 } 611 612 rphy->usbgrf_base = syscon_get_regmap(syscon); 613 if (rphy->usbgrf_base <= 0) { 614 dev_err(dev, "get syscon usbgrf regmap failed\n"); 615 return -EINVAL; 616 } 617 } else { 618 rphy->usbgrf_base = NULL; 619 } 620 621 if (!strncmp(parent->name, "root_driver", 11)) { 622 ret = dev_read_resource(dev, 0, &res); 623 reg = res.start; 624 } else { 625 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 626 } 627 628 if (ret) { 629 dev_err(dev, "could not read reg\n"); 630 return -EINVAL; 631 } 632 633 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 634 if (ret) 635 dev_dbg(dev, "no u2phy reset control specified\n"); 636 637 phy_cfgs = 638 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 639 if (!phy_cfgs) { 640 dev_err(dev, "unable to get phy_cfgs\n"); 641 return -EINVAL; 642 } 643 644 /* find out a proper config which can be matched with dt. */ 645 index = 0; 646 do { 647 if (phy_cfgs[index].reg == reg) { 648 rphy->phy_cfg = &phy_cfgs[index]; 649 break; 650 } 651 ++index; 652 } while (phy_cfgs[index].reg); 653 654 if (!rphy->phy_cfg) { 655 dev_err(dev, "no phy-config can be matched\n"); 656 return -EINVAL; 657 } 658 659 if (rphy->phy_cfg->phy_tuning) 660 rphy->phy_cfg->phy_tuning(rphy); 661 662 return 0; 663 } 664 665 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 666 { 667 struct regmap *base = get_reg_base(rphy); 668 int ret = 0; 669 670 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 671 if (rphy->phy_cfg->reg == 0x760) 672 ret = regmap_write(base, 0x76c, 0x00070004); 673 674 return ret; 675 } 676 677 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 678 { 679 struct regmap *base = get_reg_base(rphy); 680 unsigned int tmp, orig; 681 int ret; 682 683 if (soc_is_rk3308bs()) { 684 /* Enable otg/host port pre-emphasis during non-chirp phase */ 685 ret = regmap_read(base, 0, &orig); 686 if (ret) 687 return ret; 688 tmp = orig & ~GENMASK(2, 0); 689 tmp |= BIT(2) & GENMASK(2, 0); 690 ret = regmap_write(base, 0, tmp); 691 if (ret) 692 return ret; 693 694 /* Set otg port squelch trigger point configure to 100mv */ 695 ret = regmap_read(base, 0x004, &orig); 696 if (ret) 697 return ret; 698 tmp = orig & ~GENMASK(7, 5); 699 tmp |= 0x40 & GENMASK(7, 5); 700 ret = regmap_write(base, 0x004, tmp); 701 if (ret) 702 return ret; 703 704 ret = regmap_read(base, 0x008, &orig); 705 if (ret) 706 return ret; 707 tmp = orig & ~BIT(0); 708 tmp |= 0x1 & BIT(0); 709 ret = regmap_write(base, 0x008, tmp); 710 if (ret) 711 return ret; 712 713 /* Enable host port pre-emphasis during non-chirp phase */ 714 ret = regmap_read(base, 0x400, &orig); 715 if (ret) 716 return ret; 717 tmp = orig & ~GENMASK(2, 0); 718 tmp |= BIT(2) & GENMASK(2, 0); 719 ret = regmap_write(base, 0x400, tmp); 720 if (ret) 721 return ret; 722 723 /* Set host port squelch trigger point configure to 100mv */ 724 ret = regmap_read(base, 0x404, &orig); 725 if (ret) 726 return ret; 727 tmp = orig & ~GENMASK(7, 5); 728 tmp |= 0x40 & GENMASK(7, 5); 729 ret = regmap_write(base, 0x404, tmp); 730 if (ret) 731 return ret; 732 733 ret = regmap_read(base, 0x408, &orig); 734 if (ret) 735 return ret; 736 tmp = orig & ~BIT(0); 737 tmp |= 0x1 & BIT(0); 738 ret = regmap_write(base, 0x408, tmp); 739 if (ret) 740 return ret; 741 } 742 743 return 0; 744 } 745 746 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 747 { 748 struct regmap *base = get_reg_base(rphy); 749 unsigned int tmp, orig; 750 int ret; 751 752 if (soc_is_px30s()) { 753 /* Enable otg/host port pre-emphasis during non-chirp phase */ 754 ret = regmap_read(base, 0x8000, &orig); 755 if (ret) 756 return ret; 757 tmp = orig & ~GENMASK(2, 0); 758 tmp |= BIT(2) & GENMASK(2, 0); 759 ret = regmap_write(base, 0x8000, tmp); 760 if (ret) 761 return ret; 762 763 /* Set otg port squelch trigger point configure to 100mv */ 764 ret = regmap_read(base, 0x8004, &orig); 765 if (ret) 766 return ret; 767 tmp = orig & ~GENMASK(7, 5); 768 tmp |= 0x40 & GENMASK(7, 5); 769 ret = regmap_write(base, 0x8004, tmp); 770 if (ret) 771 return ret; 772 773 ret = regmap_read(base, 0x8008, &orig); 774 if (ret) 775 return ret; 776 tmp = orig & ~BIT(0); 777 tmp |= 0x1 & BIT(0); 778 ret = regmap_write(base, 0x8008, tmp); 779 if (ret) 780 return ret; 781 782 /* Enable host port pre-emphasis during non-chirp phase */ 783 ret = regmap_read(base, 0x8400, &orig); 784 if (ret) 785 return ret; 786 tmp = orig & ~GENMASK(2, 0); 787 tmp |= BIT(2) & GENMASK(2, 0); 788 ret = regmap_write(base, 0x8400, tmp); 789 if (ret) 790 return ret; 791 792 /* Set host port squelch trigger point configure to 100mv */ 793 ret = regmap_read(base, 0x8404, &orig); 794 if (ret) 795 return ret; 796 tmp = orig & ~GENMASK(7, 5); 797 tmp |= 0x40 & GENMASK(7, 5); 798 ret = regmap_write(base, 0x8404, tmp); 799 if (ret) 800 return ret; 801 802 ret = regmap_read(base, 0x8408, &orig); 803 if (ret) 804 return ret; 805 tmp = orig & ~BIT(0); 806 tmp |= 0x1 & BIT(0); 807 ret = regmap_write(base, 0x8408, tmp); 808 if (ret) 809 return ret; 810 } 811 812 return 0; 813 } 814 815 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 816 { 817 struct regmap *base = get_reg_base(rphy); 818 int ret; 819 820 /* Deassert SIDDQ to power on analog block */ 821 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 822 if (ret) 823 return ret; 824 825 /* Do reset after exit IDDQ mode */ 826 ret = rockchip_usb2phy_reset(rphy); 827 if (ret) 828 return ret; 829 830 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 831 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 832 if (ret) 833 return ret; 834 835 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 836 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 837 if (ret) 838 return ret; 839 840 return 0; 841 } 842 843 static struct phy_ops rockchip_usb2phy_ops = { 844 .init = rockchip_usb2phy_init, 845 .exit = rockchip_usb2phy_exit, 846 .power_on = rockchip_usb2phy_power_on, 847 .power_off = rockchip_usb2phy_power_off, 848 .of_xlate = rockchip_usb2phy_of_xlate, 849 }; 850 851 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 852 { 853 .reg = 0x100, 854 .num_ports = 2, 855 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 856 .port_cfgs = { 857 [USB2PHY_PORT_OTG] = { 858 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 859 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 860 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 861 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 862 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 863 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 864 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 865 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 866 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 867 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 868 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 869 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 870 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 871 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 872 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 873 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 874 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 875 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 876 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 877 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 878 }, 879 [USB2PHY_PORT_HOST] = { 880 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 881 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 882 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 883 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 884 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 885 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 886 } 887 }, 888 .chg_det = { 889 .opmode = { 0x0100, 3, 0, 5, 1 }, 890 .cp_det = { 0x0120, 24, 24, 0, 1 }, 891 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 892 .dp_det = { 0x0120, 25, 25, 0, 1 }, 893 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 894 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 895 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 896 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 897 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 898 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 899 }, 900 }, 901 { /* sentinel */ } 902 }; 903 904 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 905 { 906 .reg = 0x17c, 907 .num_ports = 2, 908 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 909 .port_cfgs = { 910 [USB2PHY_PORT_OTG] = { 911 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 912 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 913 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 914 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 915 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 916 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 917 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 918 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 919 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 920 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 921 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 922 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 923 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 924 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 925 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 926 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 927 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 928 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 929 }, 930 [USB2PHY_PORT_HOST] = { 931 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 932 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 933 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 934 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 935 } 936 }, 937 .chg_det = { 938 .opmode = { 0x017c, 3, 0, 5, 1 }, 939 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 940 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 941 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 942 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 943 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 944 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 945 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 946 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 947 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 948 }, 949 }, 950 { /* sentinel */ } 951 }; 952 953 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 954 { 955 .reg = 0x760, 956 .num_ports = 2, 957 .phy_tuning = rk322x_usb2phy_tuning, 958 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 959 .port_cfgs = { 960 [USB2PHY_PORT_OTG] = { 961 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 962 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 963 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 964 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 965 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 966 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 967 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 968 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 969 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 970 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 971 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 972 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 973 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 974 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 975 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 976 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 977 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 978 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 979 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 980 }, 981 [USB2PHY_PORT_HOST] = { 982 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 983 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 984 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 985 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 986 } 987 }, 988 .chg_det = { 989 .opmode = { 0x0760, 3, 0, 5, 1 }, 990 .cp_det = { 0x0884, 4, 4, 0, 1 }, 991 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 992 .dp_det = { 0x0884, 5, 5, 0, 1 }, 993 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 994 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 995 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 996 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 997 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 998 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 999 }, 1000 }, 1001 { 1002 .reg = 0x800, 1003 .num_ports = 2, 1004 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1005 .port_cfgs = { 1006 [USB2PHY_PORT_OTG] = { 1007 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1008 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1009 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1010 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1011 }, 1012 [USB2PHY_PORT_HOST] = { 1013 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1014 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1015 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1016 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1017 } 1018 }, 1019 }, 1020 { /* sentinel */ } 1021 }; 1022 1023 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1024 { 1025 .reg = 0x100, 1026 .num_ports = 2, 1027 .phy_tuning = rk3308_usb2phy_tuning, 1028 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1029 .port_cfgs = { 1030 [USB2PHY_PORT_OTG] = { 1031 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1032 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1033 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1034 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1035 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1036 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1037 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1038 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1039 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1040 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1041 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1042 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1043 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1044 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1045 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1046 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1047 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1048 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1049 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1050 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1051 }, 1052 [USB2PHY_PORT_HOST] = { 1053 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1054 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1055 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1056 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1057 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1058 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1059 } 1060 }, 1061 .chg_det = { 1062 .opmode = { 0x0100, 3, 0, 5, 1 }, 1063 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1064 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1065 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1066 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1067 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1068 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1069 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1070 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1071 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1072 }, 1073 }, 1074 { /* sentinel */ } 1075 }; 1076 1077 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1078 { 1079 .reg = 0x100, 1080 .num_ports = 2, 1081 .phy_tuning = rk3328_usb2phy_tuning, 1082 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1083 .port_cfgs = { 1084 [USB2PHY_PORT_OTG] = { 1085 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1086 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1087 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1088 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1089 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1090 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1091 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1092 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1093 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1094 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1095 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1096 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1097 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1098 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1099 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1100 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1101 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1102 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1103 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1104 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1105 }, 1106 [USB2PHY_PORT_HOST] = { 1107 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1108 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1109 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1110 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1111 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1112 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1113 } 1114 }, 1115 .chg_det = { 1116 .opmode = { 0x0100, 3, 0, 5, 1 }, 1117 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1118 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1119 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1120 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1121 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1122 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1123 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1124 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1125 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1126 }, 1127 }, 1128 { /* sentinel */ } 1129 }; 1130 1131 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1132 { 1133 .reg = 0x700, 1134 .num_ports = 2, 1135 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1136 .port_cfgs = { 1137 [USB2PHY_PORT_OTG] = { 1138 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1139 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1140 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1141 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1142 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1143 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1144 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1145 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1146 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1147 }, 1148 [USB2PHY_PORT_HOST] = { 1149 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1150 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1151 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1152 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1153 } 1154 }, 1155 .chg_det = { 1156 .opmode = { 0x0700, 3, 0, 5, 1 }, 1157 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1158 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1159 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1160 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1161 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1162 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1163 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1164 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1165 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1166 }, 1167 }, 1168 { /* sentinel */ } 1169 }; 1170 1171 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1172 { 1173 .reg = 0xe450, 1174 .num_ports = 2, 1175 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1176 .port_cfgs = { 1177 [USB2PHY_PORT_OTG] = { 1178 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1179 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1180 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1181 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1182 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1183 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1184 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1185 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1186 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1187 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1188 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1189 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1190 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1191 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1192 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1193 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1194 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1195 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1196 }, 1197 [USB2PHY_PORT_HOST] = { 1198 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1199 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1200 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1201 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1202 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1203 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1204 } 1205 }, 1206 .chg_det = { 1207 .opmode = { 0xe454, 3, 0, 5, 1 }, 1208 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1209 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1210 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1211 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1212 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1213 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1214 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1215 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1216 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1217 }, 1218 }, 1219 { 1220 .reg = 0xe460, 1221 .num_ports = 2, 1222 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1223 .port_cfgs = { 1224 [USB2PHY_PORT_OTG] = { 1225 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1226 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1227 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1228 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1229 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1230 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1231 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1232 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1233 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1234 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1235 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1236 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1237 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1238 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1239 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1240 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1241 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1242 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1243 }, 1244 [USB2PHY_PORT_HOST] = { 1245 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1246 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1247 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1248 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1249 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1250 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1251 } 1252 }, 1253 .chg_det = { 1254 .opmode = { 0xe464, 3, 0, 5, 1 }, 1255 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1256 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1257 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1258 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1259 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1260 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1261 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1262 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1263 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1264 }, 1265 }, 1266 { /* sentinel */ } 1267 }; 1268 1269 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1270 { 1271 .reg = 0x100, 1272 .num_ports = 2, 1273 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1274 .port_cfgs = { 1275 [USB2PHY_PORT_OTG] = { 1276 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1277 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1278 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1279 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1280 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1281 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1282 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1283 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1284 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1285 }, 1286 [USB2PHY_PORT_HOST] = { 1287 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1288 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1289 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1290 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1291 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1292 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1293 } 1294 }, 1295 .chg_det = { 1296 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1297 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1298 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1299 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1300 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1301 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1302 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1303 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1304 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1305 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1306 }, 1307 }, 1308 { /* sentinel */ } 1309 }; 1310 1311 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1312 { 1313 .reg = 0xfe8a0000, 1314 .num_ports = 2, 1315 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1316 .port_cfgs = { 1317 [USB2PHY_PORT_OTG] = { 1318 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1319 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1320 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1321 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1322 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1323 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1324 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1325 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1326 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1327 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1328 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1329 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1330 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1331 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1332 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1333 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1334 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1335 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1336 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1337 }, 1338 [USB2PHY_PORT_HOST] = { 1339 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1340 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1341 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1342 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1343 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1344 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1345 } 1346 }, 1347 .chg_det = { 1348 .opmode = { 0x0000, 3, 0, 5, 1 }, 1349 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1350 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1351 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1352 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1353 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1354 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1355 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1356 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1357 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1358 }, 1359 }, 1360 { 1361 .reg = 0xfe8b0000, 1362 .num_ports = 2, 1363 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1364 .port_cfgs = { 1365 [USB2PHY_PORT_OTG] = { 1366 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1367 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1368 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1369 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1370 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1371 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1372 }, 1373 [USB2PHY_PORT_HOST] = { 1374 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1375 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1376 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1377 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1378 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1379 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1380 } 1381 }, 1382 }, 1383 { /* sentinel */ } 1384 }; 1385 1386 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1387 { 1388 .reg = 0x0000, 1389 .num_ports = 1, 1390 .phy_tuning = rk3588_usb2phy_tuning, 1391 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1392 .port_cfgs = { 1393 [USB2PHY_PORT_OTG] = { 1394 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1395 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1396 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1397 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1398 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1399 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1400 } 1401 }, 1402 .chg_det = { 1403 .opmode = { 0x0008, 2, 2, 1, 0 }, 1404 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1405 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1406 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1407 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1408 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1409 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1410 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1411 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1412 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1413 }, 1414 }, 1415 { 1416 .reg = 0x4000, 1417 .num_ports = 1, 1418 .phy_tuning = rk3588_usb2phy_tuning, 1419 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1420 .port_cfgs = { 1421 /* Select suspend control from controller */ 1422 [USB2PHY_PORT_OTG] = { 1423 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1424 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1425 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1426 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1427 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1428 } 1429 }, 1430 }, 1431 { 1432 .reg = 0x8000, 1433 .num_ports = 1, 1434 .phy_tuning = rk3588_usb2phy_tuning, 1435 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1436 .port_cfgs = { 1437 [USB2PHY_PORT_HOST] = { 1438 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1439 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1440 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1441 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1442 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1443 } 1444 }, 1445 }, 1446 { 1447 .reg = 0xc000, 1448 .num_ports = 1, 1449 .phy_tuning = rk3588_usb2phy_tuning, 1450 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1451 .port_cfgs = { 1452 [USB2PHY_PORT_HOST] = { 1453 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1454 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1455 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1456 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1457 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1458 } 1459 }, 1460 }, 1461 { /* sentinel */ } 1462 }; 1463 1464 static const struct udevice_id rockchip_usb2phy_ids[] = { 1465 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1466 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1467 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1468 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1469 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1470 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1471 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1472 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1473 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1474 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1475 { } 1476 }; 1477 1478 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1479 .name = "rockchip_usb2phy_port", 1480 .id = UCLASS_PHY, 1481 .ops = &rockchip_usb2phy_ops, 1482 }; 1483 1484 U_BOOT_DRIVER(rockchip_usb2phy) = { 1485 .name = "rockchip_usb2phy", 1486 .id = UCLASS_PHY, 1487 .of_match = rockchip_usb2phy_ids, 1488 .probe = rockchip_usb2phy_probe, 1489 .bind = rockchip_usb2phy_bind, 1490 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1491 }; 1492