1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <generic-phy.h> 12 #include <usb.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <phys2bus.h> 16 #include <usbroothubdes.h> 17 #include <wait_bit.h> 18 #include <asm/io.h> 19 #include <power/regulator.h> 20 #include <reset.h> 21 22 #include "dwc2.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* Use only HC channel 0. */ 27 #define DWC2_HC_CHANNEL 0 28 29 #define DWC2_STATUS_BUF_SIZE 64 30 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024) 31 32 #define MAX_DEVICE 16 33 #define MAX_ENDPOINT 16 34 35 struct dwc2_priv { 36 #if CONFIG_IS_ENABLED(DM_USB) 37 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 38 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 39 #ifdef CONFIG_DM_REGULATOR 40 struct udevice *vbus_supply; 41 #endif 42 struct phy phy; 43 #else 44 uint8_t *aligned_buffer; 45 uint8_t *status_buffer; 46 #endif 47 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 48 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 49 struct dwc2_core_regs *regs; 50 int root_hub_devnum; 51 bool ext_vbus; 52 /* 53 * The hnp/srp capability must be disabled if the platform 54 * does't support hnp/srp. Otherwise the force mode can't work. 55 */ 56 bool hnp_srp_disable; 57 bool oc_disable; 58 59 struct reset_ctl_bulk resets; 60 }; 61 62 #if !CONFIG_IS_ENABLED(DM_USB) 63 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 64 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 65 ARCH_DMA_MINALIGN); 66 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 67 ARCH_DMA_MINALIGN); 68 69 static struct dwc2_priv local; 70 #endif 71 72 /* 73 * DWC2 IP interface 74 */ 75 76 /* 77 * Initializes the FSLSPClkSel field of the HCFG register 78 * depending on the PHY type. 79 */ 80 static void init_fslspclksel(struct dwc2_core_regs *regs) 81 { 82 uint32_t phyclk; 83 84 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 85 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 86 #else 87 /* High speed PHY running at full speed or high speed */ 88 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 89 #endif 90 91 #ifdef CONFIG_DWC2_ULPI_FS_LS 92 uint32_t hwcfg2 = readl(®s->ghwcfg2); 93 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 94 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 95 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 96 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 97 98 if (hval == 2 && fval == 1) 99 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 100 #endif 101 102 clrsetbits_le32(®s->host_regs.hcfg, 103 DWC2_HCFG_FSLSPCLKSEL_MASK, 104 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 105 } 106 107 /* 108 * Flush a Tx FIFO. 109 * 110 * @param regs Programming view of DWC_otg controller. 111 * @param num Tx FIFO to flush. 112 */ 113 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 114 { 115 int ret; 116 117 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 118 ®s->grstctl); 119 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 120 false, 1000, false); 121 if (ret) 122 dev_info(dev, "%s: Timeout!\n", __func__); 123 124 /* Wait for 3 PHY Clocks */ 125 udelay(1); 126 } 127 128 /* 129 * Flush Rx FIFO. 130 * 131 * @param regs Programming view of DWC_otg controller. 132 */ 133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 134 { 135 int ret; 136 137 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 138 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 139 false, 1000, false); 140 if (ret) 141 dev_info(dev, "%s: Timeout!\n", __func__); 142 143 /* Wait for 3 PHY Clocks */ 144 udelay(1); 145 } 146 147 /* 148 * Do core a soft reset of the core. Be careful with this because it 149 * resets all the internal state machines of the core. 150 */ 151 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 152 { 153 int ret; 154 155 /* Wait for AHB master IDLE state. */ 156 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 157 true, 1000, false); 158 if (ret) 159 dev_info(dev, "%s: Timeout!\n", __func__); 160 161 /* Core Soft Reset */ 162 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 163 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 164 false, 1000, false); 165 if (ret) 166 dev_info(dev, "%s: Timeout!\n", __func__); 167 168 /* 169 * Wait for core to come out of reset. 170 * NOTE: This long sleep is _very_ important, otherwise the core will 171 * not stay in host mode after a connector ID change! 172 */ 173 mdelay(100); 174 } 175 176 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR) 177 static int dwc_vbus_supply_init(struct udevice *dev) 178 { 179 struct dwc2_priv *priv = dev_get_priv(dev); 180 int ret; 181 182 ret = device_get_supply_regulator(dev, "vbus-supply", 183 &priv->vbus_supply); 184 if (ret) { 185 debug("%s: No vbus supply\n", dev->name); 186 return 0; 187 } 188 189 ret = regulator_set_enable(priv->vbus_supply, true); 190 if (ret) { 191 dev_err(dev, "Error enabling vbus supply\n"); 192 return ret; 193 } 194 195 return 0; 196 } 197 198 static int dwc_vbus_supply_exit(struct udevice *dev) 199 { 200 struct dwc2_priv *priv = dev_get_priv(dev); 201 int ret; 202 203 if (priv->vbus_supply) { 204 ret = regulator_set_enable(priv->vbus_supply, false); 205 if (ret) { 206 dev_err(dev, "Error disabling vbus supply\n"); 207 return ret; 208 } 209 } 210 211 return 0; 212 } 213 #else 214 static int dwc_vbus_supply_init(struct udevice *dev) 215 { 216 return 0; 217 } 218 219 #if CONFIG_IS_ENABLED(DM_USB) 220 static int dwc_vbus_supply_exit(struct udevice *dev) 221 { 222 return 0; 223 } 224 #endif 225 #endif 226 227 /* 228 * This function initializes the DWC_otg controller registers for 229 * host mode. 230 * 231 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 232 * request queues. Host channels are reset to ensure that they are ready for 233 * performing transfers. 234 * 235 * @param dev USB Device (NULL if driver model is not being used) 236 * @param regs Programming view of DWC_otg controller 237 * 238 */ 239 static void dwc_otg_core_host_init(struct udevice *dev, 240 struct dwc2_core_regs *regs) 241 { 242 uint32_t nptxfifosize = 0; 243 uint32_t ptxfifosize = 0; 244 uint32_t hprt0 = 0; 245 int i, ret, num_channels; 246 247 /* Restart the Phy Clock */ 248 writel(0, ®s->pcgcctl); 249 250 /* Initialize Host Configuration Register */ 251 init_fslspclksel(regs); 252 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 253 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 254 #endif 255 256 /* Configure data FIFO sizes */ 257 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 258 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 259 /* Rx FIFO */ 260 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 261 262 /* Non-periodic Tx FIFO */ 263 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 264 DWC2_FIFOSIZE_DEPTH_OFFSET; 265 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 266 DWC2_FIFOSIZE_STARTADDR_OFFSET; 267 writel(nptxfifosize, ®s->gnptxfsiz); 268 269 /* Periodic Tx FIFO */ 270 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 271 DWC2_FIFOSIZE_DEPTH_OFFSET; 272 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 273 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 274 DWC2_FIFOSIZE_STARTADDR_OFFSET; 275 writel(ptxfifosize, ®s->hptxfsiz); 276 } 277 #endif 278 279 /* Clear Host Set HNP Enable in the OTG Control Register */ 280 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 281 282 /* Make sure the FIFOs are flushed. */ 283 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 284 dwc_otg_flush_rx_fifo(regs); 285 286 /* Flush out any leftover queued requests. */ 287 num_channels = readl(®s->ghwcfg2); 288 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 289 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 290 num_channels += 1; 291 292 for (i = 0; i < num_channels; i++) 293 clrsetbits_le32(®s->hc_regs[i].hcchar, 294 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 295 DWC2_HCCHAR_CHDIS); 296 297 /* Halt all channels to put them into a known state. */ 298 for (i = 0; i < num_channels; i++) { 299 clrsetbits_le32(®s->hc_regs[i].hcchar, 300 DWC2_HCCHAR_EPDIR, 301 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 302 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar, 303 DWC2_HCCHAR_CHEN, false, 1000, false); 304 if (ret) 305 dev_info("%s: Timeout!\n", __func__); 306 } 307 308 /* Turn on the vbus power. */ 309 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 310 hprt0 = readl(®s->hprt0); 311 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 312 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 313 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 314 hprt0 |= DWC2_HPRT0_PRTPWR; 315 writel(hprt0, ®s->hprt0); 316 } 317 } 318 319 if (dev) 320 dwc_vbus_supply_init(dev); 321 } 322 323 /* 324 * This function initializes the DWC_otg controller registers and 325 * prepares the core for device mode or host mode operation. 326 * 327 * @param regs Programming view of the DWC_otg controller 328 */ 329 static void dwc_otg_core_init(struct dwc2_priv *priv) 330 { 331 struct dwc2_core_regs *regs = priv->regs; 332 uint32_t ahbcfg = 0; 333 uint32_t usbcfg = 0; 334 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 335 336 /* Common Initialization */ 337 usbcfg = readl(®s->gusbcfg); 338 339 /* Program the ULPI External VBUS bit if needed */ 340 if (priv->ext_vbus) { 341 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 342 if (!priv->oc_disable) { 343 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 344 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; 345 } 346 } else { 347 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 348 } 349 350 /* Set external TS Dline pulsing */ 351 #ifdef CONFIG_DWC2_TS_DLINE 352 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 353 #else 354 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 355 #endif 356 writel(usbcfg, ®s->gusbcfg); 357 358 /* Reset the Controller */ 359 dwc_otg_core_reset(regs); 360 361 /* 362 * This programming sequence needs to happen in FS mode before 363 * any other programming occurs 364 */ 365 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 366 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 367 /* If FS mode with FS PHY */ 368 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 369 370 /* Reset after a PHY select */ 371 dwc_otg_core_reset(regs); 372 373 /* 374 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 375 * Also do this on HNP Dev/Host mode switches (done in dev_init 376 * and host_init). 377 */ 378 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 379 init_fslspclksel(regs); 380 381 #ifdef CONFIG_DWC2_I2C_ENABLE 382 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 383 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 384 385 /* Program GI2CCTL.I2CEn */ 386 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 387 DWC2_GI2CCTL_I2CDEVADDR_MASK, 388 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 389 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 390 #endif 391 392 #else 393 /* High speed PHY. */ 394 395 /* 396 * HS PHY parameters. These parameters are preserved during 397 * soft reset so only program the first time. Do a soft reset 398 * immediately after setting phyif. 399 */ 400 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 401 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 402 403 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 404 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 405 usbcfg |= DWC2_GUSBCFG_DDRSEL; 406 #else 407 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 408 #endif 409 } else { /* UTMI+ interface */ 410 #if (CONFIG_DWC2_UTMI_WIDTH == 16) 411 usbcfg |= DWC2_GUSBCFG_PHYIF; 412 #endif 413 } 414 415 writel(usbcfg, ®s->gusbcfg); 416 417 /* Reset after setting the PHY parameters */ 418 dwc_otg_core_reset(regs); 419 #endif 420 421 usbcfg = readl(®s->gusbcfg); 422 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 423 #ifdef CONFIG_DWC2_ULPI_FS_LS 424 uint32_t hwcfg2 = readl(®s->ghwcfg2); 425 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 426 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 427 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 428 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 429 if (hval == 2 && fval == 1) { 430 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 431 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 432 } 433 #endif 434 if (priv->hnp_srp_disable) 435 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; 436 437 writel(usbcfg, ®s->gusbcfg); 438 439 /* Program the GAHBCFG Register. */ 440 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 441 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 442 break; 443 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 444 while (brst_sz > 1) { 445 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 446 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 447 brst_sz >>= 1; 448 } 449 450 #ifdef CONFIG_DWC2_DMA_ENABLE 451 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 452 #endif 453 break; 454 455 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 456 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 457 #ifdef CONFIG_DWC2_DMA_ENABLE 458 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 459 #endif 460 break; 461 } 462 463 writel(ahbcfg, ®s->gahbcfg); 464 465 /* Program the capabilities in GUSBCFG Register */ 466 usbcfg = 0; 467 468 if (!priv->hnp_srp_disable) 469 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; 470 #ifdef CONFIG_DWC2_IC_USB_CAP 471 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; 472 #endif 473 474 setbits_le32(®s->gusbcfg, usbcfg); 475 } 476 477 /* 478 * Prepares a host channel for transferring packets to/from a specific 479 * endpoint. The HCCHARn register is set up with the characteristics specified 480 * in _hc. Host channel interrupts that may need to be serviced while this 481 * transfer is in progress are enabled. 482 * 483 * @param regs Programming view of DWC_otg controller 484 * @param hc Information needed to initialize the host channel 485 */ 486 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 487 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 488 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 489 { 490 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 491 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 492 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 493 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 494 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 495 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 496 497 if (dev->speed == USB_SPEED_LOW) 498 hcchar |= DWC2_HCCHAR_LSPDDEV; 499 500 /* 501 * Program the HCCHARn register with the endpoint characteristics 502 * for the current transfer. 503 */ 504 writel(hcchar, &hc_regs->hcchar); 505 506 /* Program the HCSPLIT register, default to no SPLIT */ 507 writel(0, &hc_regs->hcsplt); 508 } 509 510 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 511 uint8_t hub_devnum, uint8_t hub_port) 512 { 513 uint32_t hcsplt = 0; 514 515 hcsplt = DWC2_HCSPLT_SPLTENA; 516 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 517 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 518 519 /* Program the HCSPLIT register for SPLITs */ 520 writel(hcsplt, &hc_regs->hcsplt); 521 } 522 523 /* 524 * DWC2 to USB API interface 525 */ 526 /* Direction: In ; Request: Status */ 527 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 528 struct usb_device *dev, void *buffer, 529 int txlen, struct devrequest *cmd) 530 { 531 uint32_t hprt0 = 0; 532 uint32_t port_status = 0; 533 uint32_t port_change = 0; 534 int len = 0; 535 int stat = 0; 536 537 switch (cmd->requesttype & ~USB_DIR_IN) { 538 case 0: 539 *(uint16_t *)buffer = cpu_to_le16(1); 540 len = 2; 541 break; 542 case USB_RECIP_INTERFACE: 543 case USB_RECIP_ENDPOINT: 544 *(uint16_t *)buffer = cpu_to_le16(0); 545 len = 2; 546 break; 547 case USB_TYPE_CLASS: 548 *(uint32_t *)buffer = cpu_to_le32(0); 549 len = 4; 550 break; 551 case USB_RECIP_OTHER | USB_TYPE_CLASS: 552 hprt0 = readl(®s->hprt0); 553 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 554 port_status |= USB_PORT_STAT_CONNECTION; 555 if (hprt0 & DWC2_HPRT0_PRTENA) 556 port_status |= USB_PORT_STAT_ENABLE; 557 if (hprt0 & DWC2_HPRT0_PRTSUSP) 558 port_status |= USB_PORT_STAT_SUSPEND; 559 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 560 port_status |= USB_PORT_STAT_OVERCURRENT; 561 if (hprt0 & DWC2_HPRT0_PRTRST) 562 port_status |= USB_PORT_STAT_RESET; 563 if (hprt0 & DWC2_HPRT0_PRTPWR) 564 port_status |= USB_PORT_STAT_POWER; 565 566 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 567 port_status |= USB_PORT_STAT_LOW_SPEED; 568 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 569 DWC2_HPRT0_PRTSPD_HIGH) 570 port_status |= USB_PORT_STAT_HIGH_SPEED; 571 572 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 573 port_change |= USB_PORT_STAT_C_ENABLE; 574 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 575 port_change |= USB_PORT_STAT_C_CONNECTION; 576 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 577 port_change |= USB_PORT_STAT_C_OVERCURRENT; 578 579 *(uint32_t *)buffer = cpu_to_le32(port_status | 580 (port_change << 16)); 581 len = 4; 582 break; 583 default: 584 puts("unsupported root hub command\n"); 585 stat = USB_ST_STALLED; 586 } 587 588 dev->act_len = min(len, txlen); 589 dev->status = stat; 590 591 return stat; 592 } 593 594 /* Direction: In ; Request: Descriptor */ 595 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 596 void *buffer, int txlen, 597 struct devrequest *cmd) 598 { 599 unsigned char data[32]; 600 uint32_t dsc; 601 int len = 0; 602 int stat = 0; 603 uint16_t wValue = cpu_to_le16(cmd->value); 604 uint16_t wLength = cpu_to_le16(cmd->length); 605 606 switch (cmd->requesttype & ~USB_DIR_IN) { 607 case 0: 608 switch (wValue & 0xff00) { 609 case 0x0100: /* device descriptor */ 610 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 611 memcpy(buffer, root_hub_dev_des, len); 612 break; 613 case 0x0200: /* configuration descriptor */ 614 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 615 memcpy(buffer, root_hub_config_des, len); 616 break; 617 case 0x0300: /* string descriptors */ 618 switch (wValue & 0xff) { 619 case 0x00: 620 len = min3(txlen, (int)sizeof(root_hub_str_index0), 621 (int)wLength); 622 memcpy(buffer, root_hub_str_index0, len); 623 break; 624 case 0x01: 625 len = min3(txlen, (int)sizeof(root_hub_str_index1), 626 (int)wLength); 627 memcpy(buffer, root_hub_str_index1, len); 628 break; 629 } 630 break; 631 default: 632 stat = USB_ST_STALLED; 633 } 634 break; 635 636 case USB_TYPE_CLASS: 637 /* Root port config, set 1 port and nothing else. */ 638 dsc = 0x00000001; 639 640 data[0] = 9; /* min length; */ 641 data[1] = 0x29; 642 data[2] = dsc & RH_A_NDP; 643 data[3] = 0; 644 if (dsc & RH_A_PSM) 645 data[3] |= 0x1; 646 if (dsc & RH_A_NOCP) 647 data[3] |= 0x10; 648 else if (dsc & RH_A_OCPM) 649 data[3] |= 0x8; 650 651 /* corresponds to data[4-7] */ 652 data[5] = (dsc & RH_A_POTPGT) >> 24; 653 data[7] = dsc & RH_B_DR; 654 if (data[2] < 7) { 655 data[8] = 0xff; 656 } else { 657 data[0] += 2; 658 data[8] = (dsc & RH_B_DR) >> 8; 659 data[9] = 0xff; 660 data[10] = data[9]; 661 } 662 663 len = min3(txlen, (int)data[0], (int)wLength); 664 memcpy(buffer, data, len); 665 break; 666 default: 667 puts("unsupported root hub command\n"); 668 stat = USB_ST_STALLED; 669 } 670 671 dev->act_len = min(len, txlen); 672 dev->status = stat; 673 674 return stat; 675 } 676 677 /* Direction: In ; Request: Configuration */ 678 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 679 void *buffer, int txlen, 680 struct devrequest *cmd) 681 { 682 int len = 0; 683 int stat = 0; 684 685 switch (cmd->requesttype & ~USB_DIR_IN) { 686 case 0: 687 *(uint8_t *)buffer = 0x01; 688 len = 1; 689 break; 690 default: 691 puts("unsupported root hub command\n"); 692 stat = USB_ST_STALLED; 693 } 694 695 dev->act_len = min(len, txlen); 696 dev->status = stat; 697 698 return stat; 699 } 700 701 /* Direction: In */ 702 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 703 struct usb_device *dev, void *buffer, 704 int txlen, struct devrequest *cmd) 705 { 706 switch (cmd->request) { 707 case USB_REQ_GET_STATUS: 708 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 709 txlen, cmd); 710 case USB_REQ_GET_DESCRIPTOR: 711 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 712 txlen, cmd); 713 case USB_REQ_GET_CONFIGURATION: 714 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 715 txlen, cmd); 716 default: 717 puts("unsupported root hub command\n"); 718 return USB_ST_STALLED; 719 } 720 } 721 722 /* Direction: Out */ 723 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 724 struct usb_device *dev, 725 void *buffer, int txlen, 726 struct devrequest *cmd) 727 { 728 struct dwc2_core_regs *regs = priv->regs; 729 int len = 0; 730 int stat = 0; 731 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 732 uint16_t wValue = cpu_to_le16(cmd->value); 733 734 switch (bmrtype_breq & ~USB_DIR_IN) { 735 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 736 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 737 break; 738 739 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 740 switch (wValue) { 741 case USB_PORT_FEAT_C_CONNECTION: 742 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 743 break; 744 } 745 break; 746 747 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 748 switch (wValue) { 749 case USB_PORT_FEAT_SUSPEND: 750 break; 751 752 case USB_PORT_FEAT_RESET: 753 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 754 DWC2_HPRT0_PRTCONNDET | 755 DWC2_HPRT0_PRTENCHNG | 756 DWC2_HPRT0_PRTOVRCURRCHNG, 757 DWC2_HPRT0_PRTRST); 758 mdelay(50); 759 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 760 break; 761 762 case USB_PORT_FEAT_POWER: 763 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 764 DWC2_HPRT0_PRTCONNDET | 765 DWC2_HPRT0_PRTENCHNG | 766 DWC2_HPRT0_PRTOVRCURRCHNG, 767 DWC2_HPRT0_PRTRST); 768 break; 769 770 case USB_PORT_FEAT_ENABLE: 771 break; 772 } 773 break; 774 case (USB_REQ_SET_ADDRESS << 8): 775 priv->root_hub_devnum = wValue; 776 break; 777 case (USB_REQ_SET_CONFIGURATION << 8): 778 break; 779 default: 780 puts("unsupported root hub command\n"); 781 stat = USB_ST_STALLED; 782 } 783 784 len = min(len, txlen); 785 786 dev->act_len = len; 787 dev->status = stat; 788 789 return stat; 790 } 791 792 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 793 unsigned long pipe, void *buffer, int txlen, 794 struct devrequest *cmd) 795 { 796 int stat = 0; 797 798 if (usb_pipeint(pipe)) { 799 puts("Root-Hub submit IRQ: NOT implemented\n"); 800 return 0; 801 } 802 803 if (cmd->requesttype & USB_DIR_IN) 804 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 805 else 806 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 807 808 mdelay(1); 809 810 return stat; 811 } 812 813 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 814 { 815 int ret; 816 uint32_t hcint, hctsiz; 817 818 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 819 2000, false); 820 if (ret) 821 return ret; 822 823 hcint = readl(&hc_regs->hcint); 824 hctsiz = readl(&hc_regs->hctsiz); 825 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 826 DWC2_HCTSIZ_XFERSIZE_OFFSET; 827 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 828 829 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 830 *toggle); 831 832 if (hcint & DWC2_HCINT_XFERCOMP) 833 return 0; 834 835 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 836 return -EAGAIN; 837 838 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 839 return -EINVAL; 840 } 841 842 static int dwc2_eptype[] = { 843 DWC2_HCCHAR_EPTYPE_ISOC, 844 DWC2_HCCHAR_EPTYPE_INTR, 845 DWC2_HCCHAR_EPTYPE_CONTROL, 846 DWC2_HCCHAR_EPTYPE_BULK, 847 }; 848 849 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 850 u8 *pid, int in, void *buffer, int num_packets, 851 int xfer_len, int *actual_len, int odd_frame) 852 { 853 int ret = 0; 854 uint32_t sub; 855 856 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 857 *pid, xfer_len, num_packets); 858 859 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 860 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 861 (*pid << DWC2_HCTSIZ_PID_OFFSET), 862 &hc_regs->hctsiz); 863 864 if (xfer_len) { 865 if (in) { 866 invalidate_dcache_range( 867 (uintptr_t)aligned_buffer, 868 (uintptr_t)aligned_buffer + 869 roundup(xfer_len, ARCH_DMA_MINALIGN)); 870 } else { 871 memcpy(aligned_buffer, buffer, xfer_len); 872 flush_dcache_range( 873 (uintptr_t)aligned_buffer, 874 (uintptr_t)aligned_buffer + 875 roundup(xfer_len, ARCH_DMA_MINALIGN)); 876 } 877 } 878 879 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 880 881 /* Clear old interrupt conditions for this host channel. */ 882 writel(0x3fff, &hc_regs->hcint); 883 884 /* Set host channel enable after all other setup is complete. */ 885 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 886 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 887 DWC2_HCCHAR_ODDFRM, 888 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 889 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 890 DWC2_HCCHAR_CHEN); 891 892 ret = wait_for_chhltd(hc_regs, &sub, pid); 893 if (ret < 0) 894 return ret; 895 896 if (in) { 897 xfer_len -= sub; 898 899 invalidate_dcache_range((unsigned long)aligned_buffer, 900 (unsigned long)aligned_buffer + 901 roundup(xfer_len, ARCH_DMA_MINALIGN)); 902 903 memcpy(buffer, aligned_buffer, xfer_len); 904 } 905 *actual_len = xfer_len; 906 907 return ret; 908 } 909 910 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 911 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 912 { 913 struct dwc2_core_regs *regs = priv->regs; 914 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 915 struct dwc2_host_regs *host_regs = ®s->host_regs; 916 int devnum = usb_pipedevice(pipe); 917 int ep = usb_pipeendpoint(pipe); 918 int max = usb_maxpacket(dev, pipe); 919 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 920 int done = 0; 921 int ret = 0; 922 int do_split = 0; 923 int complete_split = 0; 924 uint32_t xfer_len; 925 uint32_t num_packets; 926 int stop_transfer = 0; 927 uint32_t max_xfer_len; 928 int ssplit_frame_num = 0; 929 930 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 931 in, len); 932 933 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 934 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 935 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 936 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 937 max_xfer_len = DWC2_DATA_BUF_SIZE; 938 939 /* Make sure that max_xfer_len is a multiple of max packet size. */ 940 num_packets = max_xfer_len / max; 941 max_xfer_len = num_packets * max; 942 943 /* Initialize channel */ 944 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 945 eptype, max); 946 947 /* Check if the target is a FS/LS device behind a HS hub */ 948 if (dev->speed != USB_SPEED_HIGH) { 949 uint8_t hub_addr; 950 uint8_t hub_port; 951 uint32_t hprt0 = readl(®s->hprt0); 952 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 953 DWC2_HPRT0_PRTSPD_HIGH) { 954 usb_find_usb2_hub_address_port(dev, &hub_addr, 955 &hub_port); 956 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 957 958 do_split = 1; 959 num_packets = 1; 960 max_xfer_len = max; 961 } 962 } 963 964 do { 965 int actual_len = 0; 966 uint32_t hcint; 967 int odd_frame = 0; 968 xfer_len = len - done; 969 970 if (xfer_len > max_xfer_len) 971 xfer_len = max_xfer_len; 972 else if (xfer_len > max) 973 num_packets = (xfer_len + max - 1) / max; 974 else 975 num_packets = 1; 976 977 if (complete_split) 978 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 979 else if (do_split) 980 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 981 982 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 983 int uframe_num = readl(&host_regs->hfnum); 984 if (!(uframe_num & 0x1)) 985 odd_frame = 1; 986 } 987 988 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 989 in, (char *)buffer + done, num_packets, 990 xfer_len, &actual_len, odd_frame); 991 992 hcint = readl(&hc_regs->hcint); 993 if (complete_split) { 994 stop_transfer = 0; 995 if (hcint & DWC2_HCINT_NYET) { 996 ret = 0; 997 int frame_num = DWC2_HFNUM_MAX_FRNUM & 998 readl(&host_regs->hfnum); 999 if (((frame_num - ssplit_frame_num) & 1000 DWC2_HFNUM_MAX_FRNUM) > 4) 1001 ret = -EAGAIN; 1002 } else 1003 complete_split = 0; 1004 } else if (do_split) { 1005 if (hcint & DWC2_HCINT_ACK) { 1006 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 1007 readl(&host_regs->hfnum); 1008 ret = 0; 1009 complete_split = 1; 1010 } 1011 } 1012 1013 if (ret) 1014 break; 1015 1016 if (actual_len < xfer_len) 1017 stop_transfer = 1; 1018 1019 done += actual_len; 1020 1021 /* Transactions are done when when either all data is transferred or 1022 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 1023 * is executed. 1024 */ 1025 } while (((done < len) && !stop_transfer) || complete_split); 1026 1027 writel(0, &hc_regs->hcintmsk); 1028 writel(0xFFFFFFFF, &hc_regs->hcint); 1029 1030 dev->status = 0; 1031 dev->act_len = done; 1032 1033 return ret; 1034 } 1035 1036 /* U-Boot USB transmission interface */ 1037 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 1038 unsigned long pipe, void *buffer, int len) 1039 { 1040 int devnum = usb_pipedevice(pipe); 1041 int ep = usb_pipeendpoint(pipe); 1042 u8* pid; 1043 1044 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 1045 dev->status = 0; 1046 return -EINVAL; 1047 } 1048 1049 if (usb_pipein(pipe)) 1050 pid = &priv->in_data_toggle[devnum][ep]; 1051 else 1052 pid = &priv->out_data_toggle[devnum][ep]; 1053 1054 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 1055 } 1056 1057 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 1058 unsigned long pipe, void *buffer, int len, 1059 struct devrequest *setup) 1060 { 1061 int devnum = usb_pipedevice(pipe); 1062 int ret, act_len; 1063 u8 pid; 1064 /* For CONTROL endpoint pid should start with DATA1 */ 1065 int status_direction; 1066 1067 if (devnum == priv->root_hub_devnum) { 1068 dev->status = 0; 1069 dev->speed = USB_SPEED_HIGH; 1070 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 1071 setup); 1072 } 1073 1074 /* SETUP stage */ 1075 pid = DWC2_HC_PID_SETUP; 1076 do { 1077 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 1078 } while (ret == -EAGAIN); 1079 if (ret) 1080 return ret; 1081 1082 /* DATA stage */ 1083 act_len = 0; 1084 if (buffer) { 1085 pid = DWC2_HC_PID_DATA1; 1086 do { 1087 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1088 buffer, len); 1089 act_len += dev->act_len; 1090 buffer += dev->act_len; 1091 len -= dev->act_len; 1092 } while (ret == -EAGAIN); 1093 if (ret) 1094 return ret; 1095 status_direction = usb_pipeout(pipe); 1096 } else { 1097 /* No-data CONTROL always ends with an IN transaction */ 1098 status_direction = 1; 1099 } 1100 1101 /* STATUS stage */ 1102 pid = DWC2_HC_PID_DATA1; 1103 do { 1104 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1105 priv->status_buffer, 0); 1106 } while (ret == -EAGAIN); 1107 if (ret) 1108 return ret; 1109 1110 dev->act_len = act_len; 1111 1112 return 0; 1113 } 1114 1115 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1116 unsigned long pipe, void *buffer, int len, int interval, 1117 bool nonblock) 1118 { 1119 unsigned long timeout; 1120 int ret; 1121 1122 /* FIXME: what is interval? */ 1123 1124 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1125 for (;;) { 1126 if (get_timer(0) > timeout) { 1127 dev_err(dev, "Timeout poll on interrupt endpoint\n"); 1128 return -ETIMEDOUT; 1129 } 1130 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1131 if ((ret != -EAGAIN) || nonblock) 1132 return ret; 1133 } 1134 } 1135 1136 static int dwc2_reset(struct udevice *dev) 1137 { 1138 int ret; 1139 struct dwc2_priv *priv = dev_get_priv(dev); 1140 1141 ret = reset_get_bulk(dev, &priv->resets); 1142 if (ret) { 1143 dev_warn(dev, "Can't get reset: %d\n", ret); 1144 /* Return 0 if error due to !CONFIG_DM_RESET and reset 1145 * DT property is not present. 1146 */ 1147 if (ret == -ENOENT || ret == -ENOTSUPP) 1148 return 0; 1149 else 1150 return ret; 1151 } 1152 1153 ret = reset_deassert_bulk(&priv->resets); 1154 if (ret) { 1155 reset_release_bulk(&priv->resets); 1156 dev_err(dev, "Failed to reset: %d\n", ret); 1157 return ret; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) 1164 { 1165 struct dwc2_core_regs *regs = priv->regs; 1166 uint32_t snpsid; 1167 int i, j; 1168 int ret; 1169 1170 ret = dwc2_reset(dev); 1171 if (ret) 1172 return ret; 1173 1174 snpsid = readl(®s->gsnpsid); 1175 dev_info(dev, "Core Release: %x.%03x\n", 1176 snpsid >> 12 & 0xf, snpsid & 0xfff); 1177 1178 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1179 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1180 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", 1181 snpsid); 1182 return -ENODEV; 1183 } 1184 1185 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1186 priv->ext_vbus = 1; 1187 #else 1188 priv->ext_vbus = 0; 1189 #endif 1190 1191 dwc_otg_core_init(priv); 1192 dwc_otg_core_host_init(dev, regs); 1193 1194 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1195 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1196 DWC2_HPRT0_PRTOVRCURRCHNG, 1197 DWC2_HPRT0_PRTRST); 1198 mdelay(50); 1199 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1200 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1201 DWC2_HPRT0_PRTRST); 1202 1203 for (i = 0; i < MAX_DEVICE; i++) { 1204 for (j = 0; j < MAX_ENDPOINT; j++) { 1205 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1206 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1207 } 1208 } 1209 1210 /* 1211 * Add a 1 second delay here. This gives the host controller 1212 * a bit time before the comminucation with the USB devices 1213 * is started (the bus is scanned) and fixes the USB detection 1214 * problems with some problematic USB keys. 1215 */ 1216 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 1217 mdelay(1000); 1218 1219 return 0; 1220 } 1221 1222 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1223 { 1224 /* Put everything in reset. */ 1225 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1226 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1227 DWC2_HPRT0_PRTOVRCURRCHNG, 1228 DWC2_HPRT0_PRTRST); 1229 } 1230 1231 #if !CONFIG_IS_ENABLED(DM_USB) 1232 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1233 int len, struct devrequest *setup) 1234 { 1235 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1236 } 1237 1238 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1239 int len) 1240 { 1241 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1242 } 1243 1244 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1245 int len, int interval, bool nonblock) 1246 { 1247 return _submit_int_msg(&local, dev, pipe, buffer, len, interval, 1248 nonblock); 1249 } 1250 1251 /* U-Boot USB control interface */ 1252 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1253 { 1254 struct dwc2_priv *priv = &local; 1255 1256 memset(priv, '\0', sizeof(*priv)); 1257 priv->root_hub_devnum = 0; 1258 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1259 priv->aligned_buffer = aligned_buffer_addr; 1260 priv->status_buffer = status_buffer_addr; 1261 1262 /* board-dependant init */ 1263 if (board_usb_init(index, USB_INIT_HOST)) 1264 return -1; 1265 1266 return dwc2_init_common(NULL, priv); 1267 } 1268 1269 int usb_lowlevel_stop(int index) 1270 { 1271 dwc2_uninit_common(local.regs); 1272 1273 return 0; 1274 } 1275 #endif 1276 1277 #if CONFIG_IS_ENABLED(DM_USB) 1278 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1279 unsigned long pipe, void *buffer, int length, 1280 struct devrequest *setup) 1281 { 1282 struct dwc2_priv *priv = dev_get_priv(dev); 1283 1284 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1285 dev->name, udev, udev->dev->name, udev->portnr); 1286 1287 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1288 } 1289 1290 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1291 unsigned long pipe, void *buffer, int length) 1292 { 1293 struct dwc2_priv *priv = dev_get_priv(dev); 1294 1295 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1296 1297 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1298 } 1299 1300 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1301 unsigned long pipe, void *buffer, int length, 1302 int interval, bool nonblock) 1303 { 1304 struct dwc2_priv *priv = dev_get_priv(dev); 1305 1306 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1307 1308 return _submit_int_msg(priv, udev, pipe, buffer, length, interval, 1309 nonblock); 1310 } 1311 1312 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1313 { 1314 struct dwc2_priv *priv = dev_get_priv(dev); 1315 fdt_addr_t addr; 1316 1317 addr = dev_read_addr(dev); 1318 if (addr == FDT_ADDR_T_NONE) 1319 return -EINVAL; 1320 priv->regs = (struct dwc2_core_regs *)addr; 1321 1322 priv->oc_disable = dev_read_bool(dev, "disable-over-current"); 1323 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); 1324 1325 return 0; 1326 } 1327 1328 static int dwc2_setup_phy(struct udevice *dev) 1329 { 1330 struct dwc2_priv *priv = dev_get_priv(dev); 1331 int ret; 1332 1333 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 1334 if (ret) { 1335 if (ret == -ENOENT) 1336 return 0; /* no PHY, nothing to do */ 1337 dev_err(dev, "Failed to get USB PHY: %d.\n", ret); 1338 return ret; 1339 } 1340 1341 ret = generic_phy_init(&priv->phy); 1342 if (ret) { 1343 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret); 1344 return ret; 1345 } 1346 1347 ret = generic_phy_power_on(&priv->phy); 1348 if (ret) { 1349 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret); 1350 generic_phy_exit(&priv->phy); 1351 return ret; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static int dwc2_shutdown_phy(struct udevice *dev) 1358 { 1359 struct dwc2_priv *priv = dev_get_priv(dev); 1360 int ret; 1361 1362 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */ 1363 if (!generic_phy_valid(&priv->phy)) 1364 return 0; /* no PHY, nothing to do */ 1365 1366 ret = generic_phy_power_off(&priv->phy); 1367 if (ret) { 1368 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1369 return ret; 1370 } 1371 1372 ret = generic_phy_exit(&priv->phy); 1373 if (ret) { 1374 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1375 return ret; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int dwc2_usb_probe(struct udevice *dev) 1382 { 1383 struct dwc2_priv *priv = dev_get_priv(dev); 1384 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); 1385 int ret; 1386 1387 bus_priv->desc_before_addr = true; 1388 1389 #ifdef CONFIG_ARCH_ROCKCHIP 1390 priv->hnp_srp_disable = true; 1391 #endif 1392 1393 ret = dwc2_setup_phy(dev); 1394 if (ret) 1395 return ret; 1396 1397 return dwc2_init_common(dev, priv); 1398 } 1399 1400 static int dwc2_usb_remove(struct udevice *dev) 1401 { 1402 struct dwc2_priv *priv = dev_get_priv(dev); 1403 int ret; 1404 1405 ret = dwc_vbus_supply_exit(dev); 1406 if (ret) 1407 return ret; 1408 1409 ret = dwc2_shutdown_phy(dev); 1410 if (ret) { 1411 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret); 1412 return ret; 1413 } 1414 1415 dwc2_uninit_common(priv->regs); 1416 1417 reset_release_bulk(&priv->resets); 1418 1419 return 0; 1420 } 1421 1422 struct dm_usb_ops dwc2_usb_ops = { 1423 .control = dwc2_submit_control_msg, 1424 .bulk = dwc2_submit_bulk_msg, 1425 .interrupt = dwc2_submit_int_msg, 1426 }; 1427 1428 static const struct udevice_id dwc2_usb_ids[] = { 1429 { .compatible = "brcm,bcm2835-usb" }, 1430 { .compatible = "brcm,bcm2708-usb" }, 1431 { .compatible = "snps,dwc2" }, 1432 { } 1433 }; 1434 1435 U_BOOT_DRIVER(usb_dwc2) = { 1436 .name = "dwc2_usb", 1437 .id = UCLASS_USB, 1438 .of_match = dwc2_usb_ids, 1439 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1440 .probe = dwc2_usb_probe, 1441 .remove = dwc2_usb_remove, 1442 .ops = &dwc2_usb_ops, 1443 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1444 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1445 }; 1446 #endif 1447