Merge branch 'master' of git://www.denx.de/git/u-boot-imx

ARM: AM437X: Add Silicon ID support

Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to

ARM: AM437X: Add Silicon ID support

Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to be consistent
with other OMAP platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: vf610: use strcpy for soc environment variable

To create the soc environment variable we concatenate two strings
on the stack. So far, strcat has been used for the first string as
well as for t

ARM: vf610: use strcpy for soc environment variable

To create the soc environment variable we concatenate two strings
on the stack. So far, strcat has been used for the first string as
well as for the second string. Since the variable on the stack is
not initialized, the first strcat may not start using the first
entry in the character array. This then could lead to an buffer
overflow on the stack.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

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ARM: OMAP5+: Override switch_to_hypervisor function

Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the b

ARM: OMAP5+: Override switch_to_hypervisor function

Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.

Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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ARM: Introduce function to switch to hypervisor mode

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jum

ARM: Introduce function to switch to hypervisor mode

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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omap: Set appropriate cache configuration for LPAE and non-LAPE cases

Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two

omap: Set appropriate cache configuration for LPAE and non-LAPE cases

Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.

In the case of LPAE the cache configuration happens via MAIR0 lookup.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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omap: Remove hardcoding of mmu section shift to 20

As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHI

omap: Remove hardcoding of mmu section shift to 20

As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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ARMv8/sec-firmware: fix a compile error

When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there

ARMv8/sec-firmware: fix a compile error

When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there will be some build errors,
so give a default definition.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

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ARM: Respect CONFIG_SPL_STACK define in lowlevel_init.S

The SPL and U-Boot proper may use different initial stack
locations, which are configured via CONFIG_SPL_STACK and
CONFIG_SYS_INIT_SP_ADDR def

ARM: Respect CONFIG_SPL_STACK define in lowlevel_init.S

The SPL and U-Boot proper may use different initial stack
locations, which are configured via CONFIG_SPL_STACK and
CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S
code needs to handle this in the same way as crt0.S

Without this fix, setting the U-Boot stack location to some
place, which is not safely accessible by the SPL (such as
the DRAM), causes a very early SPL deadlock.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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spl: Kconfig: Move SPL_DISPLAY_PRINT to Kconfig

Move this option to Kconfig and tidy up existing uses. Also add a function
comment to the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>

spl: Kconfig: Move SPL_DISPLAY_PRINT to Kconfig

Move this option to Kconfig and tidy up existing uses. Also add a function
comment to the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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armv7: ls1021a: Move DDR config options to Kconfig

Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Gl

armv7: ls1021a: Move DDR config options to Kconfig

Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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armv8: fsl-layerscape: Move DDR config options to Kconfig

Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Gl

armv8: fsl-layerscape: Move DDR config options to Kconfig

Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig

Move these options to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.or

arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig

Move these options to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig

Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.s

arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig

Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig

Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by:

arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig

Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Move MAX_CPUS to Kconfig

Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Review

arm: Move MAX_CPUS to Kconfig

Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig

Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by:

arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig

Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Fix Kconfig for proper display menu

Some config options should not have prompt. They are selected by choosing
target.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@c

arm: Fix Kconfig for proper display menu

Some config options should not have prompt. They are selected by choosing
target.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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armv8: fsl: Enable USB only when SYSCLK is 100 MHz

SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.

Signed-off-b

armv8: fsl: Enable USB only when SYSCLK is 100 MHz

SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC

armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Fix "cpu status" command

The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including b

armv8: fsl-layerscape: Fix "cpu status" command

The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.

Tested on LS2080ARDB and LS1043ARDB.

Signed-off-by: York Sun <york.sun@nxp.com>

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armv8/fsl-layerscape: print SoC revsion number

The exact SoC revsion number can be recognized from U-Boot log.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu

armv8/fsl-layerscape: print SoC revsion number

The exact SoC revsion number can be recognized from U-Boot log.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv7: LS1021a: enable i-cache in start.S

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faste

armv7: LS1021a: enable i-cache in start.S

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCN

armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch2: adjust sata parameter

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp

armv8: fsl-lsch2: adjust sata parameter

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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