1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_MP 13 #define CONFIG_GICV3 14 #define CONFIG_FSL_TZPC_BP147 15 16 #include <asm/arch/ls2080a_stream_id.h> 17 #include <asm/arch/config.h> 18 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) 19 #define CONFIG_SYS_HAS_SERDES 20 #endif 21 22 /* Link Definitions */ 23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 24 25 /* We need architecture specific misc initializations */ 26 #define CONFIG_ARCH_MISC_INIT 27 28 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 29 30 /* Link Definitions */ 31 #ifndef CONFIG_QSPI_BOOT 32 #ifdef CONFIG_SPL 33 #define CONFIG_SYS_TEXT_BASE 0x80400000 34 #else 35 #define CONFIG_SYS_TEXT_BASE 0x30100000 36 #endif 37 #endif 38 39 #ifdef CONFIG_EMU 40 #define CONFIG_SYS_NO_FLASH 41 #endif 42 43 #define CONFIG_SUPPORT_RAW_INITRD 44 45 #define CONFIG_SKIP_LOWLEVEL_INIT 46 #define CONFIG_BOARD_EARLY_INIT_F 1 47 48 #ifndef CONFIG_SPL 49 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 50 #endif 51 #ifndef CONFIG_SYS_FSL_DDR4 52 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 53 #define CONFIG_SYS_DDR_RAW_TIMING 54 #endif 55 56 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 57 58 #define CONFIG_VERY_BIG_RAM 59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 60 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 61 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 62 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 63 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 64 65 /* 66 * SMP Definitinos 67 */ 68 #define CPU_RELEASE_ADDR secondary_boot_func 69 70 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 71 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 72 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 73 /* 74 * DDR controller use 0 as the base address for binding. 75 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 76 */ 77 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 78 #define CONFIG_DP_DDR_CTRL 2 79 #define CONFIG_DP_DDR_NUM_CTRLS 1 80 #endif 81 82 /* Generic Timer Definitions */ 83 /* 84 * This is not an accurate number. It is used in start.S. The frequency 85 * will be udpated later when get_bus_freq(0) is available. 86 */ 87 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 88 89 /* Size of malloc() pool */ 90 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 91 92 /* I2C */ 93 #define CONFIG_SYS_I2C 94 #define CONFIG_SYS_I2C_MXC 95 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 96 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 97 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 98 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 99 100 /* Serial Port */ 101 #define CONFIG_CONS_INDEX 1 102 #define CONFIG_SYS_NS16550_SERIAL 103 #define CONFIG_SYS_NS16550_REG_SIZE 1 104 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 105 106 #define CONFIG_BAUDRATE 115200 107 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 108 109 /* IFC */ 110 #define CONFIG_FSL_IFC 111 112 /* 113 * During booting, IFC is mapped at the region of 0x30000000. 114 * But this region is limited to 256MB. To accommodate NOR, promjet 115 * and FPGA. This region is divided as below: 116 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 117 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 118 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 119 * 120 * To accommodate bigger NOR flash and other devices, we will map IFC 121 * chip selects to as below: 122 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 123 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 124 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 125 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 126 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 127 * 128 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 129 * CONFIG_SYS_FLASH_BASE has the final address (core view) 130 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 131 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 132 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 133 */ 134 135 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 136 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 137 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 138 139 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 140 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 141 142 #ifndef __ASSEMBLY__ 143 unsigned long long get_qixis_addr(void); 144 #endif 145 #define QIXIS_BASE get_qixis_addr() 146 #define QIXIS_BASE_PHYS 0x20000000 147 #define QIXIS_BASE_PHYS_EARLY 0xC000000 148 #define QIXIS_STAT_PRES1 0xb 149 #define QIXIS_SDID_MASK 0x07 150 #define QIXIS_ESDHC_NO_ADAPTER 0x7 151 152 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 153 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 154 155 /* MC firmware */ 156 #define CONFIG_FSL_MC_ENET 157 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 158 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 159 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 160 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 161 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 162 /* For LS2085A */ 163 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 164 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 165 166 /* 167 * Carve out a DDR region which will not be used by u-boot/Linux 168 * 169 * It will be used by MC and Debug Server. The MC region must be 170 * 512MB aligned, so the min size to hide is 512MB. 171 */ 172 #ifdef CONFIG_FSL_MC_ENET 173 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 174 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 175 #endif 176 177 /* PCIe */ 178 #define CONFIG_PCIE1 /* PCIE controller 1 */ 179 #define CONFIG_PCIE2 /* PCIE controller 2 */ 180 #define CONFIG_PCIE3 /* PCIE controller 3 */ 181 #define CONFIG_PCIE4 /* PCIE controller 4 */ 182 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 183 #ifdef CONFIG_LS2080A 184 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" 185 #endif 186 187 #define CONFIG_SYS_PCI_64BIT 188 189 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 190 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 191 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 192 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 193 194 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 195 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 196 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 197 198 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 199 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 200 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 201 202 /* Command line configuration */ 203 #define CONFIG_CMD_ENV 204 205 /* Miscellaneous configurable options */ 206 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 207 #define CONFIG_ARCH_EARLY_INIT_R 208 209 /* Physical Memory Map */ 210 /* fixme: these need to be checked against the board */ 211 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 212 213 #define CONFIG_NR_DRAM_BANKS 3 214 215 #define CONFIG_HWCONFIG 216 #define HWCONFIG_BUFFER_SIZE 128 217 218 #define CONFIG_DISPLAY_CPUINFO 219 220 /* Allow to overwrite serial and ethaddr */ 221 #define CONFIG_ENV_OVERWRITE 222 223 /* Initial environment variables */ 224 #define CONFIG_EXTRA_ENV_SETTINGS \ 225 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 226 "loadaddr=0x80100000\0" \ 227 "kernel_addr=0x100000\0" \ 228 "ramdisk_addr=0x800000\0" \ 229 "ramdisk_size=0x2000000\0" \ 230 "fdt_high=0xa0000000\0" \ 231 "initrd_high=0xffffffffffffffff\0" \ 232 "kernel_start=0x581200000\0" \ 233 "kernel_load=0xa0000000\0" \ 234 "kernel_size=0x2800000\0" \ 235 "console=ttyAMA0,38400n8\0" \ 236 "mcinitcmd=fsl_mc start mc 0x580300000" \ 237 " 0x580800000 \0" 238 239 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 240 "earlycon=uart8250,mmio,0x21c0500 " \ 241 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 242 " hugepagesz=2m hugepages=256" 243 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ 244 " cp.b $kernel_start $kernel_load" \ 245 " $kernel_size && bootm $kernel_load" 246 247 /* Monitor Command Prompt */ 248 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 249 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 250 sizeof(CONFIG_SYS_PROMPT) + 16) 251 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 252 #define CONFIG_SYS_LONGHELP 253 #define CONFIG_CMDLINE_EDITING 1 254 #define CONFIG_AUTO_COMPLETE 255 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 256 257 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 258 259 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 260 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 261 #define CONFIG_SPL_FRAMEWORK 262 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 263 #define CONFIG_SPL_MAX_SIZE 0x16000 264 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 265 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 266 #define CONFIG_SPL_TEXT_BASE 0x1800a000 267 268 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 269 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 270 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 271 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 272 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) 273 274 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 275 276 /* Hash command with SHA acceleration supported in hardware */ 277 #ifdef CONFIG_FSL_CAAM 278 #define CONFIG_CMD_HASH 279 #define CONFIG_SHA_HW_ACCEL 280 #endif 281 282 #endif /* __LS2_COMMON_H */ 283