1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1012A_COMMON_H 8 #define __LS1012A_COMMON_H 9 10 #define CONFIG_FSL_LAYERSCAPE 11 #define CONFIG_GICV2 12 13 #define CONFIG_SYS_HAS_SERDES 14 15 #include <asm/arch/config.h> 16 #define CONFIG_SYS_NO_FLASH 17 18 #define CONFIG_SUPPORT_RAW_INITRD 19 20 #define CONFIG_DISPLAY_BOARDINFO_LATE 21 22 #define CONFIG_SYS_TEXT_BASE 0x40100000 23 24 #define CONFIG_SYS_FSL_CLK 25 #define CONFIG_SYS_CLK_FREQ 100000000 26 #define CONFIG_DDR_CLK_FREQ 125000000 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_BOARD_EARLY_INIT_F 1 30 31 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 32 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 33 34 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 35 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 36 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 37 38 /* Generic Timer Definitions */ 39 #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ 40 41 /* CSU */ 42 #define CONFIG_LAYERSCAPE_NS_ACCESS 43 44 /* Size of malloc() pool */ 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 46 47 /*SPI device */ 48 #ifdef CONFIG_QSPI_BOOT 49 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 50 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 51 #define CONFIG_ENV_SPI_BUS 0 52 #define CONFIG_ENV_SPI_CS 0 53 #define CONFIG_ENV_SPI_MAX_HZ 1000000 54 #define CONFIG_ENV_SPI_MODE 0x03 55 #define CONFIG_SPI_FLASH_SPANSION 56 #define CONFIG_FSL_SPI_INTERFACE 57 #define CONFIG_SF_DATAFLASH 58 59 #define CONFIG_FSL_QSPI 60 #define QSPI0_AMBA_BASE 0x40000000 61 #define CONFIG_SPI_FLASH_SPANSION 62 #define CONFIG_SPI_FLASH_BAR 63 64 #define FSL_QSPI_FLASH_SIZE (1 << 24) 65 #define FSL_QSPI_FLASH_NUM 2 66 67 /* 68 * Environment 69 */ 70 #define CONFIG_ENV_OVERWRITE 71 72 #define CONFIG_ENV_IS_IN_SPI_FLASH 73 #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ 74 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ 75 #define CONFIG_ENV_SECT_SIZE 0x40000 76 #endif 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C_MXC 81 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 82 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 83 84 #define CONFIG_CONS_INDEX 1 85 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_REG_SIZE 1 87 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 88 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 91 92 /* Command line configuration */ 93 #define CONFIG_CMD_ENV 94 #undef CONFIG_CMD_IMLS 95 96 #define CONFIG_ARCH_EARLY_INIT_R 97 98 #define CONFIG_SYS_HZ 1000 99 100 #define CONFIG_HWCONFIG 101 #define HWCONFIG_BUFFER_SIZE 128 102 103 #define CONFIG_DISPLAY_CPUINFO 104 105 /* Initial environment variables */ 106 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 "initrd_high=0xffffffff\0" \ 108 "verify=no\0" \ 109 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 110 "loadaddr=0x80100000\0" \ 111 "kernel_addr=0x100000\0" \ 112 "ramdisk_addr=0x800000\0" \ 113 "ramdisk_size=0x2000000\0" \ 114 "fdt_high=0xffffffffffffffff\0" \ 115 "initrd_high=0xffffffffffffffff\0" \ 116 "kernel_start=0xa00000\0" \ 117 "kernel_load=0xa0000000\0" \ 118 "kernel_size=0x2800000\0" \ 119 "console=ttyAMA0,38400n8\0" 120 121 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 122 "earlycon=uart8250,mmio,0x21c0500" 123 #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ 124 "$kernel_start $kernel_size && "\ 125 "bootm $kernel_load" 126 127 /* Monitor Command Prompt */ 128 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 130 sizeof(CONFIG_SYS_PROMPT) + 16) 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 132 #define CONFIG_SYS_LONGHELP 133 #define CONFIG_CMDLINE_EDITING 1 134 #define CONFIG_AUTO_COMPLETE 135 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 136 137 #define CONFIG_PANIC_HANG 138 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 139 140 #include <asm/fsl_secure_boot.h> 141 142 #endif /* __LS1012A_COMMON_H */ 143