1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_LS1043A 13 #define CONFIG_MP 14 #define CONFIG_SYS_FSL_CLK 15 #define CONFIG_GICV2 16 17 #include <asm/arch/config.h> 18 #ifdef CONFIG_SYS_FSL_SRDS_1 19 #define CONFIG_SYS_HAS_SERDES 20 #endif 21 22 /* Link Definitions */ 23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 24 25 #define CONFIG_SUPPORT_RAW_INITRD 26 27 #define CONFIG_SKIP_LOWLEVEL_INIT 28 #define CONFIG_BOARD_EARLY_INIT_F 1 29 30 #ifndef CONFIG_SYS_FSL_DDR4 31 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 32 #endif 33 34 #define CONFIG_VERY_BIG_RAM 35 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 36 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 37 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 38 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 39 40 #define CPU_RELEASE_ADDR secondary_boot_func 41 42 /* Generic Timer Definitions */ 43 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 44 45 /* Size of malloc() pool */ 46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 47 48 /* Serial Port */ 49 #define CONFIG_CONS_INDEX 1 50 #define CONFIG_SYS_NS16550_SERIAL 51 #define CONFIG_SYS_NS16550_REG_SIZE 1 52 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 53 54 #define CONFIG_BAUDRATE 115200 55 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 56 57 /* SD boot SPL */ 58 #ifdef CONFIG_SD_BOOT 59 #define CONFIG_SPL_FRAMEWORK 60 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 61 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 62 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 63 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 64 65 #define CONFIG_SPL_TEXT_BASE 0x10000000 66 #define CONFIG_SPL_MAX_SIZE 0x1d000 67 #define CONFIG_SPL_STACK 0x1001e000 68 #define CONFIG_SPL_PAD_TO 0x1d000 69 70 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 71 CONFIG_SYS_MONITOR_LEN) 72 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 73 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 74 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 75 #define CONFIG_SYS_MONITOR_LEN 0xa0000 76 #endif 77 78 /* NAND SPL */ 79 #ifdef CONFIG_NAND_BOOT 80 #define CONFIG_SPL_PBL_PAD 81 #define CONFIG_SPL_FRAMEWORK 82 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SPL_TEXT_BASE 0x10000000 85 #define CONFIG_SPL_MAX_SIZE 0x1a000 86 #define CONFIG_SPL_STACK 0x1001d000 87 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 88 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 89 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 90 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 92 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 93 #define CONFIG_SYS_MONITOR_LEN 0xa0000 94 #endif 95 96 /* IFC */ 97 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 98 #define CONFIG_FSL_IFC 99 /* 100 * CONFIG_SYS_FLASH_BASE has the final address (core view) 101 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 102 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 103 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0x60000000 106 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 107 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 108 109 #ifndef CONFIG_SYS_NO_FLASH 110 #define CONFIG_FLASH_CFI_DRIVER 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 113 #define CONFIG_SYS_FLASH_QUIET_TEST 114 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 115 #endif 116 #endif 117 118 /* I2C */ 119 #define CONFIG_SYS_I2C 120 #define CONFIG_SYS_I2C_MXC 121 #define CONFIG_SYS_I2C_MXC_I2C1 122 #define CONFIG_SYS_I2C_MXC_I2C2 123 #define CONFIG_SYS_I2C_MXC_I2C3 124 #define CONFIG_SYS_I2C_MXC_I2C4 125 126 /* PCIe */ 127 #define CONFIG_PCI /* Enable PCI/PCIE */ 128 #define CONFIG_PCIE1 /* PCIE controller 1 */ 129 #define CONFIG_PCIE2 /* PCIE controller 2 */ 130 #define CONFIG_PCIE3 /* PCIE controller 3 */ 131 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 132 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 133 134 #define CONFIG_SYS_PCI_64BIT 135 136 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 137 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 138 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 139 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 140 141 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 142 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 143 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 144 145 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 146 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 147 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 148 149 #ifdef CONFIG_PCI 150 #define CONFIG_NET_MULTI 151 #define CONFIG_PCI_PNP 152 #define CONFIG_E1000 153 #define CONFIG_PCI_SCAN_SHOW 154 #define CONFIG_CMD_PCI 155 #endif 156 157 /* Command line configuration */ 158 #define CONFIG_CMD_ENV 159 #define CONFIG_MENU 160 #define CONFIG_CMD_PXE 161 162 /* MMC */ 163 #define CONFIG_MMC 164 #ifdef CONFIG_MMC 165 #define CONFIG_FSL_ESDHC 166 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 167 #define CONFIG_GENERIC_MMC 168 #define CONFIG_DOS_PARTITION 169 #endif 170 171 /* DSPI */ 172 #define CONFIG_FSL_DSPI 173 #ifdef CONFIG_FSL_DSPI 174 #define CONFIG_DM_SPI_FLASH 175 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 176 #define CONFIG_SPI_FLASH_SST /* cs1 */ 177 #define CONFIG_SPI_FLASH_EON /* cs2 */ 178 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 179 #define CONFIG_SF_DEFAULT_BUS 1 180 #define CONFIG_SF_DEFAULT_CS 0 181 #endif 182 #endif 183 184 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 185 186 /* FMan ucode */ 187 #define CONFIG_SYS_DPAA_FMAN 188 #ifdef CONFIG_SYS_DPAA_FMAN 189 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 190 191 #ifdef CONFIG_NAND_BOOT 192 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 193 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 194 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 195 #elif defined(CONFIG_SD_BOOT) 196 /* 197 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 198 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 199 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 200 */ 201 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 202 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 203 #elif defined(CONFIG_QSPI_BOOT) 204 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 205 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 206 #define CONFIG_ENV_SPI_BUS 0 207 #define CONFIG_ENV_SPI_CS 0 208 #define CONFIG_ENV_SPI_MAX_HZ 1000000 209 #define CONFIG_ENV_SPI_MODE 0x03 210 #else 211 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 212 /* FMan fireware Pre-load address */ 213 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 214 #endif 215 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 216 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 217 #endif 218 219 /* Miscellaneous configurable options */ 220 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 221 #define CONFIG_ARCH_EARLY_INIT_R 222 #define CONFIG_BOARD_LATE_INIT 223 224 #define CONFIG_HWCONFIG 225 #define HWCONFIG_BUFFER_SIZE 128 226 227 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 228 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 229 "5m(kernel),1m(dtb),9m(file_system)" 230 #else 231 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 232 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 233 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 234 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 235 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 236 "40m(nor_bank4_fit);7e800000.flash:" \ 237 "1m(nand_uboot),1m(nand_uboot_env)," \ 238 "20m(nand_fit);spi0.0:1m(uboot)," \ 239 "5m(kernel),1m(dtb),9m(file_system)" 240 #endif 241 242 /* Initial environment variables */ 243 #define CONFIG_EXTRA_ENV_SETTINGS \ 244 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 245 "loadaddr=0x80100000\0" \ 246 "fdt_high=0xffffffffffffffff\0" \ 247 "initrd_high=0xffffffffffffffff\0" \ 248 "kernel_start=0x61100000\0" \ 249 "kernel_load=0xa0000000\0" \ 250 "kernel_size=0x2800000\0" \ 251 "console=ttyS0,115200\0" \ 252 "mtdparts=" MTDPARTS_DEFAULT "\0" 253 254 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 255 "earlycon=uart8250,mmio,0x21c0500 " \ 256 MTDPARTS_DEFAULT 257 258 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 259 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 260 "e0000 f00000 && bootm $kernel_load" 261 #else 262 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 263 "$kernel_size && bootm $kernel_load" 264 #endif 265 266 /* Monitor Command Prompt */ 267 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 268 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 269 sizeof(CONFIG_SYS_PROMPT) + 16) 270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 271 #define CONFIG_SYS_LONGHELP 272 #define CONFIG_CMDLINE_EDITING 1 273 #define CONFIG_AUTO_COMPLETE 274 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 275 276 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 277 278 /* Hash command with SHA acceleration supported in hardware */ 279 #ifdef CONFIG_FSL_CAAM 280 #define CONFIG_CMD_HASH 281 #define CONFIG_SHA_HW_ACCEL 282 #endif 283 284 #endif /* __LS1043A_COMMON_H */ 285