1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_LS1043A 13 #define CONFIG_MP 14 #define CONFIG_SYS_FSL_CLK 15 #define CONFIG_GICV2 16 17 #include <asm/arch/config.h> 18 19 /* Link Definitions */ 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 22 #define CONFIG_SUPPORT_RAW_INITRD 23 24 #define CONFIG_SKIP_LOWLEVEL_INIT 25 #define CONFIG_BOARD_EARLY_INIT_F 1 26 27 #ifndef CONFIG_SYS_FSL_DDR4 28 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 29 #endif 30 31 #define CONFIG_VERY_BIG_RAM 32 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 33 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 34 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 35 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 36 37 #define CPU_RELEASE_ADDR secondary_boot_func 38 39 /* Generic Timer Definitions */ 40 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 41 42 /* Size of malloc() pool */ 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 44 45 /* Serial Port */ 46 #define CONFIG_CONS_INDEX 1 47 #define CONFIG_SYS_NS16550_SERIAL 48 #define CONFIG_SYS_NS16550_REG_SIZE 1 49 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 50 51 #define CONFIG_BAUDRATE 115200 52 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 53 54 /* SD boot SPL */ 55 #ifdef CONFIG_SD_BOOT 56 #define CONFIG_SPL_FRAMEWORK 57 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 60 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 61 62 #define CONFIG_SPL_TEXT_BASE 0x10000000 63 #define CONFIG_SPL_MAX_SIZE 0x1d000 64 #define CONFIG_SPL_STACK 0x1001e000 65 #define CONFIG_SPL_PAD_TO 0x1d000 66 67 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 68 CONFIG_SYS_MONITOR_LEN) 69 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 70 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 72 #define CONFIG_SYS_MONITOR_LEN 0xa0000 73 #endif 74 75 /* NAND SPL */ 76 #ifdef CONFIG_NAND_BOOT 77 #define CONFIG_SPL_PBL_PAD 78 #define CONFIG_SPL_FRAMEWORK 79 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 80 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 81 #define CONFIG_SPL_TEXT_BASE 0x10000000 82 #define CONFIG_SPL_MAX_SIZE 0x1a000 83 #define CONFIG_SPL_STACK 0x1001d000 84 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 85 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 86 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 87 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 88 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 89 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 90 #define CONFIG_SYS_MONITOR_LEN 0xa0000 91 #endif 92 93 /* IFC */ 94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 95 #define CONFIG_FSL_IFC 96 /* 97 * CONFIG_SYS_FLASH_BASE has the final address (core view) 98 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 99 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 100 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 101 */ 102 #define CONFIG_SYS_FLASH_BASE 0x60000000 103 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 104 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 105 106 #ifndef CONFIG_SYS_NO_FLASH 107 #define CONFIG_FLASH_CFI_DRIVER 108 #define CONFIG_SYS_FLASH_CFI 109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 110 #define CONFIG_SYS_FLASH_QUIET_TEST 111 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 112 #endif 113 #endif 114 115 /* I2C */ 116 #define CONFIG_SYS_I2C 117 #define CONFIG_SYS_I2C_MXC 118 #define CONFIG_SYS_I2C_MXC_I2C1 119 #define CONFIG_SYS_I2C_MXC_I2C2 120 #define CONFIG_SYS_I2C_MXC_I2C3 121 #define CONFIG_SYS_I2C_MXC_I2C4 122 123 /* PCIe */ 124 #define CONFIG_PCI /* Enable PCI/PCIE */ 125 #define CONFIG_PCIE1 /* PCIE controller 1 */ 126 #define CONFIG_PCIE2 /* PCIE controller 2 */ 127 #define CONFIG_PCIE3 /* PCIE controller 3 */ 128 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 129 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 130 131 #define CONFIG_SYS_PCI_64BIT 132 133 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 134 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 135 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 136 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 137 138 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 139 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 140 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 141 142 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 143 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 144 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 145 146 #ifdef CONFIG_PCI 147 #define CONFIG_NET_MULTI 148 #define CONFIG_PCI_PNP 149 #define CONFIG_E1000 150 #define CONFIG_PCI_SCAN_SHOW 151 #define CONFIG_CMD_PCI 152 #endif 153 154 /* Command line configuration */ 155 #define CONFIG_CMD_ENV 156 #define CONFIG_MENU 157 #define CONFIG_CMD_PXE 158 159 /* MMC */ 160 #define CONFIG_MMC 161 #ifdef CONFIG_MMC 162 #define CONFIG_FSL_ESDHC 163 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 164 #define CONFIG_GENERIC_MMC 165 #define CONFIG_DOS_PARTITION 166 #endif 167 168 /* DSPI */ 169 #define CONFIG_FSL_DSPI 170 #ifdef CONFIG_FSL_DSPI 171 #define CONFIG_DM_SPI_FLASH 172 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 173 #define CONFIG_SPI_FLASH_SST /* cs1 */ 174 #define CONFIG_SPI_FLASH_EON /* cs2 */ 175 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 176 #define CONFIG_SF_DEFAULT_BUS 1 177 #define CONFIG_SF_DEFAULT_CS 0 178 #endif 179 #endif 180 181 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 182 183 /* FMan ucode */ 184 #define CONFIG_SYS_DPAA_FMAN 185 #ifdef CONFIG_SYS_DPAA_FMAN 186 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 187 188 #ifdef CONFIG_NAND_BOOT 189 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 190 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 191 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 192 #elif defined(CONFIG_SD_BOOT) 193 /* 194 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 195 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 196 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 197 */ 198 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 199 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 200 #elif defined(CONFIG_QSPI_BOOT) 201 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 202 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 203 #define CONFIG_ENV_SPI_BUS 0 204 #define CONFIG_ENV_SPI_CS 0 205 #define CONFIG_ENV_SPI_MAX_HZ 1000000 206 #define CONFIG_ENV_SPI_MODE 0x03 207 #else 208 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 209 /* FMan fireware Pre-load address */ 210 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 211 #endif 212 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 213 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 214 #endif 215 216 /* Miscellaneous configurable options */ 217 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 218 #define CONFIG_ARCH_EARLY_INIT_R 219 #define CONFIG_BOARD_LATE_INIT 220 221 #define CONFIG_HWCONFIG 222 #define HWCONFIG_BUFFER_SIZE 128 223 224 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 225 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 226 "5m(kernel),1m(dtb),9m(file_system)" 227 #else 228 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 229 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 230 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 231 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 232 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 233 "40m(nor_bank4_fit);7e800000.flash:" \ 234 "1m(nand_uboot),1m(nand_uboot_env)," \ 235 "20m(nand_fit);spi0.0:1m(uboot)," \ 236 "5m(kernel),1m(dtb),9m(file_system)" 237 #endif 238 239 /* Initial environment variables */ 240 #define CONFIG_EXTRA_ENV_SETTINGS \ 241 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 242 "loadaddr=0x80100000\0" \ 243 "fdt_high=0xffffffffffffffff\0" \ 244 "initrd_high=0xffffffffffffffff\0" \ 245 "kernel_start=0x61100000\0" \ 246 "kernel_load=0xa0000000\0" \ 247 "kernel_size=0x2800000\0" \ 248 "console=ttyS0,115200\0" \ 249 "mtdparts=" MTDPARTS_DEFAULT "\0" 250 251 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 252 "earlycon=uart8250,mmio,0x21c0500 " \ 253 MTDPARTS_DEFAULT 254 255 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 256 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 257 "e0000 f00000 && bootm $kernel_load" 258 #else 259 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 260 "$kernel_size && bootm $kernel_load" 261 #endif 262 263 /* Monitor Command Prompt */ 264 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 266 sizeof(CONFIG_SYS_PROMPT) + 16) 267 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 268 #define CONFIG_SYS_LONGHELP 269 #define CONFIG_CMDLINE_EDITING 1 270 #define CONFIG_AUTO_COMPLETE 271 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 272 273 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 274 275 /* Hash command with SHA acceleration supported in hardware */ 276 #ifdef CONFIG_FSL_CAAM 277 #define CONFIG_CMD_HASH 278 #define CONFIG_SHA_HW_ACCEL 279 #endif 280 281 #endif /* __LS1043A_COMMON_H */ 282