1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 16 #define CONFIG_SYS_TEXT_BASE 0x82000000 17 #elif defined(CONFIG_QSPI_BOOT) 18 #define CONFIG_SYS_TEXT_BASE 0x40010000 19 #else 20 #define CONFIG_SYS_TEXT_BASE 0x60100000 21 #endif 22 23 #ifndef __ASSEMBLY__ 24 unsigned long get_board_sys_clk(void); 25 unsigned long get_board_ddr_clk(void); 26 #endif 27 28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 29 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 30 31 #define CONFIG_SKIP_LOWLEVEL_INIT 32 33 #define CONFIG_LAYERSCAPE_NS_ACCESS 34 35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 36 /* Physical Memory Map */ 37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 38 #define CONFIG_NR_DRAM_BANKS 2 39 40 #define CONFIG_DDR_SPD 41 #define SPD_EEPROM_ADDRESS 0x51 42 #define CONFIG_SYS_SPD_BUS_NUM 0 43 44 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 45 46 #define CONFIG_DDR_ECC 47 #ifdef CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 50 #endif 51 52 /* DSPI */ 53 #ifdef CONFIG_FSL_DSPI 54 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 55 #define CONFIG_SPI_FLASH_SST /* cs1 */ 56 #define CONFIG_SPI_FLASH_EON /* cs2 */ 57 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 58 #define CONFIG_SF_DEFAULT_BUS 1 59 #define CONFIG_SF_DEFAULT_CS 0 60 #endif 61 #endif 62 63 /* QSPI */ 64 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 65 #ifdef CONFIG_FSL_QSPI 66 #define CONFIG_SPI_FLASH_SPANSION 67 #define FSL_QSPI_FLASH_SIZE (1 << 24) 68 #define FSL_QSPI_FLASH_NUM 2 69 #endif 70 #endif 71 72 #ifdef CONFIG_SYS_DPAA_FMAN 73 #define CONFIG_FMAN_ENET 74 #define CONFIG_PHYLIB 75 #define CONFIG_PHY_VITESSE 76 #define CONFIG_PHY_REALTEK 77 #define CONFIG_PHYLIB_10G 78 #define RGMII_PHY1_ADDR 0x1 79 #define RGMII_PHY2_ADDR 0x2 80 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 81 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 82 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 83 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 84 /* PHY address on QSGMII riser card on slot 2 */ 85 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 86 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 87 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 88 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 89 #endif 90 91 #ifdef CONFIG_RAMBOOT_PBL 92 #define CONFIG_SYS_FSL_PBL_PBI \ 93 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 94 #endif 95 96 #ifdef CONFIG_NAND_BOOT 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 99 #endif 100 101 #ifdef CONFIG_SD_BOOT 102 #ifdef CONFIG_SD_BOOT_QSPI 103 #define CONFIG_SYS_FSL_PBL_RCW \ 104 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 105 #else 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 108 #endif 109 #endif 110 111 /* IFC */ 112 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 113 #define CONFIG_FSL_IFC 114 /* 115 * CONFIG_SYS_FLASH_BASE has the final address (core view) 116 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 117 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 118 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 119 */ 120 #define CONFIG_SYS_FLASH_BASE 0x60000000 121 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 122 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 123 124 #ifndef CONFIG_SYS_NO_FLASH 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 128 #define CONFIG_SYS_FLASH_QUIET_TEST 129 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 130 #endif 131 #endif 132 133 /* SATA */ 134 #define CONFIG_LIBATA 135 #define CONFIG_SCSI_AHCI 136 #define CONFIG_SCSI_AHCI_PLAT 137 #define CONFIG_SCSI 138 #define CONFIG_DOS_PARTITION 139 #define CONFIG_BOARD_LATE_INIT 140 141 /* EEPROM */ 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_NXID 144 #define CONFIG_SYS_EEPROM_BUS_NUM 0 145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 149 150 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 151 152 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 153 #define CONFIG_SYS_SCSI_MAX_LUN 1 154 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 155 CONFIG_SYS_SCSI_MAX_LUN) 156 157 /* 158 * IFC Definitions 159 */ 160 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 161 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 162 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 163 CSPR_PORT_SIZE_16 | \ 164 CSPR_MSEL_NOR | \ 165 CSPR_V) 166 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 167 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 168 + 0x8000000) | \ 169 CSPR_PORT_SIZE_16 | \ 170 CSPR_MSEL_NOR | \ 171 CSPR_V) 172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 173 174 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 175 CSOR_NOR_TRHZ_80) 176 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 177 FTIM0_NOR_TEADC(0x5) | \ 178 FTIM0_NOR_TEAHC(0x5)) 179 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 180 FTIM1_NOR_TRAD_NOR(0x1a) | \ 181 FTIM1_NOR_TSEQRAD_NOR(0x13)) 182 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 183 FTIM2_NOR_TCH(0x4) | \ 184 FTIM2_NOR_TWPH(0xe) | \ 185 FTIM2_NOR_TWP(0x1c)) 186 #define CONFIG_SYS_NOR_FTIM3 0 187 188 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #define CONFIG_SYS_FLASH_EMPTY_INFO 194 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 195 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 196 197 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 198 #define CONFIG_SYS_WRITE_SWAPPED_DATA 199 200 /* 201 * NAND Flash Definitions 202 */ 203 #define CONFIG_NAND_FSL_IFC 204 205 #define CONFIG_SYS_NAND_BASE 0x7e800000 206 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 207 208 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 209 210 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 211 | CSPR_PORT_SIZE_8 \ 212 | CSPR_MSEL_NAND \ 213 | CSPR_V) 214 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 215 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 216 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 217 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 218 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 219 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 220 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 221 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 222 223 #define CONFIG_SYS_NAND_ONFI_DETECTION 224 225 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 226 FTIM0_NAND_TWP(0x18) | \ 227 FTIM0_NAND_TWCHT(0x7) | \ 228 FTIM0_NAND_TWH(0xa)) 229 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 230 FTIM1_NAND_TWBE(0x39) | \ 231 FTIM1_NAND_TRR(0xe) | \ 232 FTIM1_NAND_TRP(0x18)) 233 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 234 FTIM2_NAND_TREH(0xa) | \ 235 FTIM2_NAND_TWHRE(0x1e)) 236 #define CONFIG_SYS_NAND_FTIM3 0x0 237 238 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 239 #define CONFIG_SYS_MAX_NAND_DEVICE 1 240 #define CONFIG_MTD_NAND_VERIFY_WRITE 241 #define CONFIG_CMD_NAND 242 243 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 244 #endif 245 246 #ifdef CONFIG_NAND_BOOT 247 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 248 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 249 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 250 #endif 251 252 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 253 #define CONFIG_QIXIS_I2C_ACCESS 254 #define CONFIG_SYS_I2C_EARLY_INIT 255 #define CONFIG_SYS_NO_FLASH 256 #endif 257 258 /* 259 * QIXIS Definitions 260 */ 261 #define CONFIG_FSL_QIXIS 262 263 #ifdef CONFIG_FSL_QIXIS 264 #define QIXIS_BASE 0x7fb00000 265 #define QIXIS_BASE_PHYS QIXIS_BASE 266 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 267 #define QIXIS_LBMAP_SWITCH 6 268 #define QIXIS_LBMAP_MASK 0x0f 269 #define QIXIS_LBMAP_SHIFT 0 270 #define QIXIS_LBMAP_DFLTBANK 0x00 271 #define QIXIS_LBMAP_ALTBANK 0x04 272 #define QIXIS_LBMAP_NAND 0x09 273 #define QIXIS_LBMAP_SD 0x00 274 #define QIXIS_LBMAP_SD_QSPI 0xff 275 #define QIXIS_LBMAP_QSPI 0xff 276 #define QIXIS_RCW_SRC_NAND 0x110 277 #define QIXIS_RCW_SRC_SD 0x040 278 #define QIXIS_RCW_SRC_QSPI 0x045 279 #define QIXIS_RST_CTL_RESET 0x41 280 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 281 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 282 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 283 284 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 285 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 286 CSPR_PORT_SIZE_8 | \ 287 CSPR_MSEL_GPCM | \ 288 CSPR_V) 289 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 290 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 291 CSOR_NOR_NOR_MODE_AVD_NOR | \ 292 CSOR_NOR_TRHZ_80) 293 294 /* 295 * QIXIS Timing parameters for IFC GPCM 296 */ 297 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 298 FTIM0_GPCM_TEADC(0x20) | \ 299 FTIM0_GPCM_TEAHC(0x10)) 300 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 301 FTIM1_GPCM_TRAD(0x1f)) 302 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 303 FTIM2_GPCM_TCH(0x8) | \ 304 FTIM2_GPCM_TWP(0xf0)) 305 #define CONFIG_SYS_FPGA_FTIM3 0x0 306 #endif 307 308 #ifdef CONFIG_NAND_BOOT 309 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 310 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 311 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 312 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 313 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 314 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 315 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 316 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 317 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 326 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 327 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 334 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 335 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 336 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 337 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 338 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 339 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 340 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 341 #else 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 351 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 352 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 353 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 354 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 355 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 356 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 357 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 358 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 359 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 360 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 361 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 362 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 363 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 364 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 365 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 366 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 367 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 368 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 369 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 370 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 371 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 372 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 373 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 374 #endif 375 376 /* 377 * I2C bus multiplexer 378 */ 379 #define I2C_MUX_PCA_ADDR_PRI 0x77 380 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 381 #define I2C_RETIMER_ADDR 0x18 382 #define I2C_MUX_CH_DEFAULT 0x8 383 #define I2C_MUX_CH_CH7301 0xC 384 #define I2C_MUX_CH5 0xD 385 #define I2C_MUX_CH6 0xE 386 #define I2C_MUX_CH7 0xF 387 388 #define I2C_MUX_CH_VOL_MONITOR 0xa 389 390 /* Voltage monitor on channel 2*/ 391 #define I2C_VOL_MONITOR_ADDR 0x40 392 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 393 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 394 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 395 396 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 397 #ifndef CONFIG_SPL_BUILD 398 #define CONFIG_VID 399 #endif 400 #define CONFIG_VOL_MONITOR_IR36021_SET 401 #define CONFIG_VOL_MONITOR_INA220 402 /* The lowest and highest voltage allowed for LS1046AQDS */ 403 #define VDD_MV_MIN 819 404 #define VDD_MV_MAX 1212 405 406 /* 407 * Miscellaneous configurable options 408 */ 409 #define CONFIG_MISC_INIT_R 410 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 411 #define CONFIG_AUTO_COMPLETE 412 #define CONFIG_SYS_PBSIZE \ 413 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 414 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 415 416 #define CONFIG_SYS_MEMTEST_START 0x80000000 417 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 418 419 #define CONFIG_SYS_HZ 1000 420 421 /* 422 * Stack sizes 423 * The stack sizes are set up in start.S using the settings below 424 */ 425 #define CONFIG_STACKSIZE (30 * 1024) 426 427 #define CONFIG_SYS_INIT_SP_OFFSET \ 428 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 429 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 431 432 /* 433 * Environment 434 */ 435 #define CONFIG_ENV_OVERWRITE 436 437 #ifdef CONFIG_NAND_BOOT 438 #define CONFIG_ENV_IS_IN_NAND 439 #define CONFIG_ENV_SIZE 0x2000 440 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 441 #elif defined(CONFIG_SD_BOOT) 442 #define CONFIG_ENV_OFFSET (1024 * 1024) 443 #define CONFIG_ENV_IS_IN_MMC 444 #define CONFIG_SYS_MMC_ENV_DEV 0 445 #define CONFIG_ENV_SIZE 0x2000 446 #elif defined(CONFIG_QSPI_BOOT) 447 #define CONFIG_ENV_IS_IN_SPI_FLASH 448 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 449 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 450 #define CONFIG_ENV_SECT_SIZE 0x10000 451 #else 452 #define CONFIG_ENV_IS_IN_FLASH 453 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 454 #define CONFIG_ENV_SECT_SIZE 0x20000 455 #define CONFIG_ENV_SIZE 0x20000 456 #endif 457 458 #define CONFIG_CMDLINE_TAG 459 460 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 461 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 462 "e0000 f00000 && bootm $kernel_load" 463 #else 464 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 465 "$kernel_size && bootm $kernel_load" 466 #endif 467 468 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 469 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ 470 "14m(free)" 471 #else 472 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 473 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 474 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 475 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 476 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 477 "40m(nor_bank4_fit);7e800000.flash:" \ 478 "4m(nand_uboot),36m(nand_kernel)," \ 479 "472m(nand_free);spi0.0:2m(uboot)," \ 480 "14m(free)" 481 #endif 482 483 #include <asm/fsl_secure_boot.h> 484 485 #endif /* __LS1046AQDS_H__ */ 486