refactor(bl1): clean up bl2 layout calculation

Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logica

refactor(bl1): clean up bl2 layout calculation

Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.

Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent m

feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.

Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(tc): missing device regions in spmc manifest" into integration

fix(tc): missing device regions in spmc manifest

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I847c9ec13c3d40dd9de8cf374a81fc6d23a8864c

Merge changes from topic "nrd2_refactor" into integration

* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(n

Merge changes from topic "nrd2_refactor" into integration

* changes:
feat(docs): update maintainer list for neoverse_rd
refactor(neoverse-rd): remove soc_css.mk from common makefile
refactor(neoverse-rd): unify GIC SPI range macros
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
feat(rdn2): enable AMU if present on the platform
feat(rdn2): enable MTE2 if present on the platform
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
refactor(neoverse-rd): define naming convention for RoS macros
refactor(neoverse-rd): define naming convention for CSS macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): set mmap naming convention
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
refactor(neoverse-rd): refactor nrd_base_platform_def.h
refactor(neoverse-rd): header files for second generation platforms

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feat(docs): update maintainer list for neoverse_rd

Add Rohit.Mathew@arm.com to the maintainer list for Neoverse Reference
Design platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change

feat(docs): update maintainer list for neoverse_rd

Add Rohit.Mathew@arm.com to the maintainer list for Neoverse Reference
Design platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1b8a5714e2707162dd973d9a50215d0a6b622eb1

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Merge changes from topic "nrd1_refactor" into integration

* changes:
feat(rdn1edge): remove RD-N1-Edge from deprecated list
feat(sgi575): remove SGI-575 from deprecated list
fix(rdn1edge): upd

Merge changes from topic "nrd1_refactor" into integration

* changes:
feat(rdn1edge): remove RD-N1-Edge from deprecated list
feat(sgi575): remove SGI-575 from deprecated list
fix(rdn1edge): update RD-N1-Edge's changelog title
feat(neoverse-rd): add scope for RD-V1-MC
feat(neoverse-rd): add scope for RD-V1
feat(neoverse-rd): add scope for SGI-575
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for A75/V1/N1 platforms
feat(neoverse-rd): enable AMU if supported by the platform
refactor(neoverse-rd): clean-up nrd_plat_arm_def1.h file
refactor(neoverse-rd): remove unused defines from platform_def.h
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): rename definitions in nrd_ros_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_ros_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_def1.h file
refactor(neoverse-rd): rewrite CSS and RoS device mmap macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): migrate mmap entry from nrd_plat1.c
refactor(neoverse-rd): rename nrd_plat.c file
refactor(neoverse-rd): refactor nrd_soc_css_def.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def.h file
refactor(neoverse-rd): move away from nrd_base_platform_def.h
refactor(neoverse-rd): remove inclusion of nrd_base_platform_def.h
refactor(neoverse-rd): header files for first generation platforms
refactor(neoverse-rd): refactor scope for Neoverse RD platforms

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feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f6106

feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f61060
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by:

feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 with

refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935

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refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish

refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.

Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23

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refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
correspond

refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file

Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a

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feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value t

feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms

SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7

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feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could a

feat(rdn2): enable AMU if present on the platform

Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e

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feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
c

feat(rdn2): enable MTE2 if present on the platform

MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d

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feat(rdn1edge): remove RD-N1-Edge from deprecated list

As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: I6af06e7bd162747a

feat(rdn1edge): remove RD-N1-Edge from deprecated list

As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: I6af06e7bd162747aab72384185951d218b388ed3
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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refactor(neoverse-rd): move defines out of platform_def.h

Presently, the second generation platforms have direct references to CSS
and ROS specific addresses within RD-N2's platform header file
(pla

refactor(neoverse-rd): move defines out of platform_def.h

Presently, the second generation platforms have direct references to CSS
and ROS specific addresses within RD-N2's platform header file
(platform_def.h). Moreover, there are platform port specific macros
defined within platform_def.h To enhance organization and
appropriateness, relocate these definitions to nrd_css_def2.h,
nrd_ros_def2.h and nrd_arm_platform_def1.h files accordingly. Reuse
these definitions within the platform_def.h files as needed.

Additionally, remove reference to the unused PLAT_ARM_GICC_BASE macro
from the individual platform_def.h file.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9a237c3ae28d7e209188e2c37c8494b4a420ee83

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feat(sgi575): remove SGI-575 from deprecated list

As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: Ic9171a3e1bec198d9305e75a

feat(sgi575): remove SGI-575 from deprecated list

As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2

In the current setup, the base and size of the ROM, SRAM, and DRAM2
regions are directly defined in the nrd_fw_def2.h file for N2 CPU based

refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2

In the current setup, the base and size of the ROM, SRAM, and DRAM2
regions are directly defined in the nrd_fw_def2.h file for N2 CPU based
platforms. To enhance modularity and appropriateness, introduce macros
for these definitions in the respective css file (nrd_css_def2.h). While
the maximum sizes for ROM, SRAM, and DRAM2 are specified in the css
specification, the actual implementation sizes may vary. Consequently,
relocate the size macros to the platform-specific platform_def.h file
for individual platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I30988bf63cf942f68188a70697cc43cb6af96a9c

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refactor(neoverse-rd): define naming convention for RoS macros

As part of the refactoring for the second generation platforms,
introduce a naming convention for macros within nrd_ros_def2.h and
nrd_

refactor(neoverse-rd): define naming convention for RoS macros

As part of the refactoring for the second generation platforms,
introduce a naming convention for macros within nrd_ros_def2.h and
nrd_ros_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_ROS_<name>. Page table entry
macros are handled separately and are not part of this patch.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifcdc30b1c80b9848b793de2013095fc98d57bec6

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refactor(neoverse-rd): define naming convention for CSS macros

As part of the refactoring for the second generation of platforms,
introduce a naming convention for macros within nrd_css_def2.h and
n

refactor(neoverse-rd): define naming convention for CSS macros

As part of the refactoring for the second generation of platforms,
introduce a naming convention for macros within nrd_css_def2.h and
nrd_css_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_CSS_<name>. Page table entry
macros are handled separately and are not part of this patch.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib168320e12f06cd034342c011909896de463ab27

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refactor(neoverse-rd): refactor mmap macro for RoS device memory region

There are two macros that define ROS device memory map range and
attributes - one for local chip and the other for remote chip

refactor(neoverse-rd): refactor mmap macro for RoS device memory region

There are two macros that define ROS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I58eb65c2f046b6074f848f1448cd10a7dcc37f74

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refactor(neoverse-rd): refactor mmap macro for CSS device memory region

There are two macros that define CSS device memory map range and
attributes - one for local chip and the other for remote chip

refactor(neoverse-rd): refactor mmap macro for CSS device memory region

There are two macros that define CSS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip. While at it, rename the macro that defines
the memory map range and attributes for the remote shared RAM region.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ieddd5c81f6261490dbacb97160858903e56d327a

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refactor(neoverse-rd): set mmap naming convention

Presently, for the second generation platforms based on the N2 CPU,
macros related to page table entries lack a consistent naming
convention. This a

refactor(neoverse-rd): set mmap naming convention

Presently, for the second generation platforms based on the N2 CPU,
macros related to page table entries lack a consistent naming
convention. This absence may lead to potential mix-ups, such as css
definitions in soc files, and can contribute to decreased code clarity.
To address this, establish the following naming convention:

- NRD_CSS_<name>_MMAP for CSS related page table entries
- NRD_ROS_<name>_MMAP for ROS related page table entries

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I7bf1f9b0ddfd0444c802a23143de6a163f127731

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